Digital Output Code Research Articles

A 0.05 mm², 350 mV, 14 nW Fully-Integrated Temperature Sensor in 180-nm CMOS

In this brief, we present a fully-integrated ring-oscillator based CMOS temperature sensor for Internet-of-Things. Our design relies on a low-complexity PMOS-based sensing circuit to convert temperature into two sub-threshold biasing currents. These are then used to define two oscillation frequencies, whose ratio increases linearly with the temperature. Change in the frequency ratio is finally translated into a digital output code. The proposed sensor was fabricated in 180-nm CMOS technology. When powered at 350 mV, it can achieve an energy/conversion of 0.46 nJ in a conversion time of 33 ms. Moreover, it exhibits a measurement resolution of 0.27°C and a resolution figure-of-merit as low as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.034~{\mathrm{ nJ}}^\circ {\mathrm{ C}}^{2}$ </tex-math></inline-formula> .

S2ADC: A 12-bit, 1.25-MS/s Secure SAR ADC With Power Side-Channel Attack Resistance

When an ADC is converting a confidential analog signal into digital codes, it may expose a critical hardware security loophole. By exploiting the strong correlation between the ADC digital output codes and the ADC supply current waveforms, an attacker can perform an ADC power side-channel attack (PSA) to steal the sensitive A/D conversion results by tapping into the power supply of the ADC. In this regard, this article demonstrates two neural-network-based successive approximation register (SAR) ADC PSA methods and a 12-bit, 1.25-MS/s prototype SAR ADC with current-equalizer-based PSA protection. The first ADC PSA method employs multi-layer perceptron networks (MLP-PSA), while the second ADC PSA method uses convolutional neural networks (CNN-PSA). With the protection disabled, both MLP-PSA and CNN-PSA extract the A/D conversion results from the ADC supply current waveforms with >99% bit-wise accuracy. With the protection enabled, strong PSA-resistance against MLP-PSA is demonstrated. The same SAR ADC exhibits weaker PSA-resistance against CNN-PSA but generally provides significant protection of A/D conversion results.

A Simple Digital Thermometer

A digital thermometer is described in which the use of a modified null method has significantly reduced the impact of changes in the gain of the measuring path on the measurement accuracy. Autoregulation of the zero balance in the thermometer is performed using two types of pulse modulation: amplitude and pulse-width. For a 12-bit digital output code and a measurement resolution of 0.037°С, the integral value of the nonlinearity error did not exceed ±0.1°С in the temperature range of 100–250°С.

A CMOS Read-Out IC for Cyanobacteria Detection With 40 nApp Sensitivity and 45-dB Dynamic Range

This paper presents a low-power high-sensitivity CMOS read-out integrated circuit (ROIC) realized in a 0.13 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {\mu }\text{m}$ </tex-math></inline-formula> CMOS technology for cyanobacteria detection and monitoring with the current sensing capability of nano-ampere levels. The proposed CMOS ROIC consists of a current-conveyor transimpedance amplifier (CC-TIA) and a 9 bit successive approximation register (SAR) analog-to-digital converter (ADC). Electrically measured results of the proposed ROIC demonstrate 98.6 dB <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> transimpedance gain, 1.19 pA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\surd $ </tex-math></inline-formula> Hz noise current spectral density, and 1.8 mA current consumption from a single 1.2 V supply. The ROIC can precisely recover the digital output codes corresponding to the input current levels of 40 nA <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> ~ 7.2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$ </tex-math></inline-formula> A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> (i.e., 45 dB dynamic range). Optical experiments utilizing a 405 nm wavelength laser source and a low-cost PIN-photodiode confirm the fluorescence intensity with respect to the quantity of cyanobacteria, demonstrating that the normalized voltage (QD <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">655</sub> /QD <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">565</sub> ) is a linear function of the mcyD gene copy numbers. The CMOS ROIC chip occupies the area of 1.1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula> 2.0 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Single-Bin DFT-Based Digital Calibration Technique for CDAC in SAR ADCs

A 1024-point single-bin discrete Fourier transform (SBDFT)-based digital calibration technique is presented for high-performance, full-code successive approximation (SAR) analog-to-digital converters (ADCs). This proposed method can evaluate the radix error in capacitor-DAC (CDAC), which deviates from the designed value. Thus, the corrected digital output codes are generated to compensate the error, thereby reducing the harmonic distortion caused by capacitor mismatch. Moreover, the proposed algorithm adopts a recursive SBDFT computation rather than a conventional fast Fourier transform (FFT) computation methods because the simple hardware, which reduces hardware complexity and power consumption, can be achieved to calculate a certain bin in this work. The effective number of bits (ENOB) and signal-to-noise ratio (SNDR) can be enhanced by approximately 2 bits and 14.52 dB, respectively, on the basis of the simulation result of a 12-bit SAR ADC behavior model with 0.3% capacitor mismatch. The proposed SAR ADC is fabricated in TSMC $0.18~\boldsymbol {\mu }$ m 1P6M technology. Measurement results explain that the SNDR, spurious free dynamic range, and ENOB are 46.49/67.28 dB, 49.66/80.73 dB, and 7.43/10.88 bits before/after calibration, respectively, wherein the power supply is 3.3 V and the input signal frequency is 2 kHz with a sampling rate of 100 kS/s.

An Ultrafast Multibit/Stage Pipelined ADC Testing and Calibration Method

A novel ultrafast and low-cost pipelined analog-to-digital converter (ADC) testing and calibration method is proposed. The ADC nonlinearities are modeled as segmented parameters with interstage gain errors. During the test phase, a pure sine wave is sent as input and the model parameters are estimated from the output data with the system identification method. Significantly, fewer samples are required when compared to traditional histogram testing. The modeled errors are then removed from the digital output codes during the calibration phase. Extensive simulations have been run to verify the correctness and robustness of the proposed method. With just 4000 samples, a 12-bit ADC can be accurately tested and calibrated to achieve less than 1 least significant bit (LSB) integral nonlinearity (INL). Measurement results show that the ADC effective number of bits (ENOB) is improved from 9.7to 10.84 bits and the spurious-free dynamic range (SFDR) is improved by 20 dB after calibration. The chip is fabricated in 40-nm technology and consumes 10.71 mW at a sampling rate of 125 MS/s.

Surge protection design with surge-to-digital converter for microelectronic circuits and systems

A surge protection design with surge-to-digital converter is proposed to provide the surge protection for microelectronic products with more flexible applications. The proposed surge-to-digital converter can transfer the occurrences of the surge events into digital output codes by classifying the voltage levels of surge events. It can be used to avoid unwanted power-on reset action, redundant power consumption, or unexpected soft errors, achieving the stability improvement of microelectronic systems. With this surge-to-digital converter, a surge protection design against a surge test of 25 V can clamp the peak voltage of VDD from 22.2 V to 5.6 V. The proposed converter has been verified in a 0.18-μm CMOS process.

Design of Fully-Printed Organic Circuits on Plastic Foils for Wireless Systems

This work is dedicated to the design of fully-printed organic circuits on plastic foils. Passive ring mixers, diode-based active envelope detectors and a flash analog to digital converter are presented. The circuits based on N-type and P-type transistors are manufactured using an organic sheet-to-sheet process in ambient air. The fully-printed active envelope detector based on nine transistors and a capacitance shows better performance than the one described in the literature. The detector is able to perform with different waveforms of AM-modulated signals under a +/−20 V supply voltage for a 40 kHz carrier frequency. It still performs correctly for a modulation depth of 10%. The passive ring mixers only use four transistors and are able to mix a 5 Hz modulating wave with carrier frequencies from 100 Hz until 2 kHz. The analog to digital converter is designed with 45 transistors and four screen-printed carbon resistors for a total surface of 760 mm2. The circuit converts a 20 Hz analog input signal into a digital 2-bit output code under a +/−20 V supply voltage. All presented circuits are simulated before the realization and their measurement is performed in ambient air.

Energy‐efficient successive‐approximation‐register based capacitive interface for pressure sensors

A novel energy-efficient 8 bit 2.78 kS/s capacitance-to-digital converter (CDC) interface for capacitive pressure sensors is presented. A new direct-capacitance-comparison technique (DCCT) is proposed and employed together with a successive approximation register (SAR) algorithm to resolve the sensor capacitance by, directly, comparing it with an on-chip binary-weighted capacitive digital-to-analogue converter (DAC) array. An offset DAC array compensates for the sensor rest and parasitic capacitances, accordingly, the interface gives a dynamically zoomed digital-output code that corresponds only to the sensor capacitance change. The full-scale input capacitance of the CDC is easily adjustable to interface to a wide range of sensors. The proposed 8 bit SAR-based CDC is designed and simulated using 0.18 μm standard CMOS technology. The CDC exhibits a capacitance sensing range from 4 to 6 pF, provides a resolution and linearity of 7.26 and 8.2 bit, respectively. It achieves a figure-of-merit of 1.8 pJ/step at 1.4 V supply and 36 μs conversion time. Compared with the state-of-the-art implementations with similar performance.

Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current

Analysis of an open-loop time amplifier shows good agreement between measurements and calculations on the time gain, distortion of time gain, and rms noise and offset of output time difference. The time amplifier is based on the slew rate control method. It achieves a large time gain up to 120 and a wide range of input time difference up to 2 ns. The circuit consists of two precharged capacitors and current sources, where one capacitor is discharged at a fast slew rate during the time interval of the input time difference and then both capacitors are discharged at the same slow slew rate. The time gain is simply determined by the ratio of two bias current values. The proposed time amplifier is followed by an 8-bit TDC to obtain the digital output code. The time gain distortion caused by channel length modulation is less than 1.6% for the input time difference larger than 100 ps. The time offset and the rms noise of output time difference are inversely proportional to the smaller bias current. The rms noise is dominated by the noise of the comparator reference voltage. The time amplifier and TDC consume 0.36 mW and 1 mW, respectively, at 1.2 V supply in a 0.13 μm CMOS process.

Pulse shrinking time-to-digital converter for UWB application

A kind of architecture of Time-to-Digital Converter (TDC) for Ultra-WideBand (UWB) application is presented. The proposed TDC is based on pulse shrinking, and implemented in a Field Programmable Gate Array (FPGA) device. The pulse shrinking is realized in a loop containing two Programmable Delay Lines (PDLs) or a two-channel PDL. One line (channel) delays the rising edge and the other line (channel) delays the falling edge of a circulating pulse. Delay resolution of PDL is converted into a digital output code under known conditions of pulse width. This delay resolution measurement mechanism is different from the conventional time interval measurement mechanism based on pulse shrinking of conversion of unknown pulse width into a digital output code. This mechanism automatically avoids the influence of unwanted pulse shrinking by any circuit element apart from the lines. The achieved relative errors for four PDLs are within 0.80%-1.60%.

New 4-Bit Transient-to-Digital Converter for System-Level ESD Protection in Display Panels

A new on-chip 4-bit transient-to-digital converter for system-level electrostatic discharge (ESD) protection design is proposed. The proposed converter is designed to detect ESD-induced transient disturbances and transfer different ESD voltages into digital codes under system-level ESD tests. The experimental results in a 0.13- μm CMOS integrated circuit with 1.8-V devices have confirmed the detection function and digital output codes. The proposed on-chip transient-to-digital converter can be codesigned with firmware operations to effectively enhance immunity of display systems against system-level ESD stresses.

A Wireless Microbial Fuel Cell Voltage Data Acquisition System Based on MSP430F149

A wireless data acquisition system based on MSP430F149 is developed for the measurement of microbial fuel cells’ voltage. The main function of this system is to convert the analog input voltage into digital output code, process the digital code, and transfer the data through the GSM network or the USB interface. The core of the data acquisition device is a 16-bit general purpose Texas Instruments ultralow-power microcontroller MSP430F149. As the voltage of a microbial fuel cell is very low, the A/D converter circuit is specifically designed for high precision and high accuracy. A real-time clock is used to achieve timing measurement and the time interval can be set to meet demands. The data collected is transferred through the GSM network. Besides, a Windows environment application developed with Visual C++ can be used to access the data stored in the flash memory through USB interface.

A time-to-digital-converter-based CMOS smart temperature sensor

A time-to-digital-converter-based CMOS smart temperature sensor without a voltage/current analog-to-digital converter (ADC) or bandgap reference is proposed for high-accuracy portable applications. Conventional smart temperature sensors rely on voltage/current ADCs for digital output code conversion. For the purpose of cost reduction and power savings, the proposed smart temperature sensor first generates a pulse with a width proportional to the measured temperature. Then, a cyclic time-to-digital converter is utilized to convert the pulse into a corresponding digital code. The test chips have an extremely small area of 0.175 mm/sup 2/ and were fabricated in the TSMC CMOS 0.35-/spl mu/m 2P4M process. Due to the excellent linearity of the digital output, the achieved measurement error is merely -0.7/spl sim/+0.9/spl deg/C after two point calibration, but without any curvature correction or dynamic offset cancellation. The effective resolution is better than 0.16/spl deg/C, and the power consumption is under 10 /spl mu/W at a sample rate of 2 samples/s.

Hybrid clamping in NTSC digital video equipment

Two algorithms that are suitable for deriving the blanking level of a National Television Systems Committee (NTSC) composite video signal are described. One method consists of averaging digitized color-burst samples taken from successive scan lines. A second method involves processing a group of samples taken from a single burst interval. Either algorithm used in a hybrid clamping arrangement results in automatic drift compensation and the ability to tie the back porch or sync tip to a predetermined digital output code. This aids in matching the analog signal to the input of the analog-to-signal (A/D) converter for maximum signal-to-noise ratio (SNR). In analyzing the effect of additive noise and timing jitter, it was found that both algorithms are, generally, more vulnerable than a conventional keyed clamper.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High‐linearity and high‐speed CMOS 1‐chip A/D, D/A converters. all‐digital linearity error correction (LECS)

AbstractThis paper describes an all‐digital linearity error correction (LECS) method for A/D and D/A converters, and presents the design and performance of single‐chip CMOS LSI converters utilizing this new technique.In general, the deterioration of converter accuracy is caused by discontinuity changes (jumps) of the converter characteristics due to component tolerances in the weighting network. The proposed correction method is based on a design ensuring that only negative jumps occur which are then eliminated digitally by a shifting of digital output (input) codes. Since this method does not require analog circuits, the number of noise sources is minimum and high reliability is achieved by eliminating physical trimming.Experimental CMOS converters have been realized utilizing the proposed method; the D/A converter provides an S/N of 92 dB at 150 ksps, and 87 dB is achieved by the A/D at 78 ksps. Thus, the possibility of realizing high‐quality audio converters by MOS process technology has been demonstrated.

Full-speed testing of A/D converters

Improved computer-aided analog-to-digital converter (ADC) characterization methods based on the code density test and spectral analysis using the fast Fourier transform are described. The code density test produces a histogram of the digital output codes of an ADC sampling a known input. The code density can be interpreted to compute the differential and integral nonlinearities, gain error, offset error, and internal noise. Conversion-rate and frequency-dependent behavior can also be measured.