Digital Hardware Systems Research Articles

Direction-of-arrival estimation for acoustic signals based on direction-dependent parameter tuning of a bioinspired binaural coupling system

Bioinspired methods for sound source localization offer opportunities for resource reduction as well as concurrent performance improvement in contrast to conventional techniques. Usually, sound source localization requires a large number of microphones arranged in irregular geometries, and thus has high resource requirements in terms of space and data processing. Motivated by biology and using digital signal processing methods, an approach that adapts the coupled hearing system of the fly Ormia ochracea with a minimally distant two-microphone array is presented. Despite its physiology, the fly is able to overcome physical limitations in localizing low-frequency sound sources. By exploiting the filtering effect of the coupling system, the direction-of-arrival of the sound is determined with two microphones at an intermediate distance of 0.06 m. For conventional beamforming algorithms, these physical limitations would result in degraded localization performance. In this work, the bioinspired coupling system is analyzed and subsequently parameterized direction-sensitive for different directions of incidence of the sound. For the parameterization, an optimization method is presented which can be adopted for excitation with plane as well as spherical sound wave propagation. Finally, the method was assessed using simulated and measured data. For 90% of the simulated scenarios, the correct direction of incidence could be determined with an accuracy of less than 1∘ despite the use of a minimal distant two-microphone array. The experiments with measured data also resulted in a correct determination of the direction of incidence, which qualifies the bioinspired method for practical use in digital hardware systems.

COVID-19 Communication and Media: The First Pandemic of the Digital Age

This issue of American Behavioral Scientist marshals case studies of online media platforms such as Zoom, YouTube, and Twitter and digital hardware systems such as virtual reality technology to assess the often unexpected interactions between the pandemic and digital technologies. The issue leads with a case study of Zoom to examine the largely successful efforts which Zoom made in the wake of the pandemic to resolve unanticipated privacy and security problems afflicting the suddenly ubiquitous and indispensable platform. Subsequently, the issue charts the growing tensions between competing proprietary and open-source institutional logics during the pandemic. In the next section, articles consider the spread of covid-related information on YouTube and news outlets to take a comparative angle of vision both internationally and in terms of the dynamics of media production and reception in different cultural and societal environments. Variation is also key to the articles in the last section where research focuses on persistent digital usage gaps. Here the articles touch on the socioeconomic factors driving differentiated knowledge about the pandemic, as well as the relatively low uptake of digital technologies among older adults in housing facilities. Finally, we also learn about the effect of the social isolation and anxieties of the pandemic on the uptake of a new form of digital hardware, virtual reality equipment. To conclude this discussion of media during the first pandemic of the digital age, the issue closes with an eye to visualizations tools needed for the future. These contributions take the measure of how the pandemic intersected with digitized communications and media in varied and, at times, unequal ways, as well as lessons applicable to future crises.

Mixed‐Precision Continual Learning Based on Computational Resistance Random Access Memory

Artificial neural networks have acquired remarkable achievements in the field of artificial intelligence. However, it suffers from catastrophic forgetting when dealing with continual learning problems, i.e., the loss of previously learned knowledge upon learning new information. Although several continual learning algorithms have been proposed, it remains a challenge to implement these algorithms efficiently on conventional digital systems due to the physical separation between memory and processing units. Herein, a software–hardware codesigned in‐memory computing paradigm is proposed, where a mixed‐precision continual learning (MPCL) model is deployed on a hybrid analogue–digital hardware system equipped with resistance random access memory chip. Software‐wise, the MPCL effectively alleviates catastrophic forgetting and circumvents the requirement for high‐precision weights. Hardware‐wise, the hybrid analogue–digital system takes advantage of the colocation of memory and processing units, greatly improving energy efficiency. By combining the MPCL with an in situ fine‐tuning method, high classification accuracies of 94.9% and 95.3% (software baseline 97.0% and 97.7%) on the 5‐split‐MNIST and 5‐split‐FashionMNIST are achieved, respectively. The proposed system reduces ≈200 times energy consumption of the multiply‐and‐accumulation operations during the inference phase compared to the conventional digital systems. This work paves the way for future autonomous systems at the edge.

Pulse coding off-chip learning algorithm for memristive artificial neural network

Memristive neural network has attracted tremendous attention since the memristor array can perform parallel multiply-accumulate calculation (MAC) operations and memory-computation operations as compared with digital CMOS hardware systems. However, owing to the variability of the memristor, the implementation of high-precision neural network in memristive computation units is still difficult. Existing learning algorithms for memristive artificial neural network (ANN) is unable to achieve the performance comparable to high-precision by using CMOS-based system. Here, we propose an algorithm based on off-chip learning for memristive ANN in low precision. Training the ANN in the high-precision in digital CPUs and then quantifying the weight of the network to low precision, the quantified weights are mapped to the memristor arrays based on VTEAM model through using the pulse coding weight-mapping rule. In this work, we execute the inference of trained 5-layers convolution neural network on the memristor arrays and achieve an accuracy close to the inference in the case of high precision (64-bit). Compared with other algorithms-based off-chip learning, the algorithm proposed in the present study can easily implement the mapping process and less influence of the device variability. Our result provides an effective approach to implementing the ANN on the memristive hardware platform.

Application of Open-Hardware-Based Solutions for Rapid Transition From Stationary to the Remote Teaching Model During Pandemic.

Contribution: While research indicates usefulness of remote laboratories in teaching of digital hardware systems, their main application is to complement stationary classes. This work presents a low-cost, scalable architecture that supports rapid transformation of teaching to a model based solely on remote access mechanisms. Background: Adaptation of online laboratory solutions from the literature to en-masse teaching of digital circuits is time-consuming and expensive. Solutions that permit cheap and rapid conversion of courses to remote environments seem to be of high value, especially when social distancing renders direct teaching impossible. Intended Outcomes: Demonstration of a flexible and cheap architecture that permits rapid transformation of digital circuits laboratories to the remote environment. Validation of system's performance and usefulness on a large group of students. Application Design: Remote digital circuits laboratories from the literature are designed to complement stationary classes. For successful teaching during pandemic, a low-cost, flexible, and efficient solution to online laboratory based on commonly available technologies is required. Findings: The proposed remote laboratory architecture enables rapid conversion of on-site teaching to online model, while supporting in-situupgrades and functionality enhancements. The presented solution proved to be a convenient substitute for conventional laboratories during pandemic.

Designing Electronic Systems Using SystemC and SystemC–AMS

Current trends in the design of electronic systems is the use of embedded systems based on systems on a chip (System-on-Chip (SoC)) or (VLSI SoC). The paper discusses the design features of electronic systems on a chip using the SystemC design and verification language. For the joint design and simulation of digital systems hardware and software, seven modeling levels are presented and discussed: executable specification, disabled functional model, temporary functional model, transaction-level model, behavioral hardware model, accurate hardware model, register transfer model. The SystemC design methodology with functional verification is presented, which reduces development time.The architecture of the SystemC language and its main components are shown. The expansion of SystemC–AMS for analog and mixed analog-digital signals and its use cases in the design of electronic systems are considered. Computing models are discussed: temporary data stream (TDF), linear signal stream (LSF) and electric linear networks (ELN). The architecture of the SystemC–AMS language standard is shown and examples of its application are given. It is shown that the design languages SystemC and SystemC–AMS are widely used by leading developers of computer-aided design systems for electronic devices.

Comparative performance analysis of FPGA-based MAC unit using non-conventional number system in TVL domain for signal processing algorithm

Today, the complication of binary digital hardware system is progressively growing. Due to this fact, new methodologies for efficiently describing and realising the digital systems are explored in this paper. Multi-valued logic methodology offers a few preferences over existing binary digital system. One of the well-known multi-valued logic systems is ternary value logic (TVL) system. It is seen that all kind of digital signal processing (DSP) algorithms widely use multiply-accumulate (MAC) operation for superior digital processing system. To implement high performance DSP algorithms MAC unit is used extensively. In current scenario, it is seen that non-conventional, non-binary number system-based architecture is also exhibited better performance. The example of such non-conventional, non-binary number systems is ternary residue number systems (TRNSs) and double base ternary number system (DBTNS). Here, a comparative study is made on performance analysis of MAC unit using various non-conventional, non-binary number system. All the architecture is mapped on FPGA for analysis its performance.

Comparative performance analysis of FPGA-based MAC unit using non-conventional number system in TVL domain for signal processing algorithm

Today, the complication of binary digital hardware system is progressively growing. Due to this fact, new methodologies for efficiently describing and realising the digital systems are explored in this paper. Multi-valued logic methodology offers a few preferences over existing binary digital system. One of the well-known multi-valued logic systems is ternary value logic (TVL) system. It is seen that all kind of digital signal processing (DSP) algorithms widely use multiply-accumulate (MAC) operation for superior digital processing system. To implement high performance DSP algorithms MAC unit is used extensively. In current scenario, it is seen that non-conventional, non-binary number system-based architecture is also exhibited better performance. The example of such non-conventional, non-binary number systems is ternary residue number systems (TRNSs) and double base ternary number system (DBTNS). Here, a comparative study is made on performance analysis of MAC unit using various non-conventional, non-binary number system. All the architecture is mapped on FPGA for analysis its performance.

Digital Hardware Implementation of Gaussian Wilson–Cowan Neocortex Model

Hardware implementation of biological neural models can help in better understanding of the brain functionality, implementing cognitive tasks, and also studying the brain diseases. Gaussian Wilson–Cowan model as one of the well-known population-based models represents neuronal functionality in neocortex. In this paper, Gaussian Wilson–Cowan model is investigated in terms of its digital implementation feasibility. Digital model is proposed for the Gaussian Wilson–Cowan and examined from dynamical and timing behavior point of view. The evaluations indicate that the digitized model is able to reproduce the dynamical bifurcations as the original model is capable of. An efficient digital hardware system is given for the proposed model with minimum required resources using Verilog Hardware Description Language. Digital architectures are physically implemented on an Altera FPGA board. Experimental results show that the proposed circuits take maximum 2% of the available resources of a Stratix Altera board. In addition, static timing analysis indicates that the circuits can work in a maximum frequency of 244 MHz.

Sign backpropagation: An on-chip learning algorithm for analog RRAM neuromorphic computing systems

Currently, powerful deep learning models usually require significant resources in the form of processors and memory, which leads to very high energy consumption. The emerging resistive random access memory (RRAM) has shown great potential for constructing a scalable and energy-efficient neural network. However, it is hard to port a high-precision neural network from conventional digital CMOS hardware systems to analog RRAM systems owing to the variability of RRAM devices. A suitable on-chip learning algorithm should be developed to retrain or improve the performance of the neural network. In addition, determining how to integrate the periphery digital computations and analog RRAM crossbar is still a challenge. Here, we propose an on-chip learning algorithm, named sign backpropagation (SBP), for RRAM-based multilayer perceptron (MLP) with binary interfaces (0, 1) in forward process and 2-bit (±1, 0) in backward process. The simulation results show that the proposed method and architecture can achieve a comparable classification accuracy with MLP on MNIST dataset, meanwhile it can save area and energy cost by the calculation and storing of the intermediate results and take advantages of the RRAM crossbar potential in neuromorphic computing.

Fault-tolerant digital systems development using triple modular redundancy

The paper presents a fault-tolerant digital system design and development strategy for high reliability hardware architectures implementation. Starting from the general consideration that digital hardware systems play a key role in a large scale of control systems implementation, a triple modular redundancy (TMR) solution it is proposed for development. For this reason, the well-known 1 bit majority voter configuration has been extended and generalized to the full control bus of a digital control system. Computer simulations show that the proposed hardware solution fulfills in all the theoretical expectations and it can be used for experimental tests and implementation. The presented design solution and conclusions are well suited to generalization for a wide range of fault-tolerant digital systems development ranging from reliable and safety servo control applications up to high reliability parallel and distributed computing hardware architectures.

Assessment of vegetative, neurohumoral and psycho-emotional disorders in patients with atopic dermatitis of varying severity

Goal of the study. evaluation of psycho-vegetative disorders in patients with atopic dermatitis, and the determination of their influence on the severity of the disease. Material and methods. The study involved 72 patients with atopic dermatitis aged 18 to 46 years (men - 41, women - 31). The control group, similar in age and sex characteristics, and 30 healthy volunteers. All patients underwent an individual computer study psychophysiological and emotional state of a human body with a digital telemetry hardware and software system - analyzer of biorhythms «Omega-M» Scientific-production company «Dynamics» (Saint-Petersburg). Evaluates the performance of the autonomic, neurohumoral and central regulation, as well as the integral indicators of the functional state of the organism. Quality of life assessed by questionnaire DLQI (dermatology life quality index), the severity of the disease was determined by the index SCORAD (scoring atopic dermatitis). Results. Autonomic disorders were diagnosed in 75.0% of patients (54/72), represented mainly sympathicotonia and centralization of heart rhythm. Neurodynamic methods and fractal analysis of cardiac rhythm disorders of neurohumoral regulation and psycho-emotional diagnosed respectively in 69.4% (50/72) and 76.6% (53/72) of patients with atopic dermatitis. A moderate correlation between the severity of the disease and some indicators (IV, IVE, VR, C1, D1) showing violations of the vegetative and central regulation (0,25 < IrsI < 0,75).

Simulation alternatives for the verification of networked cyber-physical systems

Several embedded system applications are used to control physical processes thus leading to the concept of Cyber-Physical System. Sensing, computation and actuation are combined by involving a set of highly heterogeneous components, i.e., digital and analog hardware, software, energy sources, and external physical systems (e.g., a room to be heated, a mechanical component). Moreover, we see the growing use of networks to connect several sub-systems in a more efficient way; this contributes to introduce a further level of heterogeneity due to the presence of messages exchanged over communication channels. All these aspects should be taken into account in the design process to find highly optimized solutions; in particular, simulation is a key technique for their verification. However, the heterogeneity of components, together with the presence of the network, forces to adopt complex and slow co-simulation techniques to carry on the simulation of the entire system.This work aims at proposing SystemC as unified framework to model and simulate Networked Cyber-Physical Systems. Concerning the modeling of continuous-time components and a specific class of discrete-time components, the different Models of Computation provided by the Analog/Mixed-Signal (AMS) extension of SystemC are used. Regarding the network, SystemC and the SystemC Network Simulation Library are used to model communications at different abstraction levels. The approach is validated by considering a networked control system. First, the accuracy and speed of SystemC simulation is compared to Matlab/Simulink simulation. Second, different simulation alternatives are compared to co-simulation. Finally, we show that the simulation speed-up achieved by all-SystemC modeling allows to explore several design alternatives and the accurate modeling of the communication network can improve the design of the controller.

Theory and experiment research for ultra-low frequency maglev vibration sensor.

A new maglev sensor is proposed to measure ultra-low frequency (ULF) vibration, which uses hybrid-magnet levitation structure with electromagnets and permanent magnets as the supporting component, rather than the conventional spring structure of magnetoelectric vibration sensor. Since the lower measurement limit needs to be reduced, the equivalent bearing stiffness coefficient and the equivalent damping coefficient are adjusted by the sensitivity unit structure of the sensor and the closed-loop control system, which realizes both the closed-loop control and the solving algorithms. A simple sensor experimental platform is then assembled based on a digital hardware system, and experimental results demonstrate that the lower measurement limit of the sensor is increased to 0.2 Hz under these experimental conditions, indicating promising results of the maglev sensor for ULF vibration measurements.

Digital control system design and analyses of a 3-phase bearingless induction motor

The overall conguration of a magnetic suspension decoupling control system is designed to realize the reliable digital control of a 3-phase bearingless induction motor whose rotor windings are not pole-specic. Based on a digital signal processor complementary metal-oxide semiconductor chip, the digital control hardware and software systems are analyzed and designed. In this paper, the calculation and regulation of the motor rotational speed, correction and regulation methods of the radial displacements, calculation and compensation algorithms of the unilateral magnetic pulls, induction compensation algorithm of the eective suspension control current, current regulation, and space-vector pulse width modulation algorithms, are presented in detail. The experimental results verify the feasibility and practicability of the designed decoupling digital control system of the 3-phase bearingless induction motor.

Development of Digital Vehicle Information Terminal Hardware System

This paper briefly introduces remote monitoring system of the electric vehicle, and digital hardware system of vehicle information terminal development. This system consists of the core processing module, power supply module, CAN communication module, serial communication module, communication module and 3G communication module. All modules work together, they realize the function of remotely gathering data of vehicle under various operating conditions together, and diagnose fault through the analysis of the fault code and the diagnosis.

Synthesizing VHDL from Activity Models in UML 2

ABSTRACTThis document describes a synthesis technology that generates structural VHDL code from models describing the flow of data required to perform algorithms operating on bit‐blocks. The models are built using restricted activity diagrams in the Unified Modeling Language version 2. The code generator is developed using Acceleo, a technology to implement transformations from models to text. The technology described in this paper exploits the principles of object orientation and model‐driven engineering. The primary aim is to improve productivity and alleviate complexity during the design of digital hardware systems that implement demanding operations used by a wide variety of computing devices. The use of the technology is illustrated with the generation of VHDL code from models describing a block cipher algorithm. Copyright © 2012 John Wiley & Sons, Ltd.

Estabilizador de sistemas de potencia digital aplicado a uma unidade geradora da uhe de Tucurui

Este trabalho apresenta o desenvolvimento e resultados de testes de campo de um estabilizador de sistemas de potência (ESP) digital, destinado ao amortecimento de oscilações eletromecânicas em sistemas interligados. Os testes experimentais foram efetuados em uma das unidades hidrogeradoras, de 350 MVA, da UHE de Tucuruí. A lei de controle amortecedor do ESP digital foi embarcada em um sistema de hardware baseado em um controlador digital de sinais (DSPIC 30f5011). A estrutura da lei de controle é na forma canónica RST, de tempo discreto, sendo os parâmetros do controlador calculados através da técnica de deslocamento radial de pólos. Para fins de projeto, a dinâmica da planta, no ponto de operação considerado, foi representada por um modelo paramétrico, o qual foi estimado a partir de dados medidos em campo. Os resultados experimentais mostraram um excelente desempenho do ESP digital no amortecimento de um dos modos eletromecânicos observável na UHE de Tucuruí.

The Liberty Simulation Environment

In digital hardware system design, the quality of the product is directly related to the number of meaningful design alternatives properly considered. Unfortunately, existing modeling methodologies and tools have properties which make them less than ideal for rapid and accurate design-space exploration. This article identifies and evaluates the shortcomings of existing methods to motivate the Liberty Simulation Environment (LSE). LSE is a high-level modeling tool engineered to address these limitations, allowing for the rapid construction of accurate high-level simulation models. LSE simplifies model specification with low-overhead component-based reuse techniques and an abstraction for timing control. As part of a detailed description of LSE, this article presents these features, their impact on model specification effort, their implementation, and optimizations created to mitigate their otherwise deleterious impact on simulator execution performance.

Design of digital hardware system for pulse signals.

In this study, we have developed the digital hardware system which performs signal processing necessary for the filtering to eliminate noises by inputting pulse wave signals from the sensor group. With a view to obtain clinically effective information, we analyzed structural elements of pulse waveform and, thus, conducted a systematic classification. What is more, we performed the modeling of the digital filter by using the Steiglitz-McBride iteration method in order to get the same results with output signals coming out of an galvanometer of analog type of existing Pulse diagnosis system with input signals entering into galvanometer and coming out of the amp group of the Pulse diagnosis system.