Digital Front-ends Research Articles

Least-Squares Equalizer Demonstrations Using a Full-Digital Bandwidth Sub-Nyquist-Sampled Wideband Beamformer on an RFSoC

The radio frequency system-on-a-chip (RFSoC) has recently become a viable candidate for completely replacing traditional analog and digital front ends, facilitating the development of wideband phased-array systems where the modern-day RFSoC takes the comprehensive, dominate role in the architecture of the array. Wideband phased-array systems require high-fidelity compensation techniques capable of correcting imbalanced and dispersive channel effects for effective beamforming. This article provides solutions to these challenges by designing a wideband equalizer for a sub-Nyquist-sampled 1.6-GHz <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> -band phased-array system implemented on a Xilinx 8-channel RFSoC, whose analog-to-digital converters (ADC) operate at 4 gigasamples per second. In brief, an RFSoC is a unique, state-of-the-art, highly integrated device that incorporates a field programmable gate array, high-speed ADCs and digital-to-analog converters with a system-on-a-chip architecture on a single monolithic device. By definition, true time delay beamsteering can be implemented digitally via a combination of integer-sample delays and fractional-sample delay finite impulse response filters. By modifying the filter structure of the fractional-sample delay filter bank to support complex coefficients, channel equalization is integrated with fractional-sample delay filters to mitigate undesired channel effects. For the first time, to the best of our knowledge, this article has developed an equalizer design methodology for an uncalibrated 8-element RFSoC-based sub-Nyquist-sampled wideband beamformer. Lab measurements confirm efficacy.

A Prototype Digital Radiometer for Noise Metrology Applications: A Metrology-Grade Digital Radiometer

Receiver technology has evolved significantly over the past decades. A variety of receiver architectures have been developed for addressing different applications <xref ref-type="bibr" rid="ref1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]</xref> . In general, more and more analog components have been replaced by their digital counterparts. The recent advance in ultrafast sampling digitizers has even enabled digital front ends, completely eliminating analog down-conversion <xref ref-type="bibr" rid="ref2" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[2]</xref> , <xref ref-type="bibr" rid="ref3" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[3]</xref> . Although the state-of-art direct RF-sampling systems are particularly attractive and promising for new generations of communications, challenges of high power consumption and high cost hinder their current feasibility and applications <xref ref-type="bibr" rid="ref3" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[3]</xref> .

Initial Access through Beamforming in mmWave

Future Wi-Fi, 5G Cellular and millimetre-wave (mmWave) will depend on highly directional links in order to prevail over exuberant path loss experienced in the different bands of frequency. However, in order to establish these type of links, the receiver and transmitter need mutual discovery which will result in high energy consumption and large latency. The proposed work deals with reduction of energy consumption and latency significantly with the help of a fully digital front-end. The digital beamformer will receive the spatial samples within a shot, from all directions. However, in analog front-ends, sampling is allowed for beamforming in one particular direction at a time resulting in the time period in which the mobile is “on” for longer. This will result in an increase in energy consumption by more than four times for the analog front-end when compared with digital front-ends, taking into consideration the antenna arrays’ size. However, from the power consumption point of view, using a fully digital beamforming post beam discovery is not recommended. Hence in order to overcome this drawback, a digital beamformer coupled with a 4-bit A-D convertor with low resolution is proposed. The use of low resolution will decrease the power consumption such that it is in the same zone as that of analog beam forming while it is possible to make use of the fully digital beamforming spatial multiplexing capabilities resulting in improved energy efficiency and reduced discovery latency.

Spectral estimation for long‐term evolution transceivers using low‐complex filter banks

For mobile user equipments (UEs), a careful power management is essential. Despite this fact, quite an amount of energy is wasted in today's UEs’ analogue (AFEs) and digital frontends (DFEs). These are engineered for extracting the wanted signal from a spectral environment defined in the corresponding communication standards with their extremely tough requirements. These requirements define a worst-case scenario still ensuring reliable communication. In a typical receiving process the actual requirements can be considered as less critical. Knowledge about the actual environmental spectral conditions allows to reconfigure both frontends to the actual needs and to save energy. In this paper, the authors present a highly efficient generic spectrum sensing approach, which allows to collect information about the actual spectral environment of an UE. This information can be used to reconfigure both the AFE and DFE, thus endowing them with increased intelligence. A low-complex multiplier free filter bank extended by an efficient power calculation unit will be introduced. They also present simulation results, which illustrate the performance of the spectrum sensing approach and a complexity comparison with different well-known implementations is given. Furthermore, estimates on the chip area and power consumption based on a 65 nm CMOS technology database are provided, considering the Smarti4G chip as a reference.

DIFFS: A Low Power, Multi-Mode, Multi-Standard Flexible Digital Front-End for Sensing in Future Cognitive Radios

Cognitive Radios provide communication devices with the flexibility to adjust to varying network and channel conditions. For this to be fully realizable spectrum sensing and signal reception have to happen simultaneously and have to require as little power as necessary to function in handheld devices. This work argues for the need of flexible digital-front ends as indispensable building block, able to perform control operations over the analog front-end and to perform sensing and synchronization procedures without the need of power consuming baseband processors. A low power, reconfigurable digital front-end that supports concurrent synchronization and sensing of high-throughput wireless standards is presented. Multiple operating modes, useful for various communication standards, such as LTE, WLAN and DVB-T are introduced and analyzed. The digital front-end has been implemented in 65 nm CMOS technology resulting in a chip area of 6.4 mm2. Fine grain clock gating allows synchronization at 4 mW and sensing at 7 mW power consumption. Experiments in combination with a reconfigurable analog front-end show that a 1.7 GHz wide frequency band can be scanned based on energy detection in an exceptionally low time window of 10 ms while consuming 13 mW power and that coarse energy detection can speed-up the sensing process. Furthermore, advanced feature detection for DVB-T and LTE signals is implemented and measured. Low power sensing of DVB-T signals shows that a target false alarm rate of 10 % and a detection probability of 90 % at an input power level of?106 dBm while consuming 7 mW power are possible. Synchronization-aided FFT-based LTE sensing with leakage cancellation was experimentally validated for various bandwidths showing a power consumption of maximum 20 mW.

Advanced techniques on multirate signal processing for digital information processing

Multirate signal processing has become a key topic enabling efficient techniques for digital information processing in a variety of applications such as digital transceivers s for wireless as well as satellite communication systems, digital broadcasting, high performance audio and video, multimedia services, and signal compression. In the wireless communications arena, multirate signal processing techniques provide effective means to implement flexible receiver channelisation filtering and sampling rate conversion for software and cognitive radio digital frontends. As far as multimedia signal processing is concerned, recent techniques relying on multirate filter banks have resulted in improved subband coding techniques reflected in the JPEG-2000 multimedia standard, as well as on some modern audio compression formats such as MP3, AAC3 and ATRAC3plus, to cite but a few.

ADC-Based Serial I/O Receivers

Digital receiver frontends have emerged as a possible solution for the next-generation serial I/O receiver design in advanced CMOS technologies. The challenge is to achieve low power dissipation so that the I/O links can be integrated in large ASICs. With a power budget of <; 20 mW/Gb/s, the feasibility of an ADC-based receiver is limited by the high-speed analog-to-digital converter (ADC) and complex digital processing in current fabrication technologies. In this paper, various designs and architectures for each component of an ADC-based receiver and their performance trade-offs are discussed. The design requirement of an ADC and digital processing can be relaxed with the aid of simple mixed-mode circuitry. More complex digital processing techniques are becoming feasible with the scaling of CMOS technology. However, the improvement from scaling is limited by the substantial leakage current, and the rate of improvement is slowing beyond 32 nm technology node.

Smart Front-End Signal Processing for Advanced Wireless Receivers

One of the key trends in the design of radio receivers and other wireless devices is to shift more and more of the transceiver functionalities to digital signal processing (DSP). At the same time, the demands on the remaining analog circuits are greatly increased, especially with lower power supplies and nanoscale technology effects such as variability. With the terminal users requesting high radio performance and data rates, and low power consumption on one hand, and terminal flexibility and reduced implementation costs on the other hand, the requirements for these remaining analog front-end stages become extremely challenging to meet. As a result, one interesting idea is to complement analog radio-frequency (RF) circuits with smart signal-processing algorithms to digitally enhanced RF circuits. In this paper, we focus on developing and demonstrating novel signal-processing techniques intended for the analog and digital front-ends of future low-power, flexible radios. One key aspect in the work is power-efficient digital front-end design with great flexibility for digital selectivity filtering and sample rate alteration. Another key ingredient is the analysis and mitigation of different analog RF impairments, with special emphasis on I/Q imbalance effects and second-order intermodulation (IM2) distortion in wideband multicarrier or multichannel radio receivers. The approach used in this work generally draws from the practical system performance specifications. Overall, our results clearly indicate that the proposed compensation techniques can be used to suppress I/Q imbalance and IM2 distortion effects in receiver front-end sections under realistic signaling assumptions. The adaptivity and flexibility offered by the overall digital front-end design greatly reduces the power consumption of the radio.

A software-radio front-end for microwave applications

Abstract. In modern communication, sensor and signal processing systems digitisation methods are gaining importance. They allow for building software configurable systems and provide better stability and reproducibility. Moreover digital front-ends cover a wider range of applications and have better performance compared with analog ones. The quest for new architectures in radio frequency front-ends is a clear consequence of the ever increasing number of different standards and the resulting task to provide a platform which covers as many standards as possible. At microwave frequencies, in particular at frequencies beyond 10 GHz, no direct sampling receivers are available yet. A look at the roadmap of the development of commercial analog-to-digital-converters (ADC) shows clearly, that they can neither be expected in near future. We present a novel architecture, which is capable of direct sampling of band-limited signals at frequencies beyond 10 GHz by means of an over-sampling technique. The wellknown Nyquist criterion states that wide-band digitisation of an RF-signal with a maximum frequency ƒ requires a minimum sampling rate of 2 · ƒ . But for a band-limited signal of bandwidth B the demands for the minimum sampling rate of the ADC relax to the value 2 · B. Employing a noise-forming sigma-delta ADC architecture even with a 1-bit-ADC a signal-to-noise ratio sufficient for many applications can be achieved. The key component of this architecture is the sample-and-hold switch. The required bandwidth of this switch must be well above 2 · ƒ . We designed, fabricated and characterized a preliminary demonstrator for the ISM-band at 2.4 GHz employing silicon Schottky diodes as a switch and SiGe-based MMICs as impedance transformers and comparators. Simulated and measured results will be presented.

A Scalable Media Processor Based Image Data Path for the Xerox DocuSP Platform

The Xerox Document Services Platform (DocuSP) is the Xerox Digital Front End platform for production products. DocuSP supports over 26 different production engines that include monochrome, color, cut sheet, and continuous feed products. In particular DocuSP is one of the Digital Front Ends for the Xerox iGen3 Digital Press. This talk will describe some unique technologies in the DocuSP DFE that enable high performance printing at 100 pages per minute in full color. Unique to this controller is the concept of a scalable performance, &#x201C;soft&#x201D; image data path, implemented in array of low cost media processors from Equator Technologies that provide the image processing required for full performance printing on iGen3. This allows DocuSP to be an agile platform to support new imaging features without the overhead of lengthy hardware development.