Digital Frequency-locked Loop Research Articles

A Digital Frequency Locked Loop With Minimum Computation Overhead for Heavily Distorted Single-Phase Grid Systems

Grid-connected converters require grid frequency and phase information for controlling the power injections into the grid. This information is achieved by a phase-locked loop (PLL) or frequency-locked loop (FLL) algorithms. The accuracy, reliability, and ease of implementation of the PLL/FLL algorithms in all grid conditions dictate the performance of the grid-connected converters. This article proposes a digital FLL for single-phase grid-connected systems. The proposed FLL tracks the frequency accurately, even in heavily distorted grid conditions. It uses a second-order generalized integrator (SOGI) as a pre-filter and a digital counter, based on the zero-crossing detection (ZCD) logic for estimating the grid frequency and phase angle. It does not require complex filters and tuning of multiple parameters. The implementation of the proposed FLL is simple and has less computational overhead. The ability of the proposed FLL to track the frequency and phase under various steady-state (dc-offset and harmonics) and transient (voltage sag, frequency drift, and phase jump) grid disturbances is tested in simulation using MATLAB/SIMULINK, and the results are reported. The experimental validation is done using a field programmable gate array (FPGA) controller in the laboratory. The proposed algorithm is able to track the estimates within 1.2 cycles of the grid voltage when tested under a heavy-distorted grid having 26.4% total harmonic distortion (THD). The measurement uncertainties and results of single-phase grid-connected inverter (GCI) using the proposed FLL are also presented.

Hardware Self-Organizing Map Based on Digital Frequency-Locked Loop and Triangular Neighborhood Function

This paper proposes a unique hardware architecture for a self-organizing map (SOM) that mimics the biological brain by using pulse mode operation. In the proposed SOM, vector elements are given as in the form of frequency modulated signals, and digital frequency-locked loops (DFLLs) in neurons handle the computations of the vector elements. The SOM is trained by unsupervised learning, where the winner neuron that has the nearest weight vector is found first. In the proposed SOM, the winner neuron is found by counting cycle slips between the signals that carry input and weight vectors. After the winner neuron is found, weight vectors selected by a neighborhood function are updated toward the input vector. Triangular neighborhood function that is implemented by using an attenuating enable signal for the DFLLs, is employed. To evaluate the proposed SOM and its building components, VHDL simulations and experiments using an FPGA were conducted. Compared to the previous work, the operation speed and learning capability were significantly improved. Novelty of the proposed architecture is it uniquely uses a pulse-based operation that mimics the biological brain, and it was verified that unsupervised learning can be realized with neurons communicating with each other using frequency modulated pulse signals.

A 0.5-V 560-kHz 18.8-fJ/Cycle On-Chip Oscillator With 96.1-ppm/°C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop

On-chip oscillators are popular clocking solutions for a wide range of circuits and systems due to their ease of integration and low form factor, but their energy efficiency is typically limited to the pJ/cycle range by a number of contributors, such as active biasing currents, frequency dividers, and comparators. This work presents an on-chip oscillator for energy-efficient Internet-of-Things (IoT) applications based on a duty-cycled digital frequency-locked loop (DFLL) that reduces energy by disabling energy-hungry components and only periodically reactivating them to keep the output frequency stabilized during temperature drifts. A test chip is implemented in 65-nm CMOS and achieves 18.8 fJ/cycle (10.5 nW at 560 kHz) while maintaining an average steady-state temperature stability of 96.1 ppm/°C from 0 °C to 100 °C.

A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique

A 6-bit time-to-digital converter that achieves mismatch free operation by using a single delay cell and sampling flip-flop is presented. The proposed TDC was integrated in a digital fractional-N PLL fabricated in a 32-nm digital SoC CMOS process for WiFi/WiMax radios. The TDC consumes 3 mW from a 1.05-V supply and occupies an area of 0.004 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . A digital frequency-locked loop is used to track and correct for PVT variations in the TDC and no additional linearization or mismatch calibrations are required. The DPLL uses a 20-bit high dynamic range DAC to drive a VCO in order to effectively realize a DCO with 100-Hz frequency resolution. The 2.5-GHz WiFi band LO output is generated from a 40-MHz reference with an integrated phase noise of - 35 dBc (10 kHz to 10 MHz) while consuming 21 mW . The worst case spur in the LO output is below - 50 dBc without requiring TDC mismatch and linearity calibration.

Architecture and Robust Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures

A small area fast-reprogrammable Digital Frequency-Locked Loop (DFLL) engine is presented as a solution for the Dynamic Voltage and Frequency Scaling (DVFS) circuitry in Globally Asynchronous Locally Synchronous (GALS) architectures implemented in 32 nm CMOS technology. The DFLL control is designed so that the closed-loop system is able to cope with process variability while it rejects temperature changes and supply voltage slow variations. Therefore the DFLL is made of three main blocks, namely a Digitally Controlled Oscillator (DCO), a that measures the frequency of the signal at the output of the DCO and a controller. A strong emphasis is set on the loop filter architecture choice and the tuning of its parameters. An analytical model of the DCO is deduced from accurate Spice simulations. The delay introduced by the sensor is also taken into account to design. From these models, an and robust controller with a minimum implementation area is developed. Here, optimal means that the controller is computed via the minimization of a given criterion while the robustness capability ensures that the closed-loop system is tolerant to process and temperature variations in a given range. Therefore, performances of the closed-loop system are ensured whatever the system characteristics are in a given range.

A Low-Power Continuously-Calibrated Clock Recovery Circuit for UHF RFID EPC Class-1 Generation-2 Transponders

A low-power, reliable and re-configurable clock recovery circuit for UHF RFID transponders for the EPC Class-1 Generation-2 standard is proposed. Based on a digital frequency-locked loop, the clock recovery circuit uses timing information available in the downlink data, namely, the pulse intervals of the PIE-coded data, to calibrate an oscillator's output frequency to meet the stringent frequency accuracy requirement of the standard. Fabricated in a 0.18-?m standard CMOS technology, the clock recovery circuit provides a calibrated frequency of 2.56 MHz with a frequency deviation within the range from -3.2% to +1.2% over process, supply voltage and temperature variations. The chip has an active area of 0.22 ?m2, operates from a supply voltage from 0.75 V to 1.3 V, and consumes less than 2 ?W for a 1-V supply.

Filter Calibration using Self Oscillation of Biquad RC Filter

This paper presents a digitally-controlled filter calibration technique for biquad RC filter using self oscillation. The biquad RC filter is converted to a fully-differential ring oscillator by changing its resistor connections, where the oscillation frequency reflects the cut-off frequency. The proposed calibration circuit measures the oscillation frequency by counting with a fixed higher-frequency clock and then tunes it to a desired frequency with a digital frequency-locked loop including a PI controller. Because the proposed circuit directly measures the cut-off frequency of the filter itself and calibrates it with the small area digital circuits, the area and the power consumption are much small compared with conventional works. When it is implemented in a 65nm CMOS process, the calibration circuit except the filter consumes the area of 80um X 50um and power consumption is 443uA at 1.2 V supply voltage.

High resolution frequency tracking system using the maximum entropy method

Abstract The tracking capability of the maximum entropy method (MEMrpar; is employed to develop a novel digital frequency-locked loop (DFLLrpar;. Unlike the conventional digital phase-locked loop (DPLLrpar;, the proposed DFLL locks directly on the frequency. In addition to the well-known components of the DPLL, the new DFLL includes a low-order MEM frequency estimator. The DFLL is shown to be capable of tracking a wide range of frequencies in servere noisy environments. It is computationally attractive. Simulation results are included.