Digital Control Module Research Articles

Design of Nupix-A2, a Monolithic Active Pixel Sensor for heavy-ion physics

The High Intensity heavy-ion Accelerator Facility (HIAF) is being constructed to generate intense beams of primary and radioactive ion for a wide range of research fields. Hence, a Monolithic Active Pixel Sensor (MAPS) named Nupix-A2 has been developed in a 130-nm High Resistivity CMOS process. The Nupix-A2 can simultaneously measure the particle hit' energy, arrival time, and position. It consists of a 128 × 128 pixel array, a digital-to-analog converter array, and a digital control module. The Nupix-A2 can measure energy deposition from 300 e- to over 50 ke- and time duration from 13 μs to 140 μs. This sensor also offers full readout mode and fast readout mode. In full-readout mode, all pixels measure arrival time and energy, suitable for real-time beam monitoring and image reconstruction. In fast-readout mode, only particle hit's positions are detected and read out. This paper presents the design of the Nupix-A2.

Improving the Reliability of DC-DC Power Supply by Reserving Feedback Signals

The paper deals with the problem of improving the reliability of DC-DC power supplies with pulse-width modulation. The topicality of the work is related to the importance of power supply issues in modern electronics, since the quality of operation of consumer electrical appliances, including critical ones, directly depends on the serviceability of sources. The object of the study is feedback circuits aimed at stabilization of the parameters of power supply of consumers. Failures of the mentioned feedback circuits most often occurs due to the electronic components degradation under harsh operating conditions as well as under severe mechanical overloads. Such failures are dangerous for uncontrolled increase of power supply output voltage and output current. To avoid this, a new method of reserving voltage feedback signals is presented in the paper which is implemented on the basis of flyback supply topology. Feedback signals are formed from the optocoupler located on the load side and from the auxiliary winding of the power transformer, together forming two independent output voltage control circuits. Only one circuit performs stabilization at any given moment of time. If one of these circuits fails, the second one can simply replace it in its operation. The proposed method does not require any digital signal processing algorithms or microprocessor control modules and can be implemented on the basis of cheap, widely available analog chips that perform pulse-width control of the output voltage. As a result, the problem of sudden feedback loop failure is solved and the reliability of electrical equipment is increased. The validity of the proposed method is confirmed by the results of computer simulation with the use of MatLab-Simulink environment. The obtained results can be used in design of fault-tolerant secondary power supplies that operate in harsh operating conditions.

Design and performance of the LLRF control system for CSNS linac

The China Spallation Neutron Source (CSNS) linac is designed with beam energy of 80 MeV and a peak current of 15 mA in the first phase. It consists of RFQ, two bunchers of medium-energy beam transmission line, four DTL tanks and one debuncher of linac-to-ring beam transmission line. Correspondingly, eight online RF power sources are used to power these accelerators. In order to stabilize the amplitude, phase and resonant frequency of the RF accelerating field, and minimize beam loss, we have established digital low-level RF (LLRF) control system. The LLRF system includes RF reference line, analog module (AM), clock distribution module, digital control module (DCM), high-power protection module, timing and RF interlock module and so on. The DCM is mainly responsible for the stability of the RF field amplitude and phase, and RF interlock module can quickly cut off the RF drive in case of arc in the RF transmission system, VSWR over threshold or cavity vacuum fault and so on. During beam commissioning, all of eight online units of LLRF control system were operating stably and reliably. The amplitude and phase variations of the linac fields have been achieved about ± 0.4% and ± 0.15° with 10-mA beam loading, much better than the design requirements of ± 1% in amplitude and ± 1° in phase. With the help of this system, we achieved stable operation under different beam loads. Also, many important progresses have been achieved in the LLRF control system for a more convenient operation and a higher stability performance. This article describes the design and implementation of the LLRF for CSNS linac.

Integrated synchronous data acquisition subsystem for high‐speed GPR system

In this study, an integrated synchronous data acquisition subsystem for high-speed dual-channel ultra-wideband ground penetrating radar (GPR) system is designed and tested. Factors that could cause data missing and asynchronisation are analyzed. According to timing sequence, a field-programmable gate array-based onboard digital control module is integrated to synchronise the data acquisition and data storage subsystems. By applying simultaneous multi-buffer acquisition and readout mode and multi-threading configuration, as well as the critical section control and queue storage structure, the GPR data throughput is considerably improved. For the practicality of this system, a smart End-of-Job control design is performed between different threads to control data acquisition. By using different performance indexes, receiver operation characteristic curve, maximum scan rate, and the rebar detection experiment demonstrate the superiority of author's method.

ASIP development of a real-time control module for a retrodirective antenna array

Electronically steerable antenna arrays become attractive due the possibility of simultaneously steering the main lobe in the desired direction and suppressing side lobes only by means of electronic control of excitation currents, hence avoiding mechanical components. However, this type of antenna requires intensive calculation for setting the excitation current of each array element in order to shape the radiation pattern for retransmission, thus demanding a dedicated hardware. This work reports the development of a digital control module for a retrodirective antenna array based on a customized dedicated microcontroller called PAMPIUM, which has been implemented on FPGA, aiming real-time response and low power consumption. A methodology for generation of optimized hardware in terms of area, power efficiency and performance is discussed. A design tool to provide the user with a practical and intuitive environment has been developed, which allows simulating and assessing statistics about execution and performance of the designed architecture. The developed digital control module is capable of updating the current coefficients of an eight-element antenna array in less than 1 s with a power consumption of 5.3 mW for beamsteering angles from 0° to 60°. The proposed methodology allows the demonstration of full efficiency of a retrodirective antenna array system.

Hardware design implementation issues of the estimator-based controller using FPGA

ABSTRACTHardware implementation issues play a vital role to realize the system accurately. Realization of hardware in digital domain has more advantages than analog domain. Field programming gate array (FPGA) based architectures are suitable for fast and reconfigurable systems. In this paper, implementation issues of an estimator based controller using FPGA are discussed. Verilog coding is developed to defeat these issues and efficient hardware mapping is derived. Input signal processing is proposed to overcome the analog to digital converter (ADC) interfacing issues such as quantization, sampling rate, resolution, non-linearity error and offset error. Optimum bit sizing of digital control modules are derived, considering system requirements and specifications. Controller operations are analyzed in binary form to choose the bit size of various operands and control modules, to derive accurate results. In this application, a 16-bit control architecture is proposed to estimate states of the converter and to generate control signals. Estimator based controller is designed for a dc-dc converter. Atlys Spartan-6 XC6SLX45 FPGA is used to implement the controller. Implementation issues such as ADC errors, settling time, the bit size of variables, quantization effects of the estimator and controller are mainly focused. It enables verilog coding quite easier to implement non-linear controllers using FPGA.

A Digital Control System for the Power Conditioning Unit of Spacecraft

The paper considers the design concept and estimated characteristics of automatic control systems for the power conditioning unit of spacecraft with a digital control system. The purpose of the present work is to develop a structure of an automatic control system providing the following: power improvement for the power conditioning unit due to the parallel connection of power conditioning modules; high structural reliability of the power conditioning unit designed for two or more failures due to the channel redundancy for the digital control module and a special design for the majority logic element; the organization of the required operating sequence of power sources and their efficient use; high speed and accuracy of regulation of voltage output approaching the analog control systems. The expected results of channel redundancy for the digital control module have been confirmed using the experimental prototype. The authors' results include the generation of the superordinate control level without raising requirements to the reliability indices of the majority logic element; this control level has been generated using the hierarchical digital control system with a redundant control system.

Benchmarks for cyber-physical systems: A modular model library for building automation systems

Building Automation Systems (BAS) are exemplars of Cyber-Physical Systems (CPS), incorporating digital control architectures over underlying continuous physical processes. We provide a modular model library for BAS drawn from expertise developed on a real BAS setup. The library allows to build models comprising either physical quantities or digital control modules. The structure, operation, and dynamics of the model can be complex, incorporating (i) stochasticity, (ii) non-linearities, (iii) numerous continuous variables or discrete states, (iv) various input and output signals, and (v) a large number of possible discrete configurations. The modular composition of BAS components can generate useful CPS benchmarks. We display this use by means of three realistic case studies, where corresponding models are built and engaged with different analysis goals. The benchmarks, the model library and associated data collected from the BAS setup at the University of Oxford, are kept on-line at https://github.com/natchi92/BASBenchmarks

Embedded Signal Processing Module for Online Filtering in High-Event Rate Conditions

Online event detection (filtering) is required in communications, industry and electronic instrumentation systems. Those systems may comprise sequential decision levels. Eventually, decision to reject or accept an event may comprise fusion of different measured data. This work describes an embedded solution in field-programmable gate array (FPGA), which allows to combine information from two different sources for a decision. A matched filter discriminator was used to identify typical signatures of interest. The main focus is on both digital data control and packaging module design and implementation and optimization of the matched filter module in terms of FPGA occupation. The proposed digital electronic system is presented and simulation results are used to validate the design.

A monolithic integrated low-voltage deep brain stimulator with wireless power and data transmission**Project supported by the National Natural Science Foundation of China (Nos. 61404043, 61401137), the Key Laboratory of Infrared Imaging Materials and Detectors, Shanghai Institute of Technical Physics, Chinese Academy of Sciences (Nos. IIMDKFJJ-13-06, IIMDKFJJ-14-03), and the Fundamental Research Funds for the Central Universities (No. 2015HGZX0026).

A monolithic integrated low-voltage deep brain stimulator with wireless power and data transmission is presented. Data and power are transmitted to the stimulator by mutual inductance coupling, while the in-vitro controller encodes the stimulation parameters. The stimulator integrates the digital control module and can generate the bipolar current with equal amplitude in four channels. In order to reduce power consumption, a novel controlled threshold voltage cancellation rectifier is proposed in this paper to provide the supply voltage of the stimulator. The monolithic stimulator was fabricated in a SMIC 0.18 μm 1-poly 6-metal mixed-signal CMOS process, occupying 0.23 mm2, and consumes 180 μW on average. Compared with previously published stimulators, this design has advantages of large stimulated current (0–0.8 mA) with the double low-voltage supply (1.8 and 3.3 V), and high-level integration.

Sensitivity Analysis of Digital I&C Modules in Protection and Safety Systems

This research is performed to examine the sensitivity of digital Instrumentation and Control (I&C) components and modules used in regulating and protection systems architectures of nuclear industry. Fault Tree Analysis (FTA) was performed for four configurations of RPS channel architecture. The channel unavailability has been calculated by using AIMS-PSA, which comes out 4.517E-03, 2.551E-03, 2.246E-03 and 2.7613-04 for architecture configuration I, II, III and IV respectively. It is observed that unavailability decreases by 43.5 % & 50.4% by inserting partial redundancy whereas maximum reduction of 93.9 % in unavailability happens when double redundancy is inserted in architecture. Coincidence module output failure and bi-stable output failures are identified as sensitive failures by Risk Reduction Worth (RRW) and Fussell-Vesely (FV) importance. RRW highlights that risk from coincidence processor output failure can reduced by 48.83 folds and FV indicates that BP output is sensitive by 0.9796 (on a scale of 1).

Silicon-Based Multichannel Probe Integrated with a Front End Low Power Neural Recording IC for Acute Neural Recording

This work presents a silicon-based multichannel probe integrated with a front end low power neural recording integrated circuit (IC) which is used in acute neural recording application. The low power neural recording IC contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. The 100-channel neural recording IC consumes 1.16-mW, making it the optimum solution for multi-channel neural recording systems. The neural recording IC and Si probe are integrated in a printed circuit board (PCB) which is fixed on the skull using dental resin. Digital neural signal is converted to analog signal and output by neural recording IC. The signal-to-noise ratio of neural recording signal can be increased through the reduction of interconnect length. The buckling strength of the fabricated probes was simulated using finite element analysis and measured by compression tester. The packaging method of 2D probe and neural recording IC was successfully demonstrated. The impedance of the assembled probe is also measured and discussed. To verify the functionality of Si probe integrated with neural recording IC, a pseudo neural signal acquisitions have been perform.

A 100-Channel 1-mW Implantable Neural Recording IC

This paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channel by more than 50% compared to the conventional multiplexing neural recording system. A neural amplifier (NA) with current-reuse technique and weak inversion operation is demonstrated, consuming 800 nA under 1-V supply while achieving an input-referred noise of 4.0 μVrms in a 8-kHz bandwidth and a NEF of 1.9 for the whole analog recording chain. The measured frequency response of the analog front-end has a high-pass cutoff frequency from sub-1 Hz to 248 Hz and a low-pass cutoff frequency from 432 Hz to 5.1 kHz, which can be configured to record neural spikes and local field potentials simultaneously or separately. The whole system was fabricated in a 0.18-μm standard CMOS process and operates under 1 V for analog blocks and ADC, and 1.8 V for digital modules. The number of active recording channels is programmable and the digital output data rate changes accordingly, leading to high system power efficiency. The overall 100-channel interface IC consumes 1.16-mW total power, making it the optimum solution for multi-channel neural recording systems.

基于数字控制模块的工业有毒气体在线监测仪

基于数字控制模块的工业有毒气体在线监测仪

Low cost and low power open-loop frequency synthesiser

A fully integrated frequency synthesiser based on a low-cost and low-power multifunctional phase-locked loop (PLL) is proposed for frequency shift keying applications. The optimised open-loop modulation circuit and its digital control module are detailed. The 0.166 mm 2 synthesiser is implemented in a 0.28 μm CMOS technology with 2.5 V supply voltage. Measurement results related to the open-loop frequency drift and demodulated signal together with the PLL lock time are presented.

Use of an AC induction motor system for producing finger movements in human subjects

This report describes the set-up and evaluation of a novel system for producing precise finger movements, for tests of movement perception. The specifications were to construct a system using commercially available components that were easy to use but which offered both flexibility and also high precision control. The system was constructed around an industrial AC induction motor with an optical encoder, controlled by an AC servo digital control module that could be programmed using a simple, high-level language. This set-up fulfilled the requirements regarding position and velocity control for a range of movements and also the facility for the subject to move the joint voluntarily while still attached to the motor. However a number of problems were encountered, the most serious being the level of vibration and the inability to vary the torque during movements. The vibration was reduced to the point where it did not affect the subject, by the introduction of mechanical dampening using an anti-vibration coupling and a pneumatic splint. The torque control could not be modified during rotation and so the system could only be operated using constant torque for any given movement.

A Digital Control Kit for MATLAB

This paper outlines the features of a toolkit which provides a user-friendly, graphical front-end to MATLAB for analysing and designing digital control systems. It is aimed particularly at educational applications in support of digital control modules.

Telepathological (image transmission) configuration.

The Laboratory for Biomedical Informatics (LBMI) has developed a digital microscope control module incorporated into an image analysis system. This is now equipped with an ISDN switch box for linking up with a remote computer-based station for delivering histopathological services. The FRAME, client/server integrated software, was developed to initiate the communication link, adjust the microscope settings, acquire and transmit images. This LBMI telepathology initiative employs simple solutions to arrive at the point of prototyping and demonstrating the state of the art on the one hand and encountering the prevailing problems in order to deliberate on possible remedies on the other.

A fault-tolerant multiprocess controller for magnetic bearings

A fault-tolerant microprocessor system designed to provide digital control for an active magnetic bearing is described. This particular control problem demands significant processing power, is easily divided into relatively independent parallel tasks, and cannot tolerate controller failures. The overall system requirements and architecture are described, as is the design of the digital control module and the analog I/O board. The fault tolerance of the system is evaluated. Extensive computer simulations of system reliability models verified that the design satisfies all of the reliability requirements. Although the system was designed for a specific problem, much effort was expended to make it general enough for applications to a wide range of real-time applications.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A Standard Digital Control Module for Two-Transistor Pulsewidth Modulated Converters

Two-transistor pulsewidth modulated converters do not find widespread application since they are usually expensive, bulky, and difficult to design. To resolve these difficulties, a circuit is presented in which the pulsewidth control mechanism is separate from the power-handling stages. This permits the use of a standard integrated digital control module, which simplifies the overall design of two-transistor pulsewidth modulated converters. The module is small and inexpensive, and results in efficient, high-performance converters.