Digital Control Logic Research Articles

A Non-Linear Successive Approximation Finite State Machine for ADCs with Robust Performance

This work presents the detailed design of a Successive Approximation Analog to Digital Data Converter (SAR ADC) using bulk 180 nm CMOS IC technology. The focus of the study is on replacing the typical Successive Approximation Register array with a Finite State Machine. This converter features a fully differential and bipolar architecture, which leads to the logic SAR nonlinear behavior. A novel digital control logic mitigates the conversion errors through the conditions in the previous logic states. The logic scheme, in combination with a robust continuous comparator, demonstrates tolerance to Process, Voltage, and Temperature variations. The architecture does not include calibration or additional redundancies in post-layout simulations to emphasize the exclusive benefits of the new SAR logic. The proposed SAR ADC achieves a 14.07 effective number of bits with 7.04 fJ/conversion step Walden figure of merit in biomedical applications.

Design methodology for the control logic of flexible production systems and related logistics

The ever-shorter product life cycle entails a shortening of the life cycle of the production site and production systems as well. One of the biggest advantages of flexible production systems is that new products can be introduced to them continuously, so that their life cycle can be significantly extended. Flexible manufacturing systems, on the other hand, also require flexible control, the logic of which must be defined already in the design phase. The main elements of the design methodology of the production and logistics layout that make up the research are the information relationship chart and the related decision tables, which are suitable for speeding up the design and later for facilitating the creation of a digital twin and control logic programming.

Energy digital twins in smart manufacturing systems: A case study

Among core Industry 4.0 technologies, the Digital Twin represents a promising smart technology and tool that researchers are investigating to help improve energy efficiency at the shopfloor level by analyzing and optimizing energy consumption. Energy Digital Twins are a relatively new area of research, only gaining popularity in industry applications and academia recently. where a comprehensive literature review uncovered only one ‘true’ Energy Digital Twin application across published research to date. To address this research gap, an Energy Digital Twin for smart manufacturing systems was developed and evaluated in this study. In particular, the study focused on bidirectional parameter communication between the physical and the virtual part with the aim of optimizing the energy used in the manufacturing process. To address this research gap, the research objective is to create and evaluate an application of an energy optimizing Digital Twin for a Heating Tunnel. Following the definition of a Digital Twin, the research methodology and experimental setup have three major components: i) the Heating Tunnel as the physical object, ii) the digital counterpart constructed using Python to house the digital control logic and linear energy optimization feedback model, and iii) the connecting fabric, in form of a bidirectional OPC UA communication protocol. The optimization model ingests input parameters of setpoint temperature, power level, and targeted overshoot time, and after running the simulation, returns a calculated value of the required turn off temperature to the real-time heating process of the physical system. Results show that the Energy Digital Twin is effective at maintaining the maximum temperature range of the Heating Tunnel during the heating process, in addition to reducing the energy consumption and cost for all trial runs compared to the original process. Overall, the study successfully created and evaluated a functioning energy optimizing Digital Twin with bidirectional, automated feedback. The results of this research emphasize the potential impact of Energy Digital Twin applications in any manufacturing process and show the promise of future work in this realm of Energy Digital Twins.

A Low-Power SAR ADC with Capacitor-Splitting Energy-Efficient Switching Scheme for Wearable Biosensor Applications.

A low-power SAR ADC with capacitor-splitting energy-efficient switching scheme is proposed for wearable biosensor applications. Based on capacitor-splitting, additional reference voltage Vcm, and common-mode techniques, the proposed switching scheme achieves 93.76% less switching energy compared to the conventional scheme with common-mode voltage shift in one LSB. With the switching scheme, the proposed SAR ADC can lower the dependency on the accuracy of Vcm and the complexity of digital control logic and DAC driver circuits. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low sampling error sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrate that the ADC achieves a 61.77 dB SNDR and a 78.06 dB SFDR and consumes 4.45 μW of power in a 180 nm process with a 1 V power supply, a full-swing input signal frequency of 93.33 kHz, and a sampling rate of 200 kS/s.

Second-Order Level-Crossing Sampling Analog to Digital Converter for Electrocardiogram Delineation and Premature Ventricular Contraction Detection.

This article presents an electrocardiogram (ECG) delineation and arrhythmia heartbeat detection system using a novel second-order level-crossing sampling analog to digital converter (ADC) for real-time data compression and feature extraction. The proposed system consists of the front-end integrated circuit of the data converter, the delineation algorithm, and the arrhythmia detection algorithm. Compared with conventional level-sampling ADCs, the proposed circuit updates tracking thresholds using linear extrapolation, which forms a second-order level-crossing sampling ADC that has sloped sampling levels. The computing is done digitally and is implemented by modifying the digital control logic of a conventional Successive-approximation-register (SAR) ADC. The system separates the sampling and quantization processes and only selects the turning points in the input waveform for quantization. The output of the proposed data converter consists of both the digital value of the selected sampling points and the timestamp between the selected sampling points. The main advantages are data savings for the data converter and the following digital signal processing or communication circuits, which are ideal for low-power sensors. The test chip was fabricated using a 180 nm CMOS process. When sensing sparse signals such as ECG signals the proposed ADC achieves a compression factor of 8.33. The delineation algorithm uses a triangle filter method to locate the fiducial points and measures the intervals, slopes, and morphology of the QRS complex and the P/T waves. Those extracted features are then used in the arrhythmia heartbeat detection algorithm to identify Premature Ventricular Contraction (PVC). The overall performance of the system is evaluated using the MIT-BIH database and the QT database, which is also compared with the recently reported systems. The accuracy, sensitivity, specificity, PPV, and F1 score are 97.3%, 89.6%, 97.8%, 73.3%, and 0.81 for detecting PVC.

A Shifting Current Mirror Driver Circuit for Electrical Impedance Tomography Applications

This brief describes a high power efficiency, high linearity current driver for wearable electrical impedance tomography (EIT). It is extremely important to improve the power efficiency of the current driver circuit for wearable EIT applications because it consumes the majority of the power. As such, we propose a multi-stage shifting current mirror (SCM) current-steering current driver circuit with customized dynamic element matching (DEM) techniques to suppress harmonic distortion (HD) to the greatest extent. Furthermore, the placement of switches in the current mirror circuit is optimized to reduce glitches during the switching phases. Operating between 14 MHz to 56 MHz, the power consumptions for the current mirror and the digital control logic are 21.6-141.6 lW and 64.8-438 μW, respectively. The proposed circuit has demonstrated an excellent energy efficiency of 0.3 μW/kHz while maintaining a total harmonic distortion (HD) of <-43 dB (0.7%).

A Wideband True Time Delay Circuit Using 0.25 µm GaN HEMT Technology.

This paper presents a wideband 4-bit true time delay IC using a 0.25 μm GaN HEMT (High-Electron-Mobility Transistor) process for the beam-squint-free phased array antennas. The true time delay IC is implemented with a switched path circuit topology using DPDT (Double Pole Double Throw) with no shunt transistor in the inter-stages to improve the bandwidth and SPDT (Single Pole Single Throw) switches at the input and the output ports. The delay lines are implemented with CLC π-networks with the lumped element to ensure a compact chip size. A negative voltage generator and an SPI controller are implemented in the PCB (Printed Circuit Board) due to the lack of digital control logic in GaN technology. A maximum time delay of ~182 ps with a time delay resolution of 10.5 ps is achieved at DC-6 GHz. The RMS (Root Mean Square) time delay and amplitude error are <5 ps and <0.6 dB, respectively. The measured insertion loss is <6.8 dB and the input and output return losses are >10 dB at DC-6 GHz. The current consumption is nearly zero with a 3.3 V supply. The chip size including pads is 2.45 × 1.75 mm2. To the authors' knowledge, this is the first demonstration of a true time delay IC using GaN HEMT technology.

A 64-channel waveform sampling ASIC for SiPM in space-born applications

The architecture of a 64-channel ASIC for the readout of Silicon Photomultipliers in space experiments is described. Each channel embeds a front-end amplifier with a common gate topology followed by a 256 cells analogue memory with a sampling frequency of 200 MHz. A single memory cell includes a storage capacitor, a single-slope Analog-to-Digital Converter (ADC) with programmable resolution between 8 and 12 bits and the digital control logic. To save power, the A/D conversion is carried-out only when a trigger signal is received. The trigger can either be generated inside the ASIC or provided by an external source. The analogue samples are digitized in parallel, thus reducing the conversion dead time. The memory cells can be arranged in a single array or they can be grouped in shorter slots of 32 or 64 cells that work in a multi-buffer configuration. The channels can work independently or they can be synchronised to acquire the same time-frame in the full chip. The target power consumption is 5 mW/channel. The ASIC is being designed in a 65-nm CMOS technology. A digital-on-top flow is applied for the integration and final validation of the chip. The tape-out is scheduled in the first quarter of 2023.

High Efficiency Power Management Unit for Implantable Optical-Electrical Stimulators

Battery-less active implantable devices are of interest because they offer longer life span and eliminate costly battery replacement surgical interventions. This is possible as a result of advances in inductive power transfer and development of power management circuits to maximize the overall power transfer and provide various voltage levels for multi-functional implantable devices. Rehabilitation therapy using optical stimulation of genetically modified peripheral neurons requires high current loads. Standard rectification topologies are inefficient and have associated voltage drops unsuited for miniaturized implants. This paper presents an integrated power management unit (PMU) for an optical-electrical stimulator to be used in the treatment of motor neurone disease. It includes a power-efficient regulating rectifier with a novel body biased high-speed comparator providing 3.3 V for the operation of the stimulator, a 3-stage latch-up charge pump with 12 V output for the input stage of the optical-electrical stimulator, and 1.8 V for digital control logic. The chip was fabricated in a 0.18 lm CMOS process. Measured results show that for a regulated output of 3.3 V delivering 30.3 mW power, the peak power conversion efficiency is 84.2% at 6.78 MHz inductive link tunable frequency reducing to 70.3% at 13.56 MHz. The charge pump with on chip capacitors has 90.9% measured voltage conversion efficiency.

Implementation of TCM grid-connected inverter based on STM32

In this paper, STM32 is used to realize the control of TCM grid-connected inverter, which replaces the traditional control mode of digital logic controller and MCU combination, and simplifies the controller structure. A simple method for calculating the negative driving voltage of gallium nitride is presented. In this paper, the circuit parameters of each part of TCM inverter are designed, and the design scheme of each part of the circuit is given. Finally, a 200W prototype is built to verify the feasibility of the design scheme.

Power Quality Improvement in a Solar PV Assisted Microgrid Using Upgraded ANN-Based Controller

This paper proposes the design of a controller using the artificial neural network (ANN) for a solar photovoltaic (PV)-fed cascaded multilevel inverter (CMLI) to enhance the power quality. The objective of this presented ANN controller is to obtain a maximum output voltage with no filter components. This paper also investigates and eliminates the voltage harmonics that occurred in a solar-fed cascaded 3-stage inverter using various techniques such as pulse width modulation (PWM), digital logic control (DLC), fuzzy logic controller (FLC), and ANN, and the results are compared. Based on the results, the proposed ANN-based controller efficiently reduces harmonics and improves the power quality. This is achieved by solving the harmonic equations and thereby changing the switching angles of each semiconductor to a minimum value. The ANN is trained by a dataset consisting of varying input voltage and switching angles. The simulation was performed using MATLAB/Simulink for different types of controllers like PWM, DLC, FLC, and ANN for the 3-stage inverter. The simulated results are compared with the results obtained from a 3 kWp photovoltaic plant connected to the CMLI. Finally, on the basis of performance analysis, it was confirmed that the ANN-based controller effectively eliminates harmonics and improves the power quality.

Design a novel digital sliding mode predictive control for buck converter

ABSTRACT In this article, a new discrete-time sliding mode predictive control (DSMPC) with a PID sliding function is proposed for synchronous DC–DC buck converter, and its stability analysis is reported. The model predictive control, along with digital sliding mode control (DSMC), is able to further reducing the chattering phenomenon, steady-state error, overshoot and undershoot. The proposed control implementation only requires output error voltage evaluation. The effectiveness of the proposed DSMPC is proved through simulation results executed by the MATLAB/SIMULINK software. These results demonstrate its superior performance to DSMC. In other words, it represents a significant reduction of the chattering, overshoot and undershoots of output voltage response by an optimised control law during load and line variations. The proposed DSMPC almost overcomes the steady-state error (0.02%) and decreases the ripple value to about 0.2%. The overshoot and undershoot are 1.5% and 1%, respectively. Moreover, when the input voltage is changed by 26%, there is approximately no overshoot and undershoot. Also, some experimental results are presented to further illustrate the effectiveness of the proposed system. Experimental studies have been performed using a Spartan-6 field programmable gate array platform by Xilinx for the implementation of the digital control and relevant logic.

A 170 MHz to 330 MHz Wideband 90 nm CMOS RC–CR Phase Shifter with Integrated On-Line Amplitude Locked Loop Calibration for Hartley Image Rejection Transceiver

A 160 MHz bandwidth 90° active RC–CR phase shifter with integrated on-line amplitude locked loop (ALL) calibration targeted to 802.11ac 5 GHz wireless local area network (WLAN) applications is presented in this paper. The quadrature phase shifter is a key component for transceivers employing the Hartley image rejection architecture. The passive RC–CR phase shifter generates the required two quadrature outputs with an accurate 90° phase shift over the required bandwidth but lack the required accuracy in amplitude matching. A 90 nm CMOS microelectronic implementation of an RC–CR phase shifter is proposed with active resistors that are adjusted by an integrated on-line ALL calibration system to maintain matching amplitudes of the quadrature outputs over the required bandwidth. The on-line ALL calibration system employs peak detectors, comparators, digital logic control, and charge pump to incrementally adjust the active resistors while converging to matched amplitudes similar to the operation of phase-locked loop with a phase-frequency detector and charge pump. The resulting 90 nm implementation supports − 40db to − 70db image rejection ratios (IMMRs) over the IF 170 MHz to 330 MHz bandwidth. The 90 nm CMOS implementation is fully functional considering process variations based on 200 Monte Carlo simulations.

Design of a general-purpose automation software based on Raspberry Pi

Embedded systems and open technologies play a fundamental role in implementing the Internet of Things in the industrial automation field. This paper is related to the engineering of a general-purpose automation software, based on a computerised system with Raspberry Pi operating as a digital logic controller. The automation solution regulates sequential and continuous processes of multiple input/output signals, and its functioning can be effectively configured according to the project's requirements. This software technology proposal aims to simplify obtaining a process control solution for industrial, laboratory, and home automation projects through computer-assisted design. This solution offers a pre-elaborated software structure and functionalities, allowing creators to obtain their results faster and with less effort, where commercial automation products demand deep expertise in programming languages, in process control technologies, and expend long developing times.

Low power analogue equaliser with adaptive digital tuning for fast ethernet

This work presents an analogue equaliser with digital tuning. It compensates the losses introduced by up to 120 m long category 5 unshielded twisted pair cables and baseline wander (BLW). The equaliser is designed for Fast Ethernet with a symbol rate of 125 MHz. A g m -C filter, based on three first-order high pass filters, is used to compensate the cable loss. To minimise power consumption, three operational transconductance amplifiers (OTAs) are merged into a novel multi-input OTA structure. Additionally, a robust digital control logic is presented to automatically adjust the parameters of the equaliser for different cable lengths. A fast settling time below 250 µs is demonstrated for different scenarios. The equaliser is fabricated as part of a Fast Ethernet PHY chip in a 180 nm CMOS technology of GLOBALFOUNDRIES. Measurement results demonstrate error-free data transmission (bit error rate below 10 −12 ) for cable lengths up to 120 m. The power consumption of the analogue equaliser ranges from 2.3 mW (short cable) to 6.5 mW (120 m cable). To the best of the authors’ knowledge, this is the lowest power consumption of an analogue equaliser for Fast Ethernet, supporting additional BLW and flat loss compensation reported to date.

A 0.5 to 1.7 Gbps PI-CDR with a Wide Frequency-Tracking Range

This paper proposes a continuous-rate clock-data-recovery (CDR) circuit that covers a data rate range of 500[Formula: see text]Mbps to 1.7[Formula: see text]Gbps. The proposed CDR is based on the phase interpolation principle and implemented in 130[Formula: see text]nm CMOS. The design utilizes digital voter and phase control logic instead of analog charge pump and filter, which facilitates migration among different technologies. To avoid the phase interpolator (PI) getting into the nonlinear region, multiple modes are selected to limit the frequency range of the sampling clock within 500[Formula: see text]MHz to 1[Formula: see text]GHz. A 5[Formula: see text]mm2 test chip is fabricated, where the CDR core occupies 0.359[Formula: see text]mm2 of silicon area. The PI achieves a resolution of 7 bits and a good linearity of 0.9955. The proposed CDR also achieves a BER less than 10[Formula: see text] and has a frequency tracking range of [Formula: see text][Formula: see text]ppm. The power consumed by the proposed CDR is 32.6[Formula: see text]mW/Gbps.

Low Power Design of a 1 V 8-bit 125 fJ Asynchronous SAR ADC with Binary Weighted Capacitive DAC

The work proposes an improved technique to design a low power 8-bit asynchronous successive approximation register (ASAR), an analog-to-digital converter (ADC). The proposed ASAR ADC consists of a comparator, ASAR (digital control logic block), and a capacitive-digital-to-analog convertor (C-DAC). The comparator is a preamplier-based improved positive feedback latch circuit which has a built-in sample and hold (S/H) functionality and saves an enormous amount of power. The implemented digital control logic block performing the successive approximation (SA) algorithm is totally unrestrained of the external clock pulse. The outputs from the comparator are given to a XOR logic whose outputs serve as an internally generated clock (ready signal) to trigger the digital control block. Hence, an external clock is not required to initiate the digital control block making its operation asynchronous. By implementing this, the ADC can circumvent the usage of an oversampled clock and can operate on a single low-speed sample clock. This, in turn, saves power and it cuts down the required resilience in sampling rates. The proposed ADC has been designed and simulated using UMC-0.18[Formula: see text][Formula: see text]m CMOS technology which dissipates 32.18[Formula: see text][Formula: see text]W power when operated on a single 1[Formula: see text]V power supply and achieves complete 8-bit conversion in 1.09[Formula: see text][Formula: see text]s. The relative accuracy of capacitor ratio, aperture jitter and FOM are 0.39[Formula: see text], 1.2[Formula: see text]ns and 125[Formula: see text]fJ/conversion-step, respectively.

A Mixed Signal DC Offset Cancellation for VGA of Zero-IF Receiver

This paper proposes a mixed signal DC offset cancellation (DCOC) which does not cause the near-DC rejection for zero-IF receiver. To achieve low output offset efficiently, the DCOC consisting of a comparator, a digital logic controller and compensation voltage generators is used. It utilizes current sources arrays that are controlled by thermometer code to generate the compensation voltage. The proposed DCOC is implemented in GF 0.18 [Formula: see text]m CMOS process. The measurement results show that the proposed calibration method can reduce the offset residue to less than 80 mV and the total calibration time is less than 13 [Formula: see text]s. It only drains 60 [Formula: see text]A from a 3.3 V supply.

A Resistance Deviation-To-Time Interval Converter Based On Dual-Slope Integration

A resistance deviation-to-time interval converter based on dual-slope integration using second generation current conveyors (CCIIs) is designed for connecting resistive bridge sensors with a digital system. It consists of a differential integrator using CCIIs, a voltage comparator, and a digital control logic for controlling four analog switches. Experimental results exhibit that a conversion sensitivity amounts to <TEX>$15.56{\mu}s/{\Omega}$</TEX> over the resistance deviation range of <TEX>$0-200{\Omega}$</TEX> and its linearity error is less than <TEX>${\pm}0.02%$</TEX>. Its temperature stability is less than <TEX>$220ppm/^{\circ}C$</TEX> in the temperature range of <TEX>$-25-85^{\circ}C$</TEX>. Power dissipation of the converter is 60.2 mW.

Theorem-Proving Analysis of Digital Control Logic Interacting with Continuous Dynamics

This work outlines an equation-based formulation of a digital control program and transducer interacting with a continuous physical process, and an approach using the Coq theorem prover for verifying the performance of the combined hybrid system. Considering thermal dynamics with linear dissipation for simplicity, we focus on a generalizable, physically consistent description of the interaction of the real-valued temperature and the digital program acting as a thermostat. Of interest in this work is the discovery and formal proof of bounds on the temperature, the degree of variation, and other performance characteristics. Our approach explicitly addresses the need to mathematically represent the decision problem inherent in an analog-to-digital converter, which for rare values can take an arbitrarily long time to produce a digital answer (the so-called Buridan's Principle); this constraint ineluctably manifests itself in the verification of thermostat performance. Furthermore, the temporal causality constraints in the thermal physics must be made explicit to obtain a consistent model for analysis. We discuss the significance of these findings toward the verification of digital control for more complex physical variables and fields.