Digital Control Delay Research Articles

Analysis of active impedance characteristics and harmonic deterioration of multiple grid connected inverters considering nonlinear factors

AbstractThe harmonic problems caused by non‐linear factors of the grid connected inverter (GCI) system are more complicated, including both non‐characteristic harmonics emitted by the dead‐time and the changes in harmonic impedance characteristics. Harmonics interact with the changing impedance, and even cause harmonic amplification and resonance. The harmonic deterioration of the multiple GCIs system is serious. To analyse the mechanism and way of harmonic deterioration in grid‐connected system caused by nonlinear factors, the active impedance models of single inverter and multiple GCIs system including dead‐time effect and digital control delay are established first. In view of this, the influence mechanism of non‐linear factors on system stability is explored. The improved modal analysis method is used to traverse the network series parallel resonance caused by nonlinear factors. The results show that both the dead‐time effect and digital control delay reduce phase margin of the system, resulting in the resonant frequency shift and the resonant peak increase. When the harmonic excitation source interacts with the complex network under the influence of nonlinear factors, it will lead to further deterioration of harmonics. Finally, based on the MATLAB and RT‐LAB hardware‐in‐the‐loop simulation platforms, a multiple GCIs system model is built to verify the correctness of the established active impedance model and harmonic deterioration analysis.

Adaptability enhancement of fractional‐order LLCL‐type grid‐connected inverter to weak grid based on grid voltage weighted feedforward scheme

SummaryGrid‐connected inverter with a novel fractional‐order LLCL filter has the advantage of high grid current tracking accuracy and low total harmonic distortion without passive or active dampers, and the grid voltage full feedforward scheme is an effective method to improve the quality of grid current. However, due to the digital control delay, the suppression of the grid current harmonics is weakened, and the inverter output impedance has an additional negative phase shift, which deteriorates the stability of grid‐connected systems under weak grid. In this paper, a weighted grid voltage fractional‐order feedforward control scheme is proposed based on a quasi‐proportional resonant (QPR) controller, which introduces two weighting factors in the full feedforward path of the grid voltage and compensates the phase lag of the output impedance by designing appropriate weighting factors. Then, an improved scheme combining the QPR controller with a phase compensator is presented. As a result, the suppression ability of grid current harmonics and the adaptability to grid impedance variations are enhanced. Simulation and experimental results verify the effectiveness of the proposed grid voltage fractional‐order weighted feedforward scheme.

A weighted average mixed feedback control method based on LCL‐type grid‐connected inverter

SummaryThe weighted average current (WAC) control method has gained recognition for its order reduction characteristics and broad control bandwidth. However, the interaction of digital control delay and grid impedance introduces an inverse resonance peak in the system loop gain, challenging the order reduction properties of conventional WAC control and system passivity across a wide frequency range. Conventional approaches, such as lead compensator‐based delay compensation or weighting coefficient redesign, improve system stability to some extent but fail to retain order reduction characteristics. To address these limitations, this article proposes a new control method known as weighted average mixed feedback, incorporating distinct voltage feedforward paths. By introducing a voltage feedback path, the proposed method reconfigures the system's zero positions, enabling the pole‐zero cancelation in the open‐loop characteristics independent of grid impedance. Additionally, this supplementary path offers impedance reshaping capabilities, enhancing system passivity and adaptability to weak grids. The effectiveness of the proposed control method is verified through simulations and experiments.

An Optimized PLL With Time Delay and Harmonic Suppression for Improved Position Estimation Accuracy of PMSM Based on Levenberg–Marquardt

This paper proposes an optimized phase-locked loop (OPLL) based on Levenberg-Marquardt (LM) to improve the estimation accuracy of the sliding mode observer (SMO) based position estimator. The position estimation suffers from dc bias caused by digital control delay, and harmonic caused by inverter nonlinearity and flux spatial harmonics. The OPLL is constructed with two parts to overcome the above negative effects. The delay phase is preliminarily calculated based on linear prediction, so as to compensate for the lag phase in the estimated back electromotive force (back-EMF); secondly, the objective function is built based on the reference and feedback position error, the former contains an unknown harmonic. The objective function can be minimized by the LM to solve for the harmonic amplitude, then the obtained harmonic is used to offset the harmonic components in the estimated position. Wherein, the required partial derivatives of the LM method can be deduced based on the transfer function of PLL and the delay-compensated back-EMF to achieve a stable update of harmonic amplitude. Finally, the corresponding comparative experiments in steady-state and dynamic conditions proved the superiority of the proposed method applied to permanent magnet synchronous motors.

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

SummaryThis paper proposes a wireline serial link transceiver for on‐package die‐to‐die links based on 12‐nm fin field‐effect transistor (FinFET) technology. The link is crucial for improving the computational performance of larger systems built from chiplets. To achieve high pin/energy efficiency and prevent traditional single‐ended signaling disadvantages, the transceiver adopts single‐ended ground‐reference signaling (GRS) to transfer information. To precompensate for the frequency‐dependent loss, retain the advantages of GRS, and avoid the disadvantages of traditional AC‐coupled equalizer, the transmitter in the transceiver adopts a DC‐coupled switched‐capacitor charge pump equalizer that can transmit GRS and its equilibrium value can be adjusted according to the channel attenuation. This paper proposes a method for timing de‐skew using digital control delay lines to eliminate the timing skew between data and the clock. In addition, this paper presents a duty cycle corrector to avoid duty cycle distortion, with an adjustment range of 44.5% to 52% and a power dissipation of only 30 W. The transceiver has an area of 1.016 0.676 mm2, including one clock lane link and four data lane links. At a nominal 0.8‐V power supply voltage, the aggregate eye‐opening of the measured 25 Gb/s data on an organic substrate channel with an attenuation of −2.2 dB over 6 mm is 0.675 UI, with a bit error rate (BER) of less than 10−12 and an energy efficiency of 1.01 pJ/bit.

Using IIR Filter in Fractional Order Phase Lead Compensation PIMR-RC for Grid-Tied Inverters

Phase lead compensation precision dramatically affects the performance of repetitive controller (RC). Integer order phase lead compensation of proportional integral multi-resonant type RC (PIMR-RC) with low sampling frequency cannot meet the need of fine phase compensation. In addition, the digital control delay affects the actual modeling of the system, and then influences the precision phase compensation. To finely compensate the phase lag of the PIMR-RC system, this paper proposes a fine fractional order phase lead compensation PIMR-RC (FL-PIMR-RC) scheme based on a novel phase lead infinite impulse response (IIR) filter. Its comprehensive synthesis is systematically detailed, including actual modeling considering 1.5-period digital control delay, IIR fractional lead filter design, stability analysis, and parameter optimization. Finally, experiments on a 2 kW prototype grid-tied inverter are successfully carried out to verify the solution.

A regular sampling method based on the immediate mode for improving the stability of inverters

The shadow mode-based regular sampling methods are usually used in the digital control of power inverters, which introduce a control delay of one and a half sampling periods. The control delay affects the closed loop bandwidth and the stability of dc–ac inverters. Recently, regular sampling methods based on the immediate mode is emerging and helpful for reducing the digital control delay. When employing the immediate mode, the induced vertical crossings may arouse the duty-cycle loss and dead-band effect during the modulation process, which deteriorate the normal operation of the inverters. Although the duty-cycle loss can be avoided by forcing the PWM signal to flip at the occurrence of vertical crossings, the introduced dead bands still exist. Thus, this paper investigates the phenomenon of vertical crossings and proposes a control algorithm composed of predicting the occurrence of vertical crossings and compensating the dead-band effect for regular sampling methods based on the immediate mode. Finally, experimental results on a single-phase dc–ac inverter prototype are provided to compare the efficacy of different approaches.

A small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit

AbstractThis paper proposes a small‐area and low‐power all‐digital duty cycle corrector with de‐skew circuit. By adopting the proposed delay unit containing a pre‐charge transistor, half cycle delay line can accurately generate half‐cycle delay, thus ensuring that the circuit can achieve duty cycle correction with small area and low power. To achieve high‐precision clock synchronization, the proposed de‐skew circuit utilizes a high‐resolution two‐stage digital control delay line to eliminate the additional clock skew between the input clock and output clock of the circuit. The test chip is fabricated in 130 nm CMOS process and the area only occupies 0.009 mm2. The chip testing results show that duty cycle correction error is within 3.2% and phase error is less than 16 ps when input duty cycle from 20% to 80% at the frequency range from 380 MHz to 1.25 GHz. And the proposed circuit only consumes 3 mW when supply voltage is 1.2 V and clock frequency is 1 GHz.

Sensorless Control Method of High-Speed Permanent Magnet Synchronous Motor Based on Discrete Current Error

When the Surface-Mounted Permanent Magnet Synchronous Motor (SPMSM) is in the condition of high-speed and low carrier-wave ratio, the performance of sensorless control is more affected by digital control delay, parameter inaccuracy, and other factors. This paper presents a sensorless control method based on the static error between the discrete d-axis current and the corresponding reference value. If there is no error in position angle, the discrete d-axis current should have no static error approximately. In addition, the static error of the d-axis current is related to the speed, so the PI controller with a variable proportional integral coefficient is used to ensure a stable error compensation performance in a wide speed range. The proposed method can accurately compensate the estimated rotor position of the motor under high-speed and low carrier ratio conditions and improve the accuracy of sensorless control. It provides an effective measure for the stable and reliable acceleration of electric vehicles and has specific practical significance for the development of electric vehicle control.

A sensorless control system of permanent magnet synchronous motor for electric locomotive based on improved high-frequency rotating injection method

The mechanical sensor of electric locomotive is easy to lose, leading to position measurement error, which deteriorates the performance of permanent magnet synchronous motor (PMSM) drive system. Therefore, a limp-home mode based on high-frequency injection sensorless strategy is proposed. The signal processing of conventional high-frequency rotating injection needs several filters, and the delay has an impact on estimated position, which is phase-based demodulation. In this paper, an amplitude-based demodulation strategy is proposed, which needs only one low-pass filter, meanwhile the digital control delay can be canceled automatically. Accordingly, the position estimation precision and robustness can be enhanced with the aid of proposed method. The feasibility and effectiveness of theoretical analysis is verified on an 18-kW PMSM drive system experimental platform.

Modified Passivity-Based Control for LCL-Filtered Grid-Tied Inverter with Output Admittance Reshaping

As a nonlinear control method, the Euler–Lagrange- (EL-) based passivity-based control (PBC) has been studied for grid-tied converters based on energy function to achieve better performance. However, the EL-based PBC method is dependent on an accurate mathematical model. In the traditional EL-based PBC research for LCL-filtered grid-tied inverter, the effect of the digital control delay is rarely considered and the stability under the grid impedance uncertainties is not discussed, especially in the capacitive grid or complex weak grid. To address these concerns, this study proposes a modified EL-based PBC method based on the output admittance reshaping for LCL-filtered grid-tied inverters. The system’ passive region is expanded by adding capacitor current feedback loop up to the Nyquist frequency. The potential resonance is thus eliminated irrespective of the grid impedance. Additionally, the stable region and control parameters design methods of the modified EL-based PBC method with inverter-side control are also carried out. To verify the correctness of the theoretical analysis, both simulation and experimental results are investigated from a 3 kW grid-tied inverter prototype.

A Novel SPMSM Sensorless Drive Using Discrete-Time Synchronous-Frequency Adaptive Observer Under Low Frequency Ratio

To improve the stability and accuracy of the estimated position using the conventional sliding mode observer (CSMO) under low frequency ratio (LFR), this article proposes a novel discrete-time synchronous-frequency adaptive observer (SFAO) for surface-mounted permanent magnet synchronous motor (SPMSM) sensorless drives. The proposed SFAO has merits of high amplitude and zero-phase lag of resonant controller at synchronous frequency. The sign function and the low-pass filter (LPF) of CSMO in the proposed observer can be removed and conducive to dispel the inherent chattering of the CSMO as well as phase shift produced by the LPF. Then, taking into account the digital control delay and discretization truncation error, an exact complex-vector discrete-time model in the stationary coordinate is developed. Based on that, the direct discrete-time domain design approach is utilized in the proposed observer, which can be devised by pole placement directly on complex <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">z</i> -domain to assure the stability and position estimation accuracy under LFR. Finally, the availability of the proposed discrete-time SFAO scheme is verified via experiments on a 2.1-kW SPMSM drive.

Adaptive Self-Tuned Current Controller Design for an LCL-Filtered LC-Tuned Single-Phase Shunt Hybrid Active Power Filter

This paper proposes an adaptive self-tuned current controller design for an LCL-filtered LC-tuned single-phase shunt hybrid active power filter (HAPF), which offers adaptability and flexibility of the control system to filter parameters changes. System modelling and online identification of parameters are presented. Then, a systematic self-tuned controller (STC) design is proposed to calculate the controller parameters and obtain the final control law adaptively. The exact HAPF parameters design is described and the overall closed-loop stability evaluation with considering digital control delay is discussed in this paper. To confirm the theoretical achievements, simulations and experimental tests on a real prototype system are performed. The results are in good accordance and demonstrate the effectiveness and superior performance of the suggested control technique. Furthermore, a comprehensive comparison between the proposed control technique and other controllers is provided to show the superiority of the proposed system from different aspects.

Analysis and Control of Current Harmonic in IPMSM Field-Oriented Control System

There is a certain amount of current harmonics in interior permanent magnet synchronous motor. In order to accurately control the current harmonic, this article focuses on three aspects: establishing current harmonic calculation model, extracting current harmonic, and designing current harmonic regulator. A current harmonic calculation model, which considers the effect of voltage harmonics induced by current controllers and digital control delay on the initial phase angle of voltage harmonics, is established for the first time. With the help of multiple synchronous rotating frame transformation, a current harmonic extraction method more suitable for motor drive field, which aims to extract the current harmonic characteristics of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</i> -axis and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">q</i> -axis currents, is proposed. On this basis, the controlled quantity and control quantity are unified in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d–q</i> coordinate frame for analyzing the coupling relationship of current harmonic characteristics. And then a PI current harmonic regulator, including current harmonic decoupling and voltage harmonic initial phase angle compensation, is constructed, so as to realize the effective control of current harmonics. Finally, the effectiveness and superiority of the proposed method are verified by simulation and experiments.

Cascaded control for LCL filter based grid‐tied system with reduced sensors

This work implements a cascaded control for the LCL filter-based grid-connected neutral point clamped (NPC) inverter with the reduced sensor. The conventional three-loop control requires two current sensors for the inverter side, two voltage sensors for the voltage side, and two current sensors for the grid side in total for sensing. This work proposes a novel cascaded control scheme that allows a considerable reduction of grid-side current sensors and capacitor-side voltage sensors. Only two inverter-side current sensors are required for the same. The sensing point is implemented by the proposed estimation algorithm. As an outcome, the hardware complexity, weight, size, and implementation cost of the system are downsized. A comparative assessment is performed between the conventional technique and the proposed methodology. The system is analysed for grid inductance and LCL filter parametric variations in order to assure the robustness and stability of the system. In addition, the system is also investigated for the influence of digital control delay. The implemented system offers enhanced system stability and improved dynamic performance. In order to meet grid regulation, it offers an economical solution. The proposed system is justified by simulated results on the MATLAB/Simulink platform and verified by the experimental results.

Impedance Characteristics and Harmonic Analysis of LCL-Type Grid-Connected Converter Cluster

This study addresses the output impedance model of the LCL-type grid-connected converter considering the dead-time effects and the digital control delay. The model shows that the digital control delay will affect the accuracy of the output impedance of the grid-connected converter, and the dead-time effects are only equivalent to superimposing a disturbance voltage on the original output impedance model. The derived output impedance model is verified by comparing it with the switching model in the PSIM simulation environment. The harmonic interaction between converter cluster and utility grid is modeled and analyzed based on the output impedance model. A combined harmonic suppression strategy is incorporated into every converter control scheme to suppress the harmonic interaction. Simulation results are presented to demonstrate the correctness of harmonic interaction analysis and the effectiveness of the proposed suppression strategy.

A Generalized Real-Time Computation Method With Dual-Sampling Mode to Eliminate the Computation Delay in Digitally Controlled Inverters

Digital control has been widely adopted in grid-connected inverters, thanks to easy implementation of complicated control algorithms. However, the digital control delay deteriorates the performance of the inverter and tends to cause system instability. In this article, the generating mechanism of the digital control delay, including computation delay and pulsewidth modulation delay, is analyzed. Then, a generalized real-time computation method with a dual-sampling mode is derived to directly eliminate the computation delay, based on two- and multilevel phase-legs. On this basis, the operation principle of the method for three- and single-phase inverters with two- and multilevel topologies is elaborated. Finally, the experimental and simulation results from three- and single-phase <i>LCL</i>-type grid-connected inverters are provided to verify the effectiveness of the proposed method.

An Angle-Compensating, Complex-Coefficient PI Controller Used for Decoupling Control of a Permanent-Magnet Synchronous Motor

An asymmetric, cross-coupling effect, as well as digital control delays, in a permanent-magnet synchronous motor (PMSM) will deteriorate its current-control performance in the high-speed range, especially for electric motors used in electric vehicles (EVs) with features such as high-power density and a low carrier/modulation frequency ratio. In this paper, an angle-compensating, complex-coefficient, proportional-integrator (ACCC-PI) controller is proposed, which aims to provide an excellent decoupling performance even with considerable digital control delay. Firstly, the current open and closed loop complex-coefficient transfer functions were established in the synchronous rotation coordinate system. The proposed method, along with existing ones, were then evaluated and theoretically compared. On this basis, the parameter-tuning method of the ACCC-PI controller was presented. Finally, simulation and experimental results proved the correctness of the theoretical analysis and the proposed method.

Robust Delay Compensation Strategy for LCL-Type Grid-Connected Inverter in Weak Grid

Capacitor-current-feedback active damping has been widely adopted in digitally controlled LCL-type grid-connected inverters (GCIs). However, their digital control delay causes the system stability to deteriorate within a negative damping range. Particularly, in a weak grid, such GCIs are prone to be unstable against the grid impedance variation. To address the above problem, a delay compensation strategy is proposed for an LCL-type GCI, in which a second-order low-pass filter (LPF) is inserted into the capacitor-current-feedback path. This increases the virtual-positive-resistance-region from one-sixth of the sampling frequency to almost within the Nyquist frequency. Therefore, the robustness of the grid-connected inverter can be significantly enhanced against the grid impedance variation. Furthermore, to ensure the system stability and improve the injecting current tracking performance, a proportional complex integral (PCI) strategy is adopted. More specifically, a robustness analysis is conducted under discrete domain. Finally, a 2-kW prototype is constructed, and the experimental results confirm the effectiveness of the theoretical expectations.

Capacitor-Current-Feedback With Improved Delay Compensation for LCL-Type Grid-Connected Inverter to Achieve High Robustness in Weak Grid

To attenuate the resonance of the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LCL</i> filter, capacitor-current-feedback (CCF) active damping has been extensively adopted in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LCL</i> -Type grid-connected inverters. Owing to the appearance of a negative damping region caused by the digital control delay, however, the damping performance has significantly deteriorated, thus the system is susceptible to being unstable under weak grid operation. To address this issue, this paper proposes an improved delay compensation method, which can effectively extend the boundary frequency of the positive equivalent resistance region from <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f_s</i> /6 to <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f_s</i> /4. Furthermore, the resonance frequency forbidden region of the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LCL</i> filter can be eliminated. In doing so, strong robustness against the grid impedance variation and high noise immunity can be achieved. To guarantee the system stability and obtain good control performance after compensation, a detailed parameters design procedure for the current regulator and the CCF coefficient is further presented. At last, experimental results are provided to confirm the theoretical analysis and verify the effectiveness of the proposed delay compensation method.