Analog-to-digital Research Articles

Communication Prototype for Post-Stroke Patients Using Electrooculography (EOG)

Background this prototype is intended for post-stroke patients experiencing disabilities in their daily activities, particularly in communication with others. The challenge they face is difficulty in communication, leading to a diminished quality of life for post-stroke patients. The purpose of innovating this communication aid prototype is to facilitate communication between post-stroke patients and caregivers. The method employed in the post-stroke communication aid prototype utilizes Electrooculography (EOG) signals generated from eye muscle movements during eye gazes, captured by the MaM Sense sensor. The variation in Analog-to-Digital Converter (ADC) values in the MaM Sense sensor is exploited to produce various forms of EOG signals. The resultant command signals from this method are processed by a microcontroller and displayed on a 20 x 4 Character LCD. Testing was conducted on 9 healthy individuals, comprising 5 males and 4 females. To ensure the prototype's functionality, testing was also performed on 1 post-stroke patient. The success rate of MaM Sense sensor readings was 80.5% for the 4 communication modes employed, involving 4 eye gaze movements: right gaze, left gaze, upward gaze, and downward gaze. Thus, the post-stroke communication aid prototype proves effective in assisting communication for post-stroke patients and aiding caregivers in understanding the patients' desires. In the future, a wireless system may be implemented for the acquisition of EOG signals attached to the face to minimize the use of cables.

Comparative analysis of the effectiveness of quadratus lumborum and transversus abdominis muscle blocks for postoperative pain relief during laparoscopic robot-assisted total hysterectomy.

The purpose of this study was to compare and evaluate the analgesic effectiveness of quadratus lumborum block (QLB) and transversus abdominis plane bloc block (TAPB) after laparoscopic robot-assisted total hysterectomy. Materials and methods. A prospective study of female patients (n=101), with physical status ASA I-II, who underwent laparoscopic robot-assisted total hysterectomy under multicomponent general anesthesia. In random order, patients were randomized into three groups: the first group (CON, n=40) - control, where no blocks were performed, the second group (TAPB, n=30) - a blockade of the transverse abdominis muscle, the third group (QLB, n= 31) – blockade of the quadratus lumborum muscle was performed. After surgery, pain was assessed using a 10-point digital visual analogue scale, and postoperative nausea and vomiting were assessed. (PONV) Average arterial pressure and heart rate were recorded. Additionally, the next morning, a survey was conducted to assess the well-being and satisfaction of patients. Results. There were no differences between the groups in terms of demographic characteristics, duration of surgery, and analgesic consumption during the intraoperative period. The severity of postoperative pain was higher (p<0.05) in the control group than in the blockade groups. Both block groups demonstrated lower pain scores at all time points assessed. The latest need for analgesics was in the QLB group. Mean arterial pressure (MAP) values differed only in the first 2 hours after surgery between the CON and TAPB groups (p<0.05). PONV one hour after surgery was more observed in the control group and less in the QLB group (p<0.05). According to the results of a survey conducted on the day after surgery, the number of patients satisfied with the anesthesia and assistance provided in the recovery room in the groups with blockade (TAPB, QLB) was 2.1-5.3% higher (p>0.05). More patients from the QLB group (p<0.05) noted very good and good health, and most patients (p<0.05) from the CON and TAPB group noted satisfactory health. Conclusion. The use of interfascial blocks for postoperative pain relief (TAPB, QLB) after laparoscopic robot-assisted hysterectomy improves the quality of pain relief and the well-being of patients. Benefits of QLB include better pain relief, reduced incidence of PONV, and greater patient satisfaction. TARP has shown equally good results, and this method is easier to perform.

A Low-Power 5-Bit Two-Step Flash Analog-to-Digital Converter with Double-Tail Dynamic Comparator in 90 nm Digital CMOS

Low-power portable devices play a major role in IoT applications, where the analog-to-digital converters (ADCs) are very important components for the processing of analog signals. In this paper, a 5-bit two-step flash ADC with a low-power double-tail dynamic comparator (DTDC) using the control switching technique is presented. The most significant bit (MSB) in the proposed design is produced by only one low-power DTDC in the first stage, and the remaining bits are generated by the flash ADC in the second stage with the help of an auto-control circuit. A control circuit produced reference voltages with respect to the control input and mid-point voltage (Vk). The proposed design and simulations are carried out using 90 nm CMOS technology. The result shows that the peak differential non-linearity (DNL) and integral non-linearity (INL) are +0.60/−0.69 and +0.66/−0.40 LSB, respectively. The signal-to-noise and distortion ratio (SNDR) for an input signal having a frequency of 1.75 MHz is found to be 30.31 dB. The total power consumption of the proposed design is significantly reduced, which is 439.178 μW for a supply voltage of 1.2 V. The figure of merit (FOM) is about 0.054 pJ/conversion step at 250 MS/s. The present design provides low power consumption and occupies less area compared to the existing works.

A fully integrated temperature sensor with an inaccuracy of ±0.4 °C (3σ) from −55 to 150 °C

A high-accuracy fully integrated temperature sensor for a wide temperature range up to 150 °C is presented in this article. The sensing circuits with the asymmetric operational amplifier and bias current optimization is applied to eliminate the component mismatch error and enhance the accuracy. The asymmetric operational amplifier can remove the offset voltage avoiding the switching noise compared with the chopping method. An extended counting analog-to-digital convertor (ADC) is proposed as the readout interface due to its compact structure and high efficiency. An easily-achieved dynamic range improvement is devised. Benefited by the dynamic range improvement, the 14-bit ADC can achieve a resolution of 0.0156 °C. This temperature sensor is fabricated in a 0.18-μm CMOS process, and it achieves an accuracy of ±0.4 °C (3σ) from −55 to 150 °C.

Design of a low-power Digital-to-Pulse Converter (DPC) for in-memory-computing applications

Data converters such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), digital-to-time converters (DTCs), time-to-digital converters (TDCs), among others, are considered some of the most essential blocks in the field of integrated circuit design. In this work, we introduce a novel type of data converter known as the Digital-to-Pulse converter (DPC) and present its novel analog flow circuit implementation. The DPC system is a critical component in emerging artificial neural network accelerators and in-memory computing systems. The DPC system presented in this study offers two distinct operating modes. The first mode is the generation of a single pulse with a width that is modulated by the digital input. The second mode is an n-bit digital to discrete pulse converter, where the number of generated pulses is directly related to the value of the digital input. The proposed DPC system offers designers a high level of flexibility in shaping the characteristics of the output pulses, including the number of pulses, pulse width, and pulse amplitude. This empowers designers to accommodate different application requirements and scenarios effectively. The proposed circuit has been verified and tested using Virtuoso Cadence circuit tools in 180 nm CMOS technology with post-layout simulation and analysis. The results indicate a significant enhancement in average power consumption (∼12×), layout area (∼5×), and Latency (∼1.4×) with the proposed system compared to the digital Register Transfer Level (RTL) implementation under a power supply of 1.8V and a clock frequency of 1 GHz in the Application Specific Integrated Circuits (ASIC) flow. This demonstrates the suitability of the proposed system for low-power and high-speed applications.

Integrated photonic modular arithmetic processor

Integrated photonic computing has emerged as a promising approach to overcome the limitations of electronic processors in the post-Moore era. However, present integrated photonic computing systems face challenges in achieving high-precision calculations, consequently limiting their potential applications, and their heavy reliance on analog-to-digital (AD) and digital-to-analog (DA) conversion interfaces undermines their performance. Here we propose an innovative photonic computing architecture featuring scalable calculation precision and, to our knowledge, a novel photonic conversion interface. By leveraging the residue number system (RNS) theory, the high-precision calculation is decomposed into multiple low-precision modular arithmetic operations executed through optical phase manipulation. Those operations directly interact with the digital system via our proposed optical digital-to-phase converter (ODPC) and phase-to-digital converter (OPDC). Through experimental demonstrations, we showcase a calculation precision of 9 bits and verify the feasibility of the ODPC/OPDC photonic interface. This approach paves the path towards liberating photonic computing from the constraints imposed by limited precision and AD/DA converters.

Enhancing IoT data acquisition efficiency via FPGA-based implementation with OpenCL framework

The increasing demand for real-time data processing in Internet of Things (IoT) applications necessitates the development of efficient and flexible data acquisition systems capable of receiving and processing data from various sensor types. In conjunction with OpenCL, field-programmable gate arrays (FPGAs) have recently emerged as powerful platforms for accelerating data-intensive tasks. This study explored the implementation of an FPGA for data acquisition using OpenCL, aiming to design and implement an efficient data acquisition system tailored for IoT applications. Utilizing OpenCL for FPGA-based data acquisition offers several advantages that contribute to system efficiency, particularly in hardware interfaces between FPGA and external devices used in IoT applications. OpenCL abstracts the complexity of the FPGA hardware interface to external DDR memory for storing temporary data and a communication interface to the host CPU for transferring the collected data and enabling remote access, enabling developers to focus on algorithm design and functionality. To enable data reading from an external analog-to-digital converter (ADC) chip for IoT applications, we developed a component module that utilizes the Avalon-streaming interface and can stream the data to the OpenCL kernel. An experiment was conducted to demonstrate the performance of our proposed design. According to the findings of the experiments, a data acquisition implementation based on an FPGA and OpenCL can simultaneously read analog signals via a multichannel ADC. The proposed design provides a foundation for designing efficient data acquisition solutions, addressing the increasing needs of FPGA-based data acquisition in various IoT environments.

Construction and analysis of symmetric Sprott B multi-attractors with electric implementation

Abstract In chaos theory, a number of systems and models which apparently contain simple ordinary differential equations (ODEs) turn out to show a dynamic characterized by complicated behaviors and complex trajectories. One of such systems is the Sprott B model. We construct some set of multi-attractors based on the Sprott B model where additional parameters and operators are considered. After summarizing important preliminaries relevant to simple chaotic differential systems, the model is firstly solved analytically and numerically, then graphical simulations are provided. The later show coexistence and evolution of two chaotic attractors in a symmetrical representation. Lastly, similar results and expected outcomes are recovered via an electrical circuit implementation, realized using the Field Programmable Gate Array (FPGA) board, the Digital-to-Analog Converter (DAC) and the Rigol Oscilloscope. They also show progressing sets of coexisting multi-attractors.

Analysis of Mueller–Muller Clock and Data Recovery Circuits with a Linearized Model

With the development of high-speed analog-to-digital converter (ADC)-based wireline receivers, the Mueller–Muller clock and data recovery (MM-CDR) circuit has garnered increasing attention. But in the design stage, evaluating the loop performance of MM-CDR circuits in ADC-based wireline receivers is challenging due to the absence of a linearized model for a Mueller–Muller phase detector (MMPD). In this paper, a linearized model of the MMPD is proposed by analyzing the output probability of the MMPD in different transition patterns with random jitter injection, and the model is combined with an entire MM-CDR system to analyze the performance of the MM-CDR loop. Analysis of the linearized model and corresponding simulations indicate that when the reference voltage level in the MMPD is set equal to the amplitude of the average crossing voltage at the intersection of 011 and 110 patterns, the MMPD can obtain the maximum gain, which is determined by jitter, and the jitter transfer function and jitter tolerance can achieve optimum performance.

Validity, reliability and responsiveness of digital visual analogue scales for chronic spontaneous urticaria monitoring: A CRUSE® mobile health study.

CRUSE® is an app that allows patients with chronic spontaneous urticaria (CSU) to monitor their daily disease activity through the use of visual analogue scales (VASs). We aimed to determine the concurrent validity, reliability, responsiveness and minimal important difference (MID) of CRUSE® VASs. We evaluated the properties of three daily VASs: VAS for how much patients were affected by their CSU ('VAS urticaria'), VAS for the impact of urticaria on work/school productivity ('VAS productivity') and the VAS of EQ-5D. Concurrent validity was assessed by measuring the association between each VAS and the Urticaria Activity Score (UAS). Intra-rater reliability was determined based on the data of users providing multiple daily questionnaires within the same day. Test-retest reliability and responsiveness (ability to change), respectively, were tested in clinically stable and clinically unstable users. MIDs were determined using distribution-based methods. We included 5938 patients (67,380 days). Concurrent validity was high, with VAS urticaria being more strongly associated with the UAS score than the remaining VASs. Intra-rater reliability was also high, with intraclass correlation coefficients (ICC) being above 0.950 for all VASs. Moderate-high test-retest reliability and responsiveness were observed, with reliability ICC being highest for VAS EQ-5D and responsiveness being highest for VAS urticaria. The MID for VAS urticaria was 17 (out of 100) units, compared to 15 units for VAS productivity and 11 units for VAS EQ-5D. Daily VASs for CSU available in the CRUSE® app display high concurrent validity and intra-rater reliability and moderate-high test-retest reliability and responsiveness.

Detecting Hidden Voice Recorders via ADC Electromagnetic Radiation

Unauthorized covert voice recording presents a significant threat to privacy-sensitive scenarios, such as confidential meetings and private conversations. Due to their miniaturization and disguise characteristics, hidden voice recorders are difficult to notice. In this paper, we present DeHiREC , the first proof-of-concept system capable of detecting offline hidden voice recorders from their electromagnetic radiations (EMR). We first characterize the unique patterns of the emanated EMR signals and then locate the EMR source, i.e., the analog-to-digital converter (ADC) module embedded in the mixed signal system-on-chips (MSoCs). Since these unintentional EMR signals can be extremely noisy and weak, accurately detecting them can be challenging. To address this challenge, we design an EMR Catalyzing method to actively stimulate the EMR signals and then employ an adaptive-folding algorithm to improve the signal-to-noise ratio (SNR) of the sensed EMRs. We evaluate the performance of DeHiREC on 18 commercial voice recorders under various impacts, including interference from other devices. Experimental results reveal that DeHiREC is effective in detecting all 18 voice recorders and achieves an overall success rate of 94.72% and a recall rate of 92.03% at a distance of 0.2 m.

On the System-Level Design of Noise-Shaping SAR Analog-to-Digital Converters

In this work, the system-level design of noise-shaping (NS) successive-approximation (SAR) analog-to-digital converters (ADCs) is investigated and analyzed. It is shown that despite the fact that the NS SAR architecture shares the same fundamental NS principle with the ΣΔ architecture, there are a few implementation differences that imply different considerations for optimum system-level design, particularly in the selection of the system oversampling ratio (OSR) and consequent resolution of the associated digital-to-analog converter (DAC) for a certain target overall resolution. In addition, the impacts of the OSR value on the power dissipation and figure-of-merit (FOM) are addressed in details.

A Cascaded ReRAM-based Crossbar Architecture for Transformer Neural Network Acceleration

Emerging resistive random-access memory (ReRAM) based processing-in-memory (PIM) accelerators have been increasingly explored in recent years because they can efficiently perform in-situ matrix-vector multiplication (MVM) operations involved in a wide spectrum of artificial neural networks. However, there remain significant challenges to apply existing ReRAM-based PIM accelerators to the most popular Transformer neural networks. Since Transformers involve a series of matrix-matrix multiplication (MatMul) operations with data dependencies, they should write intermediate results of MatMuls to ReRAM crossbar arrays for further processing. Conventional ReRAM-based PIM accelerators often suffer from high latency of ReRAM writes and intra-layer pipeline stalls. In this paper, we propose ReCAT, a ReRAM-based PIM accelerator designed particularly for Transformers. ReCAT exploits transimpedance amplifiers (TIAs) to cascade a pair of crossbar arrays for MatMul operations involved in the self-attention mechanism. The intermediate result of a MatMul generated by one crossbar array can be directly mapped to another crossbar array, avoiding costly analog-to-digital conversions. In this way, ReCAT allows MVM operations to overlap with the corresponding data mapping, hiding the high latency of ReRAM writes. Furthermore, we propose an analog-to-digital converter (ADC) virtualization scheme to dynamically share scarce ADCs among a group of crossbar arrays, and thus significantly improve the utilization of ADCs to eliminate the performance bottleneck of MVM operations. Experimental results show that ReCAT achieves 207.3 ×, 2.11 ×, and 3.06 × performance improvement on average compared with other Transformer acceleration solutions—GPUs, ReBert, and ReTransformer, respectively.

A Wireless Miniature Injectable Device with Memory-Assisted Backscatter for Multimodal Animal Physiological Monitoring.

This paper introduces a wirelessly powered multimodal animal physiological monitoring application-specific integrated circuit (ASIC). Fabricated in the 180 nm process, the ASIC can be integrated into an injectable device to monitor subcutaneous body temperature, electrocardiography (ECG), and photoplethysmography (PPG). To minimize the device size, the ASIC employs a miniature receiver (Rx) coil for wireless power receiving and data communication through a single inductive link operating at 13.56 MHz. We propose a folded L-shape Rx coil with improved coupling to the transmitter (Tx) coil, even in the presence of misalignment, and enhanced quality factor. The ASIC functions alternatively between recording and sleeping modes, consuming 2.55 μW on average. For PPG measurements, a reflection-type PPG sensor illuminates an LED with tunable current pulses. A current-input analog frontend (AFE) amplifies the current of a photodiode (PD) with 30.8 pARMS current input-referred noise (IRN). The ECG AFE captures ECG signals with a configurable gain of 45-80 dB. The temperature AFE achieves 0.02 ̊C inaccuracy within a sensing range between 27-47 ̊C. The AFE outputs are sequentially digitized by a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an effective number of bits (ENOB) of 8.79. To improve the reliability of data transmission, we propose a memory-assisted backscatter scheme that stores ADC data in an off-chip memory and transmits it when the coupling condition is stable. This scheme achieves a package loss rate (PLR) lower than 0.2% while allowing 24-hour data storage. The device's functionality has been evaluated by in vivo experiments.

EM-Rhythm: An Authentication Method for Heterogeneous IoT Devices

The popularity of IoT devices has penetrated our daily life while posing new challenges in user authentication. Today’s solutions, e.g., passwords, fingerprints, and FaceIDs, primarily rely on specialized sensors or user interfaces to collect user’s identification information, which may not universally exist on heterogeneous IoT devices. In this paper, we propose a novel user authentication method that exploits the EM emanations radiated from IoT devices. Our design is motivated by the observation that human touches on the IoT device can lead to time-varying coupling between these two. Consequently, it impacts the device’s EM emanations that can be picked up by its inertial ADC (analog-to-digital converter) interfaces. We ask the user to tap on the device rhythmically following a self-determined melody, such that the human-coupled EM emanations vary accordingly. We thus extract the rhythm pattern as the user’s secure password named EM-Rhythm . To examine its effectiveness, EM-Rhythm is implemented on a wide range of IoT devices. We show that our scheme achieves authentication accuracy as high as 98.67% with less than three login attempts. Besides, it is robust against various types of attacks and maintains stable performances under various settings. EM-Rhythm also exhibits satisfactory usability in terms of memorability and time consumption.

Comparative Study and Simulation of ADC Using MATLAB/SIMULINK

Digital systems play an important role in science and engineering field due to high noise immunity,high accuracy and required less space for data storage. And since all physical quantities are available in analog form so we need device which convert these quantities into digital one this device is called analog to digital converter (ADC).In this paper we present and simulate model for ADC using MATLAB/SIMULINK .

Rapid phase current sampling in a permanent magnet synchronous motor servo system utilizing flexible memory controller bus

Background The permanent magnet synchronous motor (PMSM) servo system, integral to robots and other high-precision motion control applications, has its performance directly influenced by the current loop in the PMSM servo system. Though the theoretical adjustment time of the current loop can approach the electrical time constant of PMSM in order of magnitude, constraints such as control frequency make the adjustment time significantly larger than this theoretical limit. Methods This paper introduces a PMSM servo system using a flexible memory controller (FMC) bus for rapid phase current sampling. It leverages an independent current sampling module, equipped with an external analog-to-digital (AD) conversion chip for precise sampling of the output phase current of the PMSM. The sampling precision is 16-bit with a range of 0-3V. The sampled signal is preprocessed by a field-programmable gate array (FPGA), with the phase current data finally transmitted to the primary control chip through the FMC bus. Results By implementing this rapid current sampling architecture, we have successfully reduced the current sampling time by 95.4% while maintaining sampling accuracy. This scheme also substantially shortens the microcontroller unit’s (MCU) interrupt response time, potentially enhancing the current loop's control frequency, ultimately increasing the current loop bandwidth to 20kHz. Conclusions In conclusion, the proposed PMSM servo system with rapid current sampling significantly enhances the performance of the current loop. This advancement in sampling efficiency and control frequency offers substantial improvements for high-precision motion control applications, making it a valuable contribution to the field.

Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection

This paper presents a novel background calibration method for pipelined analog-to-digital converters (ADCs) using a time-delay neural network (TDNN), which is optimized through genetic algorithm (GA) techniques. The proposed technique leverages TDNN to create enhanced feature sets, significantly improving the calibration of nonlinear errors exhibiting memory effects. It harnesses the GA's global optimization capabilities for feature selection, effectively reducing the feature dimension and consequently alleviating the NN's computational burden. A parallel pipeline architecture is devised for the calibration circuit, with its implementation realized on FPGA to facilitate forward inference processing. The inference circuit is synthesized using TSMC's 90 nm CMOS process, achieving a power consumption of 40.11 mW and an area of 0.45 mm2. Simulations based on MATLAB for a 14-bit Pipelined ADC demonstrate that the proposed calibration method significantly improves the SFDR from 59.77 dB to 165.52 dB, and ENOB from 8.79 bits to 19.23 bits, surpassing the target ADC's specifications. Moreover, the dimensionality of features is effectively reduced by up to 34 % without compromising the calibration performance.

Multi-channel photonic sampled ADC with hybrid deep-learning for distortion recovery

Analog-to-digital converter (ADC) is indispensable components in modern information systems, and photonic technologies have emerged as promising avenues for overcoming bottlenecks in ADC performance. This paper introduces a novel approach: a photonic sampled ADC integrated with a neural network that combines Convolutional Neural Networks (CNNs) and Transformers for data recovery. The proposed system utilizes a multi-wavelength optical sampling pulse train interleaved in the time domain through fiber dispersion. Sampled signals are quantified in parallel channels by electronic ADC (EADC). Through supervised training, the hybrid deep neural network extracts both local and global features of photonic system defects, enabling the recovery of distorted data. Experimental validation showcases the effectiveness of this architecture, achieving successful reconstruction of radio frequency (RF) signals at a sampling rate of 12 Giga-samples per second (Gs/s) with an effective number of bits (ENOB) of 7.13. The results underscore the potential of the proposed architecture in achieving high conversion accuracy in multi-channel photonic sampled ADCs.

A 68.5 dB-SNDR, 12.4-fJ/conv.-step, 100-MS/s pipelined-SAR ADC with PVT-enhanced circuitry

This paper presents a signal-chain friendly 12-bit pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) in 40nm CMOS, which is optimized to achieve a 68.5 dB-SNDR, 100-MS/s sample rate with 54.5% of maximum available input range. The implemented ADC employs an improved clock booster and latch-register to achieve high on-conductance of nmos switches and low-leakage data storage. It also explores an adaptive non-overlapping complementary clock generator and a dedicated VCM buffer to accommodate process, voltage, and temperature (PVT) conditions. The relative variation of non-overlapping time is reduced by 50% compared to the conventional method, and the signal-to-distortion ratio (SDR) of residue amplification is improved by 8dB . Moreover, on-chip bit weight calibration is implemented to address the gain error brought by capacitor mismatch and inner-stage gain error. The prototype ADC is simulated under 5 corners, −40 to 125°C, and 1.1V±2.5%. For a Nyquist input, the simulated SNDR under typical corner is 68.5dB , which can remain over 66dB under PVT conditions. The achieved Walden Figure of Merit (FoM) is 12.4-fJ/conv.-step.