Digit-serial Systolic Multiplier Research Articles

Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix–Vector Product Approach

Systolic finite field multiplier over $GF(2^{m})$ , because of its superior features such as high throughput and regularity, is highly desirable for many demanding cryptosystems. On the other side, however, obtaining high-performance systolic multiplier with relatively low hardware cost is still a challenging task due to the fact that the systolic structure usually involves large area complexity. Based on this consideration, in this paper, we propose to carry out two novel coherent interdependent efforts. First, a new digit-serial multiplication algorithm based on polynomial basis over binary field $(GF(2^{m}))$ is proposed. Novel Toeplitz matrix–vector product (TMVP)-based decomposition strategy is employed to derive an efficient subquadratic space complexity. Second, The proposed algorithm is then innovatively mapped into a low-complexity systolic multiplier, which involves less area-time complexities than the existing ones. A series of resource optimization techniques also has been applied on the multiplier which optimizes further the proposed design (it is the first report on digit-serial systolic multiplier based on TMVP approach covering all irreducible polynomials, to the best of our knowledge). The following complexity analysis and comparison confirm the efficiency of the proposed multiplier, that is, it has lower area-delay product (ADP) than the existing ones. The extension of the proposed multiplier for bit-parallel implementation is also considered in this paper.

Novel Hybrid-Size Digit-Serial Systolic Multiplier over GF(2m)

Because of the efficient tradeoff in area–time complexities, digit-serial systolic multiplier over G F ( 2 m ) has gained substantial attention in the research community for possible application in current/emerging cryptosystems. In general, this type of multiplier is designed to be applicable to one certain field-size, which in fact determines the actual security level of the cryptosystem and thus limits the flexibility of the operation of cryptographic applications. Based on this consideration, in this paper, we propose a novel hybrid-size digit-serial systolic multiplier which not only offers flexibility to operate in either pentanomial- or trinomial-based multiplications, but also has low-complexity implementation performance. Overall, we have made two interdependent efforts to carry out the proposed work. First, a novel algorithm is derived to formulate the mathematical idea of the hybrid-size realization. Then, a novel digit-serial structure is obtained after efficient mapping from the proposed algorithm. Finally, the complexity analysis and comparison are given to demonstrate the efficiency of the proposed multiplier, e.g., the proposed one has less area-delay product (ADP) than the best existing trinomial-based design. The proposed multiplier can be used as a standard intellectual property (IP) core in many cryptographic applications for flexible operation.

Low Register-Complexity Systolic Digit-Serial Multiplier Over Based on Trinomials

Digit-serial systolic multipliers over $GF(2^m)$ based on the National Institute of Standards and Technology (NIST) recommended trinomials play a critical role in the real-time operations of cryptosystems. Systolic multipliers over $GF(2^m)$ involve a large number of registers of size $O(m^2)$ which results in significant increase in area complexity. In this paper, we propose a novel low register-complexity digit-serial trinomial-based finite field multiplier. The proposed architecture is derived through two novel coherent interdependent stages: (i) derivation of an efficient hardware-oriented algorithm based on a novel input-operand feeding scheme and (ii) appropriate design of novel low register-complexity systolic structure based on the proposed algorithm. The extension of the proposed design to Karatsuba algorithm (KA)-based structure is also presented. The proposed design is synthesized for FPGA implementation and it is shown that it (the design based on regular multiplication process) could achieve more than 12.1 percent saving in area-delay product and nearly 2.8 percent saving in power-delay product. To the best of the authors’ knowledge, the register-complexity of proposed structure is so far the least among the competing designs for trinomial based systolic multipliers (for the same type of multiplication algorithm).

Efficient FPGA Implementation of Low-Complexity Systolic Karatsuba Multiplier Over $GF(2^{m})$ Based on NIST Polynomials

Systolic implementation of Karatsuba algo- rithm (KA)-based digit-serial multiplier over $GF(2^{m})$ on field- programmable gate array (FPGA) platforms has many attractive features, such as efficient tradeoff in area-time complexity and high-throughput rate. But on the other side, it suffers from high register-complexity, which leads to increase in area and power consumption. In this paper, we present an algorithm and architecture for efficient FPGA implementation of KA-based digit-serial systolic multiplier over $GF(2^{m})$ based on the National Institute of Standards and Technology (NIST) recommended polynomials. A number of efficient techniques have been explored and used to realize efficient implementation of these multipliers. First, we propose a novel KA-based approach, where the computational complexity is significantly reduced compared with the existing one. Second, we propose efficient register minimization techniques, such as redundant register removal, two-stage pipelining, and register sharing to reduce the register complexity of the proposed structure. Third, we adopt an efficient FPGA-specific digit-parallel implementation strategy to optimize the area-time–power complexities of the proposed structure on FPGA platforms. The results obtained from FPGA synthesis indicate that the proposed multiplier (for field based on NIST trinomial $GF(2^{233})$ ) has significantly lower area–time–power complexities than the existing designs, e.g., the proposed structure could achieve 65.7% and 73.6% reduction on area-delay product and power-delay product over the best of existing KA-based systolic structures, respectively.

Low-Latency High-Throughput Systolic Multipliers Over <formula formulatype="inline"><tex Notation="TeX">$GF(2^{m})$</tex> </formula> for NIST Recommended Pentanomials

Recently, finite field multipliers having high-throughput rate and low-latency have gained great attention in emerging cryptographic systems, but such multipliers over GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) for National Institute Standard Technology (NIST) pentanomials are not so abundant. In this paper, we present two pairs of low-latency and high-throughput bit-parallel and digit-serial systolic multipliers based on NIST pentanomials. We propose a novel decomposition technique to realize the multiplication by several parallel arrays in a 2-dimensional (2-D) systolic structure (BP-I) with a critical-path of 2TX, where TX is the propagation delay of an XOR gate. The parallel arrays in 2-D systolic structure are then projected along vertical direction to obtain a digit-serial structure (DS-I) with the same critical-path. For high-throughput applications, we present another pair of bit-parallel (BP-II) and digit-serial (DS-II) structures based on a novel modular reduction technique, where the critical-path is reduced to (TA+TX), TA being the propagation delay of an AND gate. A strategy for data sharing between a pair of processing elements (PEs) of adjacent systolic arrays has been proposed to reduce area-complexity of BP-I and BP-II further. From synthesis results, it is shown that the proposed multipliers have significantly lower latency and higher throughput than the existing designs. To the best of authors' knowledge, this is the first report on low-latency systolic multipliers for finite fields where latency is independent of field-order.

Low-complexity digit-serial systolic Gaussian normal basis multiplier for curve-based cryptosystems

Finite field multiplication over GF(2m) is one of the most important arithmetic operations for curve-based cryptosystems, such as elliptic curve cryptosystems and pairing-based cryptosystems. Gaussian normal basis (GNB) multiplier is very suitable for realizing finite field multiplication in curve-based cryptosystems because GNB multiplier is highly efficient in performing square operations of multiplicative inversion, squaring, and exponentiation operations. Therefore, this study will present a digit-serial GNB multiplier with unidirectional systolic array which is suitable for fault-tolerant design and very large scale integrated circuits implementation. The proposed digit-serial GNB multiplier can save about 22% space complexity and requires almost the same time complexity when compared with the existing similar multipliers.

Low-Latency Digit-Serial Systolic Double Basis Multiplier over &lt;formula formulatype="inline"&gt; &lt;tex Notation="TeX"&gt;$\mbi GF{(2^m})$&lt;/tex&gt; &lt;/formula&gt; Using Subquadratic Toeplitz Matrix-Vector Product Approach

Recently in cryptography and security, the multipliers with subquadratic space complexity for trinomials and some specific pentanomials have been proposed. For such kind of multipliers, alternatively, we use double basis multiplication which combines the polynomial basis and the modified polynomial basis to develop a new efficient digit-serial systolic multiplier. The proposed multiplier depends on trinomials and almost equally space pentanomials (AESPs), and utilizes the subquadratic Toeplitz matrix-vector product scheme to derive a low-latency digit-serial systolic architecture. If the selected digit-size is $d$ bits, the proposed digit-serial multiplier for both polynomials, i.e., trinomials and AESPs, requires the latency of $2\left\lceil \!{\sqrt {{m \over d}}} \right\rceil\! $ , while traditional ones take at least $O\left({\left\lceil {{m \over d}} \right\rceil} \right)$ clock cycles. Analytical and application-specific integrated circuit (ASIC) synthesis results indicate that both the area and the time $ \times $ area complexities of our proposed architecture are significantly lower than the existing digit-serial systolic multipliers.

Low-Latency Digit-Serial and Digit-Parallel Systolic Multipliers for Large Binary Extension Fields

For cryptographic algorithms, such as elliptic curve digital signature algorithm (ECDSA) and pairing algorithm, the crypto-processors are required to perform large number of additions and multiplications over finite fields of large orders. To have a balanced trade-off between space complexity and time complexity, in this paper, novel digit-serial and digit-parallel systolic structures are presented for computing multiplication over GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ). Based on novel decomposition algorithm, we have derived an efficient digit-serial systolic architecture, which involves latency of O(√{m/d}) clock cycles, while the existing digit-serial systolic multipliers involve at least O(m/d) latency for digit-size d. The proposed digit-serial design could be used for AESP-based fields with the same digit-size as the case of trinomial-based fields with a small increase in area. We have also proposed digit-parallel systolic architecture employing n-term Karatsuba-like method, where the latency can be reduced from O(√{m/d}) to O(√{m/nd}). This feature would be a major advantage for implementing multiplication for the fields of large orders. From synthesis results, it is shown that the proposed architectures have significantly lower time complexity, lower area-delay product, and higher bit-throughput than the existing digit-serial multipliers.

GF(2m)상의 MSD 우선 알고리즘 기반 디지트-시리얼 곱셈기

In this paper, an efficient digit-serial systolic array is proposed for multiplication in finite field GF() using the polynomial basis representation. The proposed systolic array is based on the most significant digit first (MSD-first) multiplication algorithm and produces multiplication results at a rate of one every "m/D" clock cycles, where D is the selected digit size. Since the inner structure of the proposed multiplier is tree-type, critical path increases logarithmically proportional to D. Therefore, the computation delay of the proposed architecture is significantly less than previously proposed digit-serial systolic multipliers whose critical path increases proportional to D. Furthermore, since the new architecture has the features of a high regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementation.

A digit-serial multiplier for finite field GF(2/sup m/)

In this paper, an efficient digit-serial systolic array is proposed for multiplication in finite field GF(2/sup m/) using the standard basis representation. From the least significant bit first multiplication algorithm, we obtain a new dependence graph and design an efficient digit-serial systolic multiplier. If input data come in continuously, the proposed array can produce multiplication results at a rate of one every /spl lceil/m/L/spl rceil/ clock cycles, where L is the selected digit size. Analysis shows that the computational delay time of the proposed architecture is significantly less than the previously proposed digit-serial systolic multiplier. Furthermore, since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementation.

유한 필드 GF(2m)상에서의 LSB 우선 디지트 시리얼 곱셈기 구현

In this paper we, implement LSB-first digit-serial systolic multiplier for computing modular multiplication A（x）B（x）mod G （x） in finite fields . If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of regularity, modularity, and unidirectional data flow, it shows good extension characteristics with respect to m and L.

Digit-serial-in-serial-out systolic multiplier for Montgomery algorithm

This paper proposes a systematic design of a digit-serial-in-serial-out systolic multiplier for the efficient implementation of the Montgomery algorithm in an RSA cryptosystem. For processing speed, the proposed multiplier can also accommodate bit-level pipelining, thereby achieving sample speeds comparable to bit-parallel multipliers with a lower area. If the appropriate digit-size is chosen, the proposed architecture can meet the throughput requirement of a specific application with minimum hardware. The new digit-serial systolic multiplier is highly regular, nearest-neighbor connected, and thus well suited for VLSI implementation.