Digit-serial Structures Research Articles

Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis

Efficient implementation of finite field multipliers based on a reordered normal basis (RNB) is highly desirable in the current/emerging cryptosystems since it offers almost free realization of squaring operation. Therefore, in this paper, we propose novel bit-parallel and digit-serial finite field multipliers over $GF(2^{m})$ based on RNB. By efficient transformation of the core multiplication algorithm using a unique circular shifting feature, we have derived an efficient algorithm for low-complexity systolic mapping. Both bit-parallel and digit-serial structures of the multipliers are then obtained and optimized to enhance the area–time efficiency. We have also utilized the unique feature of the proposed multiplication algorithm to obtain the systolic multipliers by Karatsubalike decomposition. Detailed analysis and comparison show the superior performance of the proposed implementation. For example, the proposed regular and Karatsuba-based bit-parallel designs involve at least 48.4% less area-delay product (ADP) and 42.2% less power-delay product (PDP) than the best existing ones (37.7% and 55.3% less ADP and PDP on field-programmable gate array platform), respectively. The proposed multipliers, because of their lower area–time complexities, can be used for efficient realization of cryptographic applications.

Novel Hybrid-Size Digit-Serial Systolic Multiplier over GF(2m)

Because of the efficient tradeoff in area–time complexities, digit-serial systolic multiplier over G F ( 2 m ) has gained substantial attention in the research community for possible application in current/emerging cryptosystems. In general, this type of multiplier is designed to be applicable to one certain field-size, which in fact determines the actual security level of the cryptosystem and thus limits the flexibility of the operation of cryptographic applications. Based on this consideration, in this paper, we propose a novel hybrid-size digit-serial systolic multiplier which not only offers flexibility to operate in either pentanomial- or trinomial-based multiplications, but also has low-complexity implementation performance. Overall, we have made two interdependent efforts to carry out the proposed work. First, a novel algorithm is derived to formulate the mathematical idea of the hybrid-size realization. Then, a novel digit-serial structure is obtained after efficient mapping from the proposed algorithm. Finally, the complexity analysis and comparison are given to demonstrate the efficiency of the proposed multiplier, e.g., the proposed one has less area-delay product (ADP) than the best existing trinomial-based design. The proposed multiplier can be used as a standard intellectual property (IP) core in many cryptographic applications for flexible operation.

Scalable and Unified Digit-Serial Processor Array Architecture for Multiplication and Inversion Over GF( $2^{m}$ )

This paper proposes a scalable and unified digit-serial structure, with low space complexity to perform multiplication and inversion operations in $GF(2^{m})$ , based on the bit serial multiplication algorithm and the previously modified extended Euclidean inversion algorithm. In this structure, the multiplier and inverter shares the data-path and thus saves more area resources and power than the case of using separate data-path for each operation. Also, this structure is suitable for fixed size processor that only reuse the core and does not require to modulate the core size when the field size $m$ is modified. This structure is extracted by applying a nonlinear methodology that gives the designer more flexibility to control the processing element workload. Implementation results for of the proposed scalable and unified digit-serial design and previously reported efficient designs show that the proposed scalable structure achieves a significant reduction in area ranging from 64.3% to 85.5% and also achieves a significant saving in energy ranging from 21.9% to 92.5% over them, but it has lower throughput compared with them. This makes the proposed design more suitable for constrained implementations of cryptographic primitives in ultra-low power devices, such as wireless sensor nodes and radio frequency identification devices.

Area-Efficient Subquadratic Space-Complexity Digit-Serial Multiplier for Type-II Optimal Normal Basis of <formula formulatype="inline"><tex Notation="TeX">$GF(2^{m})$</tex> </formula> Using Symmetric TMVP and Block Recombination Techniques

The type-II optimal normal basis (ONB) is popularly used to represent $GF(2^{m})$ for elliptic curve cryptosystems. It is shown in the literature that multiplication in binary fields, including those represented by type-II ONB, shifted polynomial basis, and dual basis, can be transformed into non-symmetric Toeplitz matrix-vector product (TMVP) formulation. In this paper, we show that type-II ONB multiplication can be realized by two symmetric TMVPs (STMVP). Moreover, we have proposed a novel folded TMVP block recombination (TMVPBR) for the computation of STMVP. Based on the proposed folded TMVPBR approach, we have proposed a new digit-serial structure for type-II ONB multiplication, while traditional parallel ONB multipliers are based on non-symmetric TMVPBR approach to achieve subquadratic space complexity architecture. The proposed digit-serial structure also involves subquadratic space complexity. By the theoretical analysis as well as from synthesis result, however, we find that the proposed architecture has significantly less area and less area-delay product compared to the existing digit-serial type-II ONB multipliers.

Low-Latency High-Throughput Systolic Multipliers Over <formula formulatype="inline"><tex Notation="TeX">$GF(2^{m})$</tex> </formula> for NIST Recommended Pentanomials

Recently, finite field multipliers having high-throughput rate and low-latency have gained great attention in emerging cryptographic systems, but such multipliers over GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) for National Institute Standard Technology (NIST) pentanomials are not so abundant. In this paper, we present two pairs of low-latency and high-throughput bit-parallel and digit-serial systolic multipliers based on NIST pentanomials. We propose a novel decomposition technique to realize the multiplication by several parallel arrays in a 2-dimensional (2-D) systolic structure (BP-I) with a critical-path of 2TX, where TX is the propagation delay of an XOR gate. The parallel arrays in 2-D systolic structure are then projected along vertical direction to obtain a digit-serial structure (DS-I) with the same critical-path. For high-throughput applications, we present another pair of bit-parallel (BP-II) and digit-serial (DS-II) structures based on a novel modular reduction technique, where the critical-path is reduced to (TA+TX), TA being the propagation delay of an AND gate. A strategy for data sharing between a pair of processing elements (PEs) of adjacent systolic arrays has been proposed to reduce area-complexity of BP-I and BP-II further. From synthesis results, it is shown that the proposed multipliers have significantly lower latency and higher throughput than the existing designs. To the best of authors' knowledge, this is the first report on low-latency systolic multipliers for finite fields where latency is independent of field-order.

VLSI generalised digit serial architecture for multiplication, division and square root

A novel digit serial combined arithmetic unit for multiplication, division and square root which can be pipelined to the bit level is presented for the first time. The proposed module is based on radix-2 n arithmetic. As a result, it is general for any digit size, n, and can be derived in a straightforward manner without the need to bit parallel or bit serial designs as an initial starting point. Moreover, any adder can be used in the controlled add/shift/subtract basic cell of the generalised digit serial unit. Two digital basic cells are proposed; the first cell is based on the conventional carry feedback adder and hence, the digit serial structure can be pipelined to the digit level only. The second digital cell is based on the carry fed forward adder. The feed forward of the carry out bit allows subdigit pipelining to increase the computation speed. This will give designers greater flexibility in finding the best trade-off between hardware cost and throughput rate. An evaluation of the proposed structure is also presented. It is shown that the bit level pipelined digit serial architecture can achieve better performance than the conventional carry feedback digit serial design and the bit parallel one.

Area-time efficient two's complement square rooting

The conventional two's complement digit serial square root structure processes an n-bit digit every clock cycle. Therefore, it generates one bit of the N-bit square root every m cycles, where m=N/n. Instead of generating K bits every mK cycles, these bits can be generated in m+K−1 cycles only by overlapping K steps of the conventional digit serial algorithm. The new two's complement structure is a tree representation of the conventional one and therefore, it can be considered as a high radix approach of the digit serial structure. It will be shown that the proposed architecture is faster and might be cheaper than the conventional digit serial one. Moreover, it is the first digit serial square root structure which is cheaper and faster than the two's complement binary bit parallel one.

Design methodology for subdigit pipelined digit-serial IIR filters

A novel architecture for high performance two's complement digit-serial IIR filters is presented. The application of the digit-serial computation to the design of IIR filters introduces delay elements in the feedback loop of the IIR filter. This offers the possibility of pipelining the feedback loop inherent in the IIR filters. To fully explore the advantages offered by the use of digit-serial computation, the digit serial structure is based on the feed forward of the carry digit, which allows subdigit pipelining to increase the throughput rate of the IIR filters. A systematic design methodology is presented to derive a wide range of digit-serial IIR filter architectures which can be pipelined to the subdigit level. This will give designers greater flexibility in finding the best trade off between hardware cost and throughput rate. It is shown that the application of digit-serial computations for the realisation of IIR filters combined with the possibility of subdigit pipelining, results in an increase in the computation speed with a considerable reduction in silicon area consumption when compared to an equivalent bit-parallel IIR filter realisations.

Bit-level pipelined digit-serial array processors

A new architecture for high performance digit-serial vector inner product (VIP) which can be pipelined to the bit-level is introduced. The design of the digit-serial vector inner product is based on a new systematic design methodology using radix-2/sup n/ arithmetic. The proposed architecture allows a high level of bit-level pipelining to increase the throughput rate with minimum initial delay and minimum area. This will give designers greater flexibility in finding the best tradeoff between hardware cost and throughput rate. It is shown that sub-digit pipelined digit-serial structure can achieve a higher throughput rate with much less area consumption than an equivalent bit-parallel structure. A twin-pipe architecture to double the throughput rate of digit-serial multipliers and consequently that of the digit-serial vector inner product is also presented. The effect of the number of pipelining levels and the twin-pipe architecture on the throughput rate and hardware cost are discussed. A two's complement digit-serial architecture which can operate on both negative and positive numbers is also presented.

Design, Implementation and Analysis of a New Redundant CORDIC Processor with Constant Scaling Factor and Regular Structure

A new high-speed redundant CORDIC processor is designed and implemented based on the double rotation method, which turns out to be the two-dimensional (2D) Householder CORDIC, a special case of the generalized Householder CORDIC in the 2D Euclidean vector space. The new processor has the advantages of regular structure and high throughput rate. The pipelined structure with radix-2 signed-digit (SD) redundant arithmetic is adopted to reduce the carry-propagation delay of the adders while the digit-serial structure alleviates the burden of the hardware cost and I/O requirement. Compared to previously proposed designs, the new CORDIC processor preserves the constant scaling factor, an important merit of the original CORDIC, and thus does not require any complicated division or square-root operations for variable scaling factor calculation. Furthermore, the processor is well suited to VLSI implementation since it does not call for any irregularly inserted correcting iterations. Both angle calculation mode for computing trigonometric function and vector rotation mode for plane rotations are supported. Practical VLSI chip implementation of the fixed-point redundant CORDIC processor using 0.6 μm standard cell library is given including detailed numerical error analysis.