Digit-serial Computation Research Articles

ECHO: Energy-Efficient Computation Harnessing Online Arithmetic—An MSDF-Based Accelerator for DNN Inference

Deep neural network (DNN) inference demands substantial computing power, resulting in significant energy consumption. A large number of negative output activations in convolution layers are rendered zero due to the invocation of the ReLU activation function. This results in a substantial number of unnecessary computations that consume significant amounts of energy. This paper presents ECHO, an accelerator for DNN inference designed for computation pruning, utilizing an unconventional arithmetic paradigm known as online/most significant digit first (MSDF) arithmetic, which performs computations in a digit-serial manner. The MSDF digit-serial computation of online arithmetic enables overlapped computation of successive operations, leading to substantial performance improvements. The online arithmetic, coupled with a negative output detection scheme, facilitates early and precise recognition of negative outputs. This, in turn, allows for the timely termination of unnecessary computations, resulting in a reduction in energy consumption. The implemented design has been realized on the Xilinx Virtex-7 VU3P FPGA and subjected to a comprehensive evaluation through a rigorous comparative analysis involving widely used performance metrics. The experimental results demonstrate promising power and performance improvements compared to contemporary methods. In particular, the proposed design achieved average improvements in power consumption of up to 81%, 82.9%, and 40.6% for VGG-16, ResNet-18, and ResNet-50 workloads compared to the conventional bit-serial design, respectively. Furthermore, significant average speedups of 2.39×, 2.6×, and 2.42× were observed when comparing the proposed design to conventional bit-serial designs for the VGG-16, ResNet-18, and ResNet-50 models, respectively.

A General Digit-Serial Architecture for Montgomery Modular Multiplication

The Montgomery algorithm is a fast modular multiplication method frequently used in cryptographic applications. This paper investigates the digit-serial implementations of the Montgomery algorithm for large integers. A detailed analysis is given and a tight upper bound is presented for the intermediate results obtained during the digit-serial computation. Based on this analysis, an efficient digit-serial Montgomery modular multiplier architecture using carry save adders is proposed and its complexity is presented. In this architecture, pipelined carry select adders are used to perform two final tasks: adding carry save vectors representing the modular product and subtracting the modulus from this addition, if further reduction is needed. The proposed architecture can be designed for any digit size $\delta $ and modulus $\theta $ . This paper also presents logic formulas for the bits of the precomputation $-\theta ^{-1}\bmod 2^{\delta }$ used in the Montgomery algorithm for $\delta \leq 8$ . Finally, evaluation of the proposed architecture on Virtex 7 FPGAs is presented.

High-performance scalable architecture for modular multiplication using a new digit-serial computation

Modular multiplication with a large modulus plays a vital role in many Public-Key Cryptosystems (PKCs) such as RSA and Elliptic Curve Cryptosystem (ECC). Montgomery modular multiplication algorithm is an efficient multiplication algorithm to simplify the quotient computation. The scalable architecture has been employed to perform the Montgomery modular multiplication with any precision of the modulus. This paper presents and evaluates a novel scalable modular multiplication algorithm/architecture with variable-radix. The proposed algorithm/architecture, which is based on a new digit-serial computation technique, parallelizes the data path to shorten the critical data path. It also reduces the complexity of the high-radix partial multiplications to binary partial multiplications. In this paper, we present implementation results on 0.18-µm ASIC technology, and on Xilinx Spartan 3, Virtex 2 and Virtex 6 FPGA. The results demonstrate that the proposed algorithm/architecture has area×time complexity and performance advantages compared to related algorithms/architectures.

High-Throughput Modular Multiplication and Exponentiation Algorithms Using Multibit-Scan–Multibit-Shift Technique

Modular exponentiation with a large modulus and exponent is a fundamental operation in many public-key cryptosystems. This operation is usually accomplished by repeating modular multiplications. Montgomery modular multiplication has been widely used to relax the quotient determination. The carry-save adder has been employed to reduce the critical path. This paper presents and evaluates a new and efficient Montgomery modular multiplication architecture based on a new digit serial computation. The proposed architecture relaxes the high-radix partial multiplication to a binary multiplication. It also performs several multiplications of consecutive zero bits in one clock cycle instead of several clock cycles. Moreover, the right-to-left and left-to-right modular exponentiation architectures have been modified to use the proposed modular multiplication architecture as its structural unit. We provide the implementation results on a Xilinx Virtex 5 FPGA demonstrating that the total computation time and throughput rate of the proposed architectures outperform most results so far in the literatures.

Efficient Elliptic Curve Point Multiplication Using Digit-Serial Binary Field Operations

This paper details the design of a new high-speed point multiplier for elliptic curve cryptography using either field-programmable gate array or application-specified integrated circuit technology. Different levels of digit-serial computation were applied to the data path of Galois field (GF) multiplication and division to explore the resulting performances and find out an optimal digit size. We provide results for the five National Institute of Standards and Technology recommended curves, outperforming the previous published results. In <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GF</i> (2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">163</sup> ), we achieve a point multiplication in 19.38 μs in Xilinx Virtex-E. Using the modern Xilinx Virtex-5, the point multiplication times in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GF</i> (2 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</i> ) for <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</i> = 163, 233, 409, and 571 are 5.5, 17.8, 33.6, 102.6, 384μs, respectively, which are the fastest figures reported to date.

Quantization error analysis of the radix-4 signed-digit arithmetic

The quantization error characteristics of the signed-digit arithmetic are studied for the application to the MSD (Most Significant Digit) first digit serial computation, where only truncation is allowed for the word-length reduction of the multiplied results. This study shows that truncated results in the signed-digit arithmetic contain very little DC error when a symmetric remainder reduction scheme is employed. The error characteristics are similar to those of the rounding scheme in the two's complement number system. However, the symmetric remainder reduction scheme demands more hardware and delay than the asymmetric reduction scheme.

Design methodology for subdigit pipelined digit-serial IIR filters

A novel architecture for high performance two's complement digit-serial IIR filters is presented. The application of the digit-serial computation to the design of IIR filters introduces delay elements in the feedback loop of the IIR filter. This offers the possibility of pipelining the feedback loop inherent in the IIR filters. To fully explore the advantages offered by the use of digit-serial computation, the digit serial structure is based on the feed forward of the carry digit, which allows subdigit pipelining to increase the throughput rate of the IIR filters. A systematic design methodology is presented to derive a wide range of digit-serial IIR filter architectures which can be pipelined to the subdigit level. This will give designers greater flexibility in finding the best trade off between hardware cost and throughput rate. It is shown that the application of digit-serial computations for the realisation of IIR filters combined with the possibility of subdigit pipelining, results in an increase in the computation speed with a considerable reduction in silicon area consumption when compared to an equivalent bit-parallel IIR filter realisations.

Bit-level pipelined digit-serial multiplier

A new cell architecture for high performance digit-serial computation is presented. The design of this cell is based on the feed forward of the carry digit, which allows a high level of pipelining to increase the throughput rate with minimum latency. This will give designers greater flexibility in finding the best trade-off between hardware cost and throughput rate. A twin-pipe architecture to double the throughput rate of digit-serial/parallel multipliers is also presented. The effects of the number of pipelining levels and the twin architecture on the throughput rate and hardware cost are presented. A two's complement digit-serial/parallel multiplier which can operate on both negative and positive numbers is also presented.

Novel cell architecture for high performance digit-serial computation

A new cell architecture for high performance digit-serial computation is presented. The design of this cell is based on the feedforward of the carry digit, which allows a high level of pipelining to increase the throughput rate. This will give designers greater flexibility in finding the best tradeoff between hardware cost and throughput rate. The effect of the number of pipelining levels on the throughput rate and hardware cost are presented.

Designing systolic arrays using digit-serial arithmetic

A method of transforming systolic arrays using bit-parallel arithmetic into arrays using digit-serial arithmetic is described. Digit-serial computation is an area-time efficient method of doing high-speed arithmetic calculations, having the advantage through appropriate choice of digit and word size of allowing throughput capacity to be matched to design needs. For a certain class of systolic arrays, digit-serial arithmetic allows a further very significant benefit by transforming arrays in which processors are under-utilized into arrays late with 100% processor utilization.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Digit-serial processing techniques

An architecture is presented for hard-wired data-flow algorithms which is based on the transmission of arithmetic data one digit at a time serially, and performance of operations digit-serially on that data. It is shown that digit-serial computation gives rise to particularly efficient chip designs, and that choice of digit-size allows the user to match throughput requirements to specifications. Details of the implementation of the individual operators as a cell-library of silicon CMOS circuits are given and mention is made of the software environment (silicon compiler) which allows the rapid translation of algorithms to integrated circuits. >

A case for digit serial VLSI signal processors

Digit serial architectures, which have digit serial data transmission combined with digit serial computation, are uniquely suited for the design of VLSI signal processors. The speed disadvantages of digit serial input are overcome if the input is overlapped with the computation--what we refer to as digit pipelining. Digit pipelining allows us to break up long strings of combinatorial logic and, thus, to increase the clock rate of the system while still preserving much of the circuit structure. In general, for a modest increase in hardware (which in VLSI translates to a modest increase in area) digit serial architectures offer the potential of higher throughput than equivalent word parallel architectures. Several designs for various digit serial adders are presented. Then two filter examples are discussed that use the digit serial adders to achieve digit pipelining.