Differential Voltage-controlled Oscillator Research Articles

An integrated spiral DGS and an open stub meander-line resonator in the 0.13-µm BiCMOS technology for a 18-GHz band oscillator

In this paper, an 18 GHz voltage-controlled oscillator (VCO) with improved phase noise (PN) and smaller size is proposed. The filter consists of an open stub resonator and an integrated spiral Defective Ground Structure (DGS) resonator. The proposed oscillator is designed in the 0.13-µm SiGe BiCMOS technology. The differential cross-coupled VCO uses a bandpass filter. In this work, the conventional large-size coil is replaced by a resonator based on our proposed open stub resonator and defected ground structure (DGS) where the filter is equivalent to the large coil and the associated capacitors. The use of the filter results in a great reduction of VCO size, low losses, and low power consumption, hence an enhancement in the quality factor. The integrated spiral DGS is etched on the third metal layer (M3) below an open stub meander line onthe top metal layer (TM2) of the 0.13-µm top metal two (TM2) BiCMOS technology. The proposed VCO has a small die area of 0.089 mm2 and has FoMA of 188.8 dB and a power consumption is 13.38 mw. The simulated carrier frequency and phase noise are 18-GHz and −123.59 dBc/Hz (−103.7 dBc/Hz) at 10-MHz (1 MHz) offset frequency, respectively, which results in a figure of merit of 177.37 dB.

Layout of MOS Varactor with Improved Quality Factor for Cross-Coupled Differential Voltage-Controlled Oscillator Applications

In this study, we designed an MOS varactor for application in the differential voltage-controlled oscillator (VCO). To improve the quality factor of the MOS varactor, we proposed a symmetric layout technique of the MOS varactor with reduced parasitic components. Compared with the typical MOS varactor layout, the metal line for the interconnection of the MOS varactors that is inevitable in the typical MOS varactors for the cross-coupled VCO was minimized to reduce the parasitic resistance. In addition, with the reduced interconnection metal line, the overall size of the proposed MOS varactor was also reduced compared with the typical one. To verify the feasibility of the proposed MOS varactor structure, the typical and proposed MOS varactors were designed using a 180 nm RFCMOS process. Compared to the typical MOS varactor, the measured quality factor of the proposed MOS varactor was improved by approximately 32% at the operating frequency of 5.0 GHz. Additionally, we successfully verified that the parasitic capacitance induced by the lossy silicon substrate was reduced in the proposed MOS varactor structure.

A Study of Phase-Adjusting Architectures for Low-Phase-Noise Quadrature Voltage-Controlled Oscillators

Quadrature voltage-controlled oscillators (VCOs) with current-weight-average and voltage-weight-average phase-adjusting architectures are studied. The phase adjusting equalizes the oscillation frequency to the LC-resonant frequency. The merits of the equalization are explained by using Leeson's phase noise equation and the impulse sensitivity function (ISF). Quadrature VCOs with the phase-adjusting architectures are fabricated using 180-nm TSMC CMOS and show low-phase-noise performances compared to a conventional differential VCO. The ISF analysis and small-signal analysis also show that the drawbacks of the current-weight-average phase-adjusting and voltage-weight-average phase-adjusting architectures are current-source noise effect and large additional capacitance, respectively. A voltage-average-adjusting circuit with a source follower at its input alleviates the capacitance increase.

A 33 MHz Fast-Locking PLL with Programmable VCO and Automatic Band Selection for Clock Generator Application

This paper presents a prototype of an auto-ranging phase-locked loop (PLL) with low jitter noise over a wide operating frequency range using the multiband programmable voltage-controlled oscillator (VCO) gain stage with automatic band selection. We successfully reduce the VCO gain (Kvco) and retain the desired frequency band. The proposed PLL comprises a prescaler, phase frequency detector (PFD), charge pump (CP), programmable VCO and automatic band selection circuit. The PLL prototype with all subblocks was implemented using the TSMC 0.18 μm 1P6M process. Contrary to conventional PLL architectures, the proposed architecture incorporates a real-time check and automatic band selection circuit in the secondary loop. A high-performance dual-loop PLL wide tuning range was realized using an ASIC digital control circuit. A suitable way to maintain the Kvco low is to use multiple discrete frequency bands to accommodate the required frequency range. To maintain a low Kvco and fast locking, the automatic frequency band selection circuit also has two indigenous, most probable voltage levels. The proposed architecture provides the flexibility of not only band hopping but also band twisting to obtain an optimized Kvco for the desired output range, with the minimum jitter and spurs. The proposed programmable VCO was designed using a voltage-to-current-converter circuit and current DAC followed by a four-stage differential ring oscillator with a cross-coupled pair. The VCO frequency output range is 150–400 MHz, while the input frequency is 25 MHz. A sequential phase detection loop with a negligible dead zone was designed to adjust fine phase errors between the reference and feedback clocks. All circuit blocks of the proposed PLL were simulated using the EDA tool HSPICE and layout generation by Laker. The simulation and measured results of the proposed PLL show high linearity, with a dead zone of less than 10 pV. The differential VCO was used to improve the linearity and phase noise of the PLL. The chip measured results show rms jitter of 19.10 ps. The PLL prototype also has an additional safety feature of a power down mode. The automatic band selection PLL has good immunity for possible frequency drifting due to temperature, process and supply voltage variations. The proposed PLL is designed for −40 to +85 °C, a wide temperature range.

Subharmonic single-balanced LMV with bottom LO injection

This paper proposes a subharmonic single-balanced RF receiver front-end (called LMV) where low noise amplifier is stacked on top of a differential voltage-controlled oscillator (VCO) to re-use the dc bias current. In this subharmonic (SH) LMV, the VCO itself plays the role of the single-balanced subharmonic mixer while generating an LO signal. This bottom LO SH LMV has good LO to IF and LO to RF leakage performances. Also, it can reduce the die size on a chip since it requires only one inductor for the VCO instead of two in the case of top LO LMV.Oscillating at around 2.4 GHz band, the proposed SH LMV is designed using a 65 nm CMOS technology and compared to the top LO SH LMV in terms of phase noise, conversion gain and double sideband noise figure. The SH LMVs consume about 160 μW dc power from a 1-V supply.

Low power CMOS differential ring VCO designs using dual delay stages in 0.13 ​μm technology for wireless applications

This manuscript postulates two new designs of dual-delay stage for the four-stage CMOS differential ring voltage controlled oscillators (VCOs). Ring VCOs designs use dual-delay path techniques to achieve a wide tuning range with low power dissipation. The proposed VCOs are designed in TSMC 0.13 ​μm CMOS technology with a power supply of 1.3 ​V. VCO-1 generates tuning ranges from 5.188 to 7.932 ​GHz (41.82%), whereas its power dissipation varies from 1.853 to 2.711 ​mW by the change in control voltage from −1.0 ​V to 0 ​V. VCO-2 based on I-MOS varactors produces a tuning range from 4.918 to 7.268 ​GHz (38.56%) and dissipates the power from 1.853 ​mW to 2.711 ​mW. VCO-1 and VCO-2 exhibits phase-noise of −102.2 dBc/Hz and −99.5 dBc/Hz at 1 ​MHz offset from 5.834 ​GHz to 5.482 ​GHz central frequency, respectively. The figure-of-merit (FoM) of VCO-1 and VCO-2 circuit is −173.9 dBc/Hz and −171.2 dBc/Hz. Proposed VCO-1 and VCO-2 acquire an area of 247.62 μm2 and 248.04 μm2, respectively.

A Differential Voltage-controlled Oscillator as a Single-balanced Mixer

This paper proposes a low power radio frequency receiver front-end where, in a single stage, singlebalanced mixer and voltage-controlled oscillator are stacked on top of low noise amplifier and re-use the dc current to reduce the power consumption. In the proposed topology, the voltage-controlled oscillator itself plays the dual role of oscillator and mixer by exploiting a series inductor-capacitor network. Using a 65 nm complementary metal oxide semiconductor technology, the proposed radio frequency front-end is designed and simulated. Oscillating at around 2.4 GHz frequency band, the voltage-controlled oscillator of the proposed radio frequency front-end achieves the phase noise of ‒72 dBc/Hz, ‒93 dBc/Hz, and ‒113 dBc/Hz at 10KHz, 100KHz, and 1 MHz offset frequency, respectively. The simulated voltage conversion gain is about 25 dB. The double-side band noise figure is ‒14.2 dB, ‒8.8 dB, and ‒7.3 dB at 100 KHz, 1 MHz and 10 MHz offset. The radio frequency front-end consumes only 96 μW dc power from a 1-V supply.

Constantly low‐phase‐noise differential VCO based on balanced tunable quasi‐elliptic and constant‐ABW BPF

AbstractIn this article, a parallel‐feedback differential voltage‐controlled oscillator (VCO) with constantly low‐phase noise and frequency tuning range (FTR) of 1.72–2.12 GHz (20.8%) is presented. The presented differential VCO with differential outputs and low‐phase noise is achieved using a four‐pole tunable balanced bandpass filter (BAL‐BPF) with quasi‐elliptic frequency response as a frequency stabilization element. The low‐phase noise is obtained and maintained because of the high in‐band group delay and the constant absolute bandwidth (CABW) of the used tunable BAL‐BPF. For demonstration, an example is designed, fabricated, and measured. The measured oscillation frequency of the differential VCO can be tuned from 1.72–2.12 GHz (20.8%) and the phase noises keep better than −99 dBc/Hz @100 kHz and − 129.1 dBc/Hz @1 MHz over the FTR. In the meantime, the differential oscillating signals are generated at two outputs.

Low power wide tuning range differential ring VCO designs with I-MOS and A-MOS varactor

This manuscript reports two new designs of dual delay cells based on inversion mode MOS (I-MOS) and accumulation mode MOS (A-MOS) varactor for low power and wide tuning range differential ring voltage controlled oscillator (VCO). The new designs obtained a large tuning range by varying the capacitance of the delay stages. The change in capacitance across I-MOS and A-MOS varactor are obtained by varying the gate control voltage (Vg). The proposed VCO circuits are simulated in 0.18 µm CMOS process with a supply voltage (Vdd) of 1.8 V. The tuning ranges of VCO-I (with I-MOS varactor) and VCO-II (based on A-MOS varactor) vary from 1.697–0.714 GHz (81.54%) and 2.019–0.874 GHz (79.15%), whereas their power consumption vary from 4.347–3.507 mW and 3.713–3.063 mW respectively, by modulation of control voltage (Vc) from 0 V to 1 V. The phase noise of ring VCO-I and VCO-II is −103.1 dBc/Hz and −101.2 dBc/Hz at 1 MHz offset from 1.270 GHz and 1.516 GHz central frequency respectively. The figure of merit (FoM) of the VCO-I and VCO-II is −158.92 dBc/Hz and −159.32 dBc/Hz respectively and acquires an area of 0.381 mm2.

Dual Band Switchable Voltage Controlled Oscillator in 65-nm CMOS Technology

A switchable differential voltage-controlled oscillator (VCO) has been fabricated in 65nm CMOS. It is a dual frequency VCO whose oscillation frequencies can be changed from 40GHz (VCO1) to 80GHz (VCO2). The tuning range for VCO1 is 1GHz and for VCO2 is 4GHz. The inductor switching is attained with the help of transistor as a switch and inductors are fabricated in a stacked manner for saving die area. The output power of VCO1 is 1 dBm and for VCO2 is 0dBm with a total power consumption of 42mW. The phase noises were -94.62 dBc/Hz and -81.43 dBc/Hz at 1MHz offset for VCO1 and VCO2 respectively. The chip area is 500 x 560 um2 including probing pads.

Dual Band Switchable Voltage Controlled Oscillator in 65-nm CMOS Technology

A switchable differential voltage-controlled oscillator (VCO) has been fabricated in 65nm CMOS. It is a dual oscillator whose oscillation frequencies can be changed from 40GHz (VCO1) to 80GHz (VCO2) with 1 to 4GHz tuning range for oscillator respectively. The inductor switching is attained with the help of transistor as a switch and inductors are fabricated in a stacked manner for saving die area. The output power of VCO1 is 1 dBm and for VCO2 it is 0dBm with a total power consumption of 42mW. The phase noises were -94.62 dBc/Hz and -81.43 dBc/Hz at 1MHz offset for VCO1 and VCO2 respectively. The chip area is 500 x 560 um 2 including probing pads.

Dual Band Switchable Voltage Controlled Oscillator in 65-nm CMOS Technology

A switchable differential voltage-controlled oscillator (VCO) has been fabricated in 65nm CMOS. It is a dual oscillator whose oscillation frequencies can be changed from 40GHz (VCO1) to 80GHz (VCO2) with 1 to 4GHz tuning range for oscillator respectively. The inductor switching is attained with the help of transistor as a switch and inductors are fabricated in a stacked manner for saving die area. The output power of VCO1 is 1 dBm and for VCO2 it is 0dBm with a total power consumption of 42mW. The phase noises were -94.62 dBc/Hz and -81.43 dBc/Hz at 1MHz offset for VCO1 and VCO2 respectively. The chip area is 500 x 560 um 2 including probing pads.

Utilization of Multi-Resonant Defected Ground Structure Resonators in the Oscillator Feedback for Phase Noise Reduction of K-Band VCOs in 0.18-$\mu$ m CMOS Technology

This work proposes a new theory to reduce the phase noise of K-band Voltage-Controlled Oscillators (VCOs) in Complementary Metal Oxide Semiconductor (CMOS) process by introducing one or more transmission poles around the parallel resonance of an LC-tank circuit. Introduction of transmission poles beside the parallel resonance of the LC-tank circuit sharpens the skirt characteristics of the Scattering ( $\vert \text{S}\vert$ ) parameters of the resonators. In return, sharp $\vert \text{S}\vert $ -parameters slope enhances the resonator loaded quality (Q) factor without compromising the unloaded Q-factor. In addition, the transmission pole can be realized near the second harmonic of the oscillation. This allocation of the transmission pole leads to the cancellation of this second harmonic and a further reduction of the phase noise. The proposed theory is verified by three different designs based on defected ground structure (DGS) resonators. These designs realized a low-band transmission pole before the parallel resonance, a high-band transmission pole after the parallel resonance, and dual-band transmission poles around the parallel resonance. First, each design is verified and compared to the others using circuit and electromagnetic simulations to establish the Q-factor improvement. Then, each of the resonators is utilized in a differential VCO topology and the phase noise reduction in post-layout simulations is confirmed. Finally, two chips are fabricated in 0.18- $\mu $ m CMOS technology and measured. The measurement results are in good agreement with the simulations, which confirm our claim about the proposed theory.

New low power differential VCO circuit designs with active load and IMOS varactor

In this paper, low power differential voltage-controlled oscillators (VCOs) have been reported utilizing the active load and inversion mode MOSFET (IMOS) varactor in the delay stages. VCO circuits operation is based on two NOR gates in differential mode, variations in gate control voltage of the NMOS/PMOS active load, and the varactor control voltage of IMOS. For VCO based on NMOS active load, variations in gate control voltage from 1.0 V to 2.0 V exhibit frequency variations from 6.687 GHz to 6.395 GHz. For VCO based on PMOS active load, variations in gate control voltage of PMOS active load from −0.5 V to 0.5 V provide frequency variations from 5.726 GHz to 6.142 GHz. For VCO based on IMOS varactor, variations in varactor control voltage of IMOS from 1.0 V to 2.0 V shows variations in output frequency from 3.796 GHz to 4.499 GHz with power dissipation of 2.06 mW. Proposed VCOs shows a phase noise of −76.20 dBc/Hz@1MHz for NMOS active load, −73.42 dBc/Hz@1MHz for PMOS active load and −75.63 dBc/Hz@1MHz for IMOS varactor load and the figure of merit (FoM) for the VCOs are −149.43 dBc/Hz, −145.58 dBc/Hz and −145.17 dBc/Hz, respectively.

Low power active load and IMOS varactor based VCO designs using differential delay stages in 0.18 ​μm technology

This paper proposes low power differential voltage-controlled oscillators (VCOs) with active load and IMOS varactor in delay stages. VCO circuits utilize two NOR gates in differential mode. The different levels of gate bias voltage (Vbias) of the PMOS/NMOS active load along with variations in the varactor control voltage (Vcontrol) of inversion mode MOSFET (IMOS) achieves a wide frequency tuning range. PMOS active load VCO shows the output frequency range from 4.656 ​GHz to 5.333 ​GHz and power dissipation of 2.539 ​mW. NMOS active load VCO shows the output frequency range from 4.782 ​GHz to 5.516 ​GHz and power dissipation of 2.225 ​mW. The results with different width of varactor diode and bias voltages of active load are also reported in this work. Proposed VCO circuits are showing a phase noise of −102.37 dBc/Hz for PMOS active load, and −98.63 dBc/Hz for NMOS active load at 1 ​MHz offset with the corresponding figure of merit (FoM) of −172.86 dBc and −168.41 dBc, respectively.

A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.

Low Power, Ring VCO with Pre-Charge and Pre-Discharge Circuit for 4 GHz–6.1 GHz Applications in 0.18 μm CMOS

The differential ring voltage controlled oscillator (VCO) is one of the critical devices in wireless communication system having excellent stability, controllability and noise rejection ability. A novel design of delay cell is proposed for the four staged CMOS differential ring VCO with high output frequency, low power consumption and low phase noise. The differential ring VCO utilizes multiloop dual delay path topology to acquire both high output frequency and low phase noise. Results have been achieved in TSMC 0.18-[Formula: see text]m CMOS process with a supply voltage ([Formula: see text]) 1.8[Formula: see text]V. The proposed design achieves an output frequency range of 4.029[Formula: see text]GHz to 6.122[Formula: see text]GHz and power of 4.475[Formula: see text]mW is consumed with control voltage variation from 1[Formula: see text]V to 2[Formula: see text]V. The proposed VCO exhibits [Formula: see text]89.7[Formula: see text]dBc/Hz phase noise at 1[Formula: see text]MHz offset frequency and the corresponding figure of merit (FoM) is [Formula: see text]155.9[Formula: see text]dBc/Hz. The design of differential ring VCO with novel delay stage has improved performance in terms of power consumption, output oscillation frequency and phase noise.

An energy-efficient multi-level RF-interconnect for global network-on-chip communication

A simultaneous and reconfigurable multi-level RF-interconnect (MRI) for global network-on-chip (NoC) communication is demonstrated. The proposed MRI interface consists of baseband (BB) and RF band transceivers. The BB transceiver uses multi-level signaling (MLS) to enhance communication bandwidth. The RF-band transceiver utilizes amplitude-shift keying (ASK) modulation to support simultaneous communication on a shared single-ended on-chip global interconnect. A phase-locked loop (PLL) using a sub-harmonic multiply-by-10 injection-locked frequency multiplier is also designed to support a fully-synchronous NoC architecture. A differential voltage-controlled oscillator (VCO) used in a PLL creates an output frequency for a frequency range between 0.5 and 2.65 GHz signal. The multiply-by-10 ILFM generates 10 times higher frequency than the VCO output signal. Using the proposed multiply-by-10 ILFM can minimize the number of power-hungry frequency divider stages in a PLL feedback loop, resulting in improvement of the MRI power efficiency. The MLS-based BB and ASK-based RF band carry 10 Gb/s/pin and 4.4 Gb/s/pin, respectively. The proposed system is fabricated in a 65 nm CMOS process and achieves an energy efficiency of 2 pJ/b.

A 2.3-mW 26.3-GHz $G_{m}$ -Boosted Differential Colpitts VCO With 20% Tuning Range in 65-nm CMOS

This paper presents an architecture for differential Colpitts voltage-controlled oscillators (VCOs) in complementary metal–oxide–semiconductor (CMOS) that utilizes three design techniques to extend the tuning range (TR) of the VCO, while maintaining a low phase noise (PN) and a low power consumption. First, a switched-capacitor bank based on a variable capacitive feedback technique is introduced to achieve a wide TR with a minimal PN degradation. Second, a $G_{m}$ -boosting technique using interstage inductors is employed to lower the power consumption and relax VCO startup issues. Third, a dynamic forward-body self-biased technique is used to further reduce the power consumption and PN of the proposed structure. As a proof of concept, a 26.3-GHz differential Colpitts VCO is designed and fabricated in a 65-nm CMOS process. Based on the measurement results, the VCO achieves a PN of −122.1 dBc/Hz at 10-MHz offset from the center frequency, and a TR of 20%. The circuit consumes 2.3 mW from a 1-V supply and excluding the pads occupies a 0.22 mm2 of silicon area. Compared to the recently published CMOS VCOs within the same frequency range, the proposed VCO simultaneously achieves a wide TR, low power dissipation, and low PN, resulting in a figure of merit (FOM) and FOM incorporating the TR (FOM $_{T}$ ) of −187 and −193 dBc/Hz at 10-MHz offset from the center frequency, respectively.

A 1-GS/s 20 MHz-BW Capacitive-Input Continuous-Time $\Delta\Sigma$ ADC Using a Novel Parasitic Pole-Mitigated Fully Differential VCO

This letter presents a high-speed closed-loop capacitive-input voltage controlled oscillators (VCO)-based continuous-time delta sigma modulator (CTDSM) using a novel fully differential VCO topology whose parasitic pole is inherently located at a very high frequency, regardless of the number of inverters in the ring VCO. The mitigation of the parasitic pole is achieved by splitting the VCO’s input transconductor into a set of distributed input transistors. Capacitive input and capacitive DAC result in a very low thermal noise front end, besides ensuring that there is no additional pole caused due to the VCO’s input capacitance. A single pair of pseudo-resistors is used for providing dc negative feedback in the CTDSM. The prototype first-order 63-stage VCO-based CTDSM is fabricated in 40-nm CMOS and occupies a core area of 0.02 mm2 while achieving 63.1-dB dynamic range in 480 kHz–20.48 MHz bandwidth at 1 GS/s. This is the first work to mitigate the parasitic pole in a fully differential VCO, without relying on any additional active circuits. To the authors’ best knowledge, this is also the first work to demonstrate the capacitive input in a high-speed CTDSM, without using chopping.