Differential Pass-transistor Logic Research Articles

Exploration of logic gates and multiplexer using doping-free bipolar junction transistor

Logic gates are designed using symmetric lateral doping-free bipolar junction transistor (BJT) on silicon on insulator (SOI) using differential pass transistor logic, and their performance matrices are presented. Charge carriers are induced in lightly doped emitter and collector regions using two unique approaches. i.e., the charge plasma (CP) and polarity control (PC). AND, OR and XOR gates are designed using four types of devices (CP-NPN, CP-PNP, PC-NPN, and PC-PNP) and transient and noise margin analysis are performed. The transient response shows rise and fall time less than 100 ps while worst-case noise margin of 0.25 V observed for an input voltage of 1 V. Moreover, 2:1 multiplexer is also designed and explored for output transient and voltage levels. The delay of less than 2.2 ns is achieved with a nominal deviation of 0.1 V and 0.04 V for high and low output levels respectively.

Differential pass-transistor logic

Differential pass-transistor logic (DPTL), which offers the noise immunity needed to use the unique switching properties of FETs in realizing switching network efficiencies, is discussed. CMOS DPTL offers significant power-delay product advantages over conventional CMOS logic for both 5-V and 3-V power supplies. These features are achieved by DPTL's fewer and smaller parasitic capacitances, which are the result of significantly lower device counts combined with emphasized usage of minimum-size, n-channel pass-transistors. Substantial benefits are also obtained by using DPTL with depletion and enhancement/depletion GaAs MESFET technologies. Experiments show that GaAs DPTL offers substantial power-delay-product reductions over conventional GaAs realizations. Compared to CMOS DPTL, GaAs DPTL consumes less power at very high frequencies, a consequence of the electronic properties of GaAs and the smaller signal swings used in emitter/drain (E/D) DPTL.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

DPTL 4-b carry lookahead adder

Implementation of a 4-b carry lookahead adder using D-MESFETs, in 1- mu m non-self-aligned gate GaAs technology, is presented. A novel technique to improve the circuit performance using differential pass transistor logic (DPTL) is presented. Circuit structures are presented and are compared with buffered FET logic (BFL). Experimental results are provided to verify the functionality and performance of the DPTL adder. The adder occupies an area of 0.890*0.652 mm/sup 2/ (excluding the output pads) and can add up to 1 Gwords/s dissipating 242 mW of power (excluding the output drivers). >

Design of submicrometer CMOS differential pass-transistor logic circuits

The interaction between the architectural features of CMOS differential pass-transistor logic (DPTL) and the submicron process technology used to implement it are examined. Techniques that exploit the noise immunity associated with the DPTL architecture are presented to effectively enable signal-swing reductions that result in increased speed. The extent to which DPTL can benefit from this signal-swing/speed tradeoff is examined by investigating the impact of device scaling on DPTL operation. A novel DPTL buffer that enables the implementation of a single-phase clocking scheme and the exchange of signal swing for increased circuit speed is proposed. Experimental results are provided.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

GaAs MESFET differential pass-transistor logic

Two GaAs MESFET implementations of differential pass-transistor logic (DPTL) are presented. The DPTL logic technique combines the area efficiencies and high operation speeds of ratioless pass-transistor circuits with the additional features of noise immunity and low power dissipation. Circuit structures are presented for both depletion (D)-mode and enhancement/depletion (E/D)-mode MESFET technologies, and are compared with buffered FET logic (BFL) and direct-coupled FET logic (DCFL), respectively. Experimental results are provided to verify the functionality and the performance features of both DPTL forms.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

GaAs MESFET differential pass-transistor logic

A GaAs MESFET implementation of differential pass-transistor logic (DPTL) is presented. This logic technique combines the greater area efficiencies and high operation speeds of ratioless, pass-transistor circuits with the additional advantages of good noise immunity and low power dissipation. Experimental results are provided for a four-bit counter implemented in a 1 =m, depletion (D)-mode MESFET technology to demonstrate both the functionality and noise immunity of GaAs DPTL.

CMOS differential pass-transistor logic design

This logic technique offers greater area efficiency, higher speeds of operation, and simpler design algorithms than conventional CMOS pass-transistor logic. Experimental results and the automated techniques used in implementing efficient pass-transistor layouts are presented. The application of CMOS differential pass-transistor logic design in custom applications is also discussed.

Differential pass transistor logic in CMOS technology

Differential pass transistor logic is described in the letter. This configuration results in better silicon area efficiency and higher speed of operation than conventional CMOS pass transistor logic.