Differential Operational Transconductance Amplifier Research Articles

0.5 V Multiple-Input Fully Differential Operational Transconductance Amplifier and Its Application to a Fifth-Order Chebyshev Low-Pass Filter for Bio-Signal Processing.

This paper presents a multiple-input fully differential operational transconductance amplifier (MI-FD OTA) with very low power consumption. To obtain a differential MOS pair with minimum supply voltage and minimum power consumption, the multiple-input bulk-driven MOS transistor operating in the subthreshold region is used. To show the advantage of the MI-FD OTA, a fifth-order Chebyshev filter was used to realize a low-pass filter capable of operating with a supply voltage of 0.5 V and consuming 60 nW at a nominal setup current of 3 nA. The proposed filter uses five MI-FD OTAs and five capacitors. The total harmonic distortion (THD) was 0.97% for a rail-to-rail sinusoidal input signal. The MI-FD OTA and the filter application were designed and simulated in the Cadence environment using a 0.18 µm CMOS process from TSMC. The robustness of the design was confirmed by Monte Carlo analysis and process, voltage, and temperature corner analysis.

A 0.8 V, 14.76 nVrms, Multiplexer-Based AFE for Wearable Devices Using 45 nm CMOS Techniques.

Wearable medical devices (WMDs) that continuously monitor health conditions enable people to stay healthy in everyday situations. A wristband is a monitoring format that can measure bioelectric signals. The main part of a wearable device is its analog front end (AFE). Wearables have issues such as low reliability, high power consumption, and large size. A conventional AFE device uses more analog-to-digital converters, amplifiers, and filters for individual electrodes. Our proposed MUX-based AFE design requires fewer components than a conventional AFE device, reducing power consumption and area. It includes a single-ended differential feedback operational transconductance amplifier (OTA) and n-pass MUX-based AFE circuits which are related to the emergence of low power, low area, and low cost AFE-integrated chips that are required for wearable biomedical applications. The proposed 6T n-pass multiplexer measures a gain of -68 dB across a frequency range of 100 kHz with a 136.5 nW power consumption and a delay of 0.07 ns. The design layout area is approximately 9.8 µm2 and uses 45 nm complementary metal oxide semiconductor (CMOS) technology. Additionally, the proposed single-ended differential OTA has an obtained input referred noise of 0.014 µVrms, and a gain of -5.5 dB, while the design layout area is about 2 µm2 and was designed with the help of the Cadence Virtuoso layout design tool.

Hybrid Inverter-Based Fully Differential Operational Transconductance Amplifiers

Inverter-based Operational Transconductance Amplifiers (OTAs) are versatile and friendly scalable analog circuit blocks. Especially for the new CMOS technological nodes, several recent applications have been extensively using them, ranging from Analog Front End (AFE) to analog-to-digital converters (ADC). This work tracks down the current advances in inverter-based OTAs design, comparing their basic fully differential structures, such as Nauta (N), Barthelemy (B), Vieru (V) and Mafredini (M) ones, and, in addition, mixing them up to propose new fully differential single-ended and two-stage hybrid versions. The new herein-proposed fully differential hybrid OTAs are the composition of Barthelemy/Nauta (B/N), Barthelemy/Manfredini (B/M), Nauta/Vieru (N/V), and Manfredini/Vieru (M/V) OTAs. All OTAs were designed using the same Global Foundries 180 nm open-source PDK and their performances are compared for post-layout simulations.

Low voltage fully differential OTA using DTMOS based self cascode transistor with slew-rate enhancement and its filter application

In this work, low-voltage high-performance, fully differential current mirror Operational Transconductance Amplifiers (OTAs) are designed using DTMOS and asymmetric threshold voltage self cascode structure. Additionally cross drain coupled positive feedback and auxiliary slew-rate enhancement (SRE) technique are employed to improve the gain and slew-rate of proposed circuits. The proposed-I OTA (OTA-1) utilizes the dynamic threshold metal oxide semiconductor (DTMOS) technique which operates at low supply voltage and provides enhanced performance. However, the asymmetric threshold voltage self cascode structure used in proposed-II OTA (OTA-2) further improves the gain and other parameters. The proposed OTAs operate at ± 0.4 V dual power supply. The open-loop gain for the OTA-1 and OTA-2 is obtained as 73 dB and 82 dB with 10.04 μW and 10.77 μW power consumption, respectively. It offers enhanced slew-rate and improved GBW than the conventional OTA. Moreover, it gives high CMRR as 216 dB and 250 dB for the OTA-1 and OTA-2 respectively. The universal biquad voltage-mode filter has been realized using proposed OTAs. All simulations are performed using Mentor Graphics Eldo simulation tool with TSMC 0.18 μm process parameters. To validate the robustness of proposed OTAs, Monte Carlo analysis and corner analysis have been performed.

Improved loop stability approach in fully differential operational transconductance amplifier with common‐mode feedback circuit

AbstractThis paper proposes a new approach to improve loop stability in a typical common‐mode feedback (CMFB) circuit of a differential operational transconductance amplifier (OTA). In this paper, a differential difference amplifier (DDA) with a current mirror load is employed as a CMFB circuit. The new approach is based on using two series diode‐connected transistors operating in subthreshold region in parallel with current mirror load. The proposed approach provides a reliable good function with no reduction in the OTA performance and dynamic operation of CMFB loop. The proposed scheme attains necessary high gain and large bandwidth with required phase margin for CMFB circuit. The proposed CMFB circuit is employed in a typical OTA structure. The post‐layout simulation results in TSMC 130‐nm CMOS technology show that the proposed approach leads to a better phase margin of 80°, a high unity gain bandwidth of 800 MHz, and a loop gain of 27 dB for the CMFB circuit.

Positive-Feedback-Based Design Technique for Inherently Stable Active Load Toward High-Gain Amplifiers With Unipolar a-IGZO TFT Devices

This letter presents analysis of an inherently stable positive-feedback-based active load, first reported in our prior work, to realize high gain analog amplifiers using unipolar a-IGZO TFT technology. Additionally reported are theoretical performance bounds and design guidelines to maximally utilize a general positive-feedback scheme for the active load while maintaining stability. To demonstrate a design implementation, a single stage fully differential operational transconductance amplifier with common mode feedback has been manufactured and measured to have 40-dB open-loop gain at dc and a unity gain frequency of 61 kHz while driving a 30-pF load capacitance.

Active Charge Balancer With Adaptive 3.3 V to 38 V Supply Compliance for Neural Stimulators

Charge balancing has become a common key safety requirement of electrical stimulation systems. It reduces the risk of electrode dissolution and tissue damage, which might arise after unbalanced stimulation pulses. A CMOS integrated consequence-based active charge balancer is presented that instantaneously removes excess charges between two consecutive stimulation pulses. This balancer provides a highly adaptive power supply compliance from 3.3 V to 38 V, verified by measurements. In order to maintain the compensation behavior and efficacy over the entire supply range and to protect the active components at such high voltages, a quad-rail design is elaborated that overcomes the technological high voltage limitations of the employed 0.35 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process. The presented charge balancing circuit consists of a fully differential operational transconductance amplifier for monitoring and voltage level translation, as well as an advanced class-B stage as current driver, designed in accordance with the quad-rail concept. Further system flexibility is provided by incorporating three different compensation current limitations of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm 500~\mu \text{A}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm 300~\mu \text{A}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm 200~\mu \text{A}$ </tex-math></inline-formula> . Additionally, two safety limits of ±50 mV and ±100 mV have been adopted. The charge balancer is very power efficient, it only dissipates 6.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> and 25 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> , at 3.3 V and 38 V respectively.

A 59 pA/V and 62 nW Differential OTA with 0.35% THD for Biomedical Applications

This paper presents a novel differential pA/V Operational Transconductance Amplifier (OTA) topology. The circuit is suitable for the implementation of fully integrated operational transconductance amplifier-capacitance (OTA-C) filters with small feature size capacitors, suited for electrophysiological signal acquisition and conditioning. Unlike typical OTA-Cs, the proposed topology consists of transconductance reduction technique based on unbalanced output branches thatallow current subtraction thus enabling transconductances in the order of pA/V. The technique is demonstrated through the design of a 59pA/V transconductor, which is very suited for designing long-time-constant filters. This OTA-C achieved a worst-case 0.35% THD with just 61.7nW average power consumption, which allows its applicability to biomedical implants. Simulations were carried out with STMicroelectronics 0.13µm HCMOS9 node using Cadence’s IC design tools. Weemployed the OTA in a design of a fourth-order bandpass filter with a narrow bandwidth of 12.5–21.8Hz. Similar results to the ideal transfer function, turn the proposed OTA ideal for biosensing-based applications.

Design and simulation of fourth order low-pass Gm-C filter with novel auto-tuning circuit in 90 nm CMOS

A tunable high-frequency operational transconductance amplifier (OTA) is presented along with its application in the implementation of a Gm-C filter. The OTA is tuned by varying the negative resistance produced by a positive feedback at the output. Post-layout simulation results (using TSMC 90 nm CMOS technology and a 1-V supply voltage) show that the differential DC gain, common-mode gain and OTA unity gain frequency are 34 dB, −26 dB and 10 GHz, respectively. Moreover, for precise control of filter performance, an auto-tuning circuit is presented to adjust the filter cutoff frequency at low power consumption (i.e., 0.6 mW, about 16.3% of the total circuit power consumption). The filter has a cutoff frequency of 1 GHz with a group delay variation less than 6% up to 1.3 fc. The size of filter is 0.040 × 0.023mm2 and the third order intermodulation (IM3) value at cutoff frequency is −37 dB. The Monte Carlo simulation results are presented for predicting the manufacturing process errors.

An evolutionary-based design methodology for performance enhancement of a folded-cascode OTA using symbiotic organisms search algorithm and gm/ID technique

In this paper, a new population-based evolutionary technique namely symbiotic organisms search (SOS) optimisation algorithm is proposed to optimize the design variables of transistors used in analog circuit. Here length and width of the transistors are considered to be the design variables, the optimisation of which minimizes the input-referred noise, total MOSFET area, and power consumption. This algorithm is quite useful in solving optimization problems but it suffers from higher computational time. Thus in order to minimize the computational time along with SOS algorithm, gm/ID design methodology is used. The proposed method not only guarantees appropriate bias conditions but also estimates the reduced search spaces for the design variables of the MOSFETs. To analyse the performance of SOS algorithm along with gm/ID design methodology, a low noise differential folded-cascode operational transconductance amplifier has been designed and verified using Cadence Spectre circuit simulator in UMC 0.18 µm CMOS process and MATLAB. From the optimisation results, it is observed that the gm/ID method combined with SOS algorithm converges earlier than SOS alone. The total computational time of simulation obtained using the proposed method is 8.59 s while errors found are less than 8%. Hence, this method not only reduces computational time but also improves the accuracy of the circuit design.

A new low-voltage operational transconductance amplifier with push-pull CMFB scheme for low-pass filter applications

This paper proposes a new common-mode feedback (CMFB) scheme for a fully differential operational transconductance amplifier (OTA) with enhanced linearity and large voltage swing. The main feature is that the common-mode feedback circuit output with push-pull scheme, which is parallel to the high-side PMOS and low-side NMOS of the output stage, to stabilize the common-mode state quickly and to maximize the output voltage swing. In addition, the third-order Butterworth low-pass transconductance–capacitance filter based on linear transformation techniques is also implemented in the TSMC 0.18 µm 1P6M CMOS process. The power dissipation of the designed transconductance cell is only 161 μW and the average power consumption of this chip is 1.4 mW under 1.2 V supply voltage. The filter core occupies a silicon area of 0.044 mm2.

A Complementary Recycling Operational Transconductance Amplifier with Data-Driven Enhancement of Transconductance

An improved operational transconductance amplifier (OTA) is presented in this work. The fully differential OTA adopts the current recycling technique and complementary NMOS and PMOS input branches to enhance the total transconductance. Moreover, in order to achieve higher current efficiency, a data-driven biasing circuit was developed to dynamically adjust the power consumption of the amplifier. Two comparators were added to detect the voltage difference at the input nodes, and when the differential input is large enough to activate either comparator, extra biasing current is activated and poured into the amplifier to enhance its slew rate and gain-bandwidth product (GBW). The threshold voltage of the complementary recycling folded cascode (CRFC)-based comparator is configured to suppress overshoot. Complementary common-mode feedback (CMFB) topology with local CMFB structure is built to acquire high common-mode gain. The OTA was fabricated in SMIC 0.18- μ m CMOS technology. The experimental result based on a capacitive feedback loop shows that the data-driven operation improves the average slew rate of the amplifier from 10.2 V/ μ s to 55.5 V/ μ s while the power only increases by 150%. The OTA has good potential to satisfy the fast settling demands for capacitive sensing circuits.

A 0.25-V fifth-order Butterworth low-pass filter based on fully differential difference transconductance amplifier architecture

This paper presents a fifth-order Butterworth low-pass filter based on the fully differential difference transconductance amplifier (FDDTA) building blocks. At first, the FDDTA has been stated and its operation has been evaluated. Then, a practical implementation using two fully differential inverter-based operational transconductance amplifiers (OTA) was investigated. This particular FDDTA implementation relies on two main features: the intrinsically matched transistors that assure similar transconductances and output conductances for both inverter-based OTA instances; and the inverter-based approach without internal nodes that reduces circuit complexity and power consumption since it requires no supplementary external calibration circuit such as tail current or bias voltage sources. Finally, the filter architecture, which consists of one inverter-based OTA input stage and five FDDTAs in a cascade connection has been evaluated, showing that it presents the expected fifth-order transfer function according to the Butterworth theory. The prototypes, implemented in a 130 nm CMOS process, operate in weak inversion supplied with 0.25 V and consumes 603 nW. Furthermore, they feature a DR of 57 dB in a 100 Hz bandwidth and a maximum THD of 54 dB, therefore, accomplishing specifications that suit for low-frequency applications.

Ultra-low power two-stage class-AB recycling double folded cascode OTA

This paper presents an ultra-low power two-stage class-AB recycling double folded cascode (RDFC) fully differential operational transconductance amplifier (OTA) with high DC gain, unity gain frequency, slew rate, and common-mode rejection ratio (CMRR). Design and simulation of the proposed OTA is done in a 0.18-μm standard CMOS technology with a 1 V supply voltage. In this design, all transistors operate in weak inversion. A new RDFC structure with two separate paths to increase the gain and reduce the power consumption is used in the first stage of the proposed OTA. In the second stage, a class-AB amplifier is employed to improve the CMRR, DC gain and slew rate. Also, an output current control unit is included in the first stage to reduce power consumption. The use of the same proper bias circuit for the output current control unit and Miller resistor transistors establishes robust design against the process, voltage, and temperature (PVT) variations and reduces the power consumption. Post-layout simulation results of the proposed OTA demonstrate that it has a good performance over the previous state of the arts with DC gain of 136.8 dB, power consumption of 205.8 nW, and unity gain frequency of 141.7 kHz for a capacitive load of 2 × 7.5 pF.

A Topology of Fully Differential Class-AB Symmetrical OTA With Improved CMRR

An improvement of a standard fully differential class-AB symmetrical operational transconductance amplifier (OTA) topology is proposed in this brief to enhance the common-mode behavior. Common-mode behavior could be critical in fully differential class-AB OTAs, where the total current is not fixed and differential to common-mode conversion could therefore be present. A signal proportional to the input common-mode component is generated through a simple low-current auxiliary amplifier and used to modulate a bias voltage, achieving cancellation of the output common-mode component. Simulations in 40-nm CMOS technology show a net improvement of common-mode rejection ratio without affecting differential-mode behavior; the increase in area and power consumption is minimal, with a tradeoff between power and settling time. Simulations of a sample-and-hold exploiting the proposed OTA are presented.

CMOS ECCCII with Linear Tune of Rx and Its Application to Current-mode Multiplier

In this paper present CMOS second-generation current-controlled-current-conveyor based on differential pair operational transconductance amplifier. Its parasitic resistance at x-port can be linearly controlled by an input bias current. Therefore, a proposed building block is called electronically tunable second-generation current-controlled-current-conveyor (ECCCII). The application presents 2-quadrant and 4-quadrant current-mode signal multiplier circuits. Characteristics of the proposed ECCCII and its application are simulated by the PSPICE program and they are in agreement with the theory.

A wide tuning range Gm-C complex filter with master-slave automatic frequency tuning based switched-capacitor

A wide tunable Gm-C complex filter with programmable operational transconductance amplifier (OTA) is presented in this paper. With automatic tuning of the master-slave stage, the filter's time constant C∕Gm is set to a fixed value. Programmable OTA prevails wider tunable range. To achieve high linearity, an optimized differential OTA structure based on second-generation current conveyors (CCIIs) is employed for achieving wider tuning range in the complex filter. And the linearity of the filter suffers less from the master frequency tuning circuit because of no modification in the inner V-I conversion core during the tuning course. Benefited from the virtual ground created by the amplifier in switched-capacitor circuit, higher tuning accuracy is obtained. The prototype of the filter was fabricated in SMIC 0.18-μm CMOS process. Measurement results show that the tunable center frequency ranges from 147 kHz to 1.95 MHz and the tunable bandwidth ranges from 94 kHz to 1.96 MHz. Meanwhile, the filter achieves an in-band IIP3 above 18.2 dBm.

Power Efficient Fully Differential Bulk Driven OTA for Portable Biomedical Application

This paper presents a power efficient, bulk driven, source degenerated fully differential operational transconductance amplifier (OTA), operating in the subthreshold region. The input part of the OTA consists of a bulk driven source degenerated differential pair and cross coupled transistors to improve the linearity of OTA. It consists of a bulk driven pair to reduce the supply voltage and to improve the linearity. The proposed fully differential OTA has utilized self-cascode current mirror loads which increases the output impedance and hence the overall intrinsic gain. A subthreshold region is adopted to reduce the power consumption of the circuit. For a 200 mVpp sinusoidal input at 100 Hz, a total harmonic distortion (THD) of −58.56 dB is achieved. The gain, gain bandwidth (GBW), phase margin (PM) and gain margin (GM) values obtained were 48.4 dB, 3.1 KHz, 80° and 19.01 dB, respectively. The common mode rejection ratio (CMRR), power supply rejection ratio (PSRR) and slew rate +/− values were 146.3 dB, 83 dB and 99.56/100 V/ms, respectively. The circuit is capable of operating under a supply voltage of 0.8 V with a power consumption of 59.04 nW, which proves that the circuit is suitable for portable biomedical devices. The proposed circuit is simulated in CADENCE environment virtuoso using LFoundry 150 nm Complementary metal oxide semiconductor (CMOS) process technology.

On the design of highly linear CMOS digitally programmable operational transconductance amplifiers for low and high-frequency applications

This paper proposes a novel highly linear digitally programmable fully differential operational transconductance amplifier (DPOTA) circuit. Two versions of the proposed DPOTA structure are designed. The first version is optimized for high-frequency operation with current division networks designated to 3-bit control code words. On the other hand, the second version is optimized for low-frequency operation with 4-bit control code words. The third-order harmonic distortion (HD3) of the first DPOTA version remains below − 66 dB up to 0.4 V differential input voltage at 10 MHz frequency. The second DPOTA version achieved HD3 of − 70 dB with an amplitude of 20 mVp–p and at 100 Hz frequency. The proposed circuits are designed and simulated in 90 nm CMOS model, BSIM4 (level 54) under a balanced 1.2 V supply voltage.

A Differential Output Interfacing ASIC for Integrated Capacitive Sensors

In this paper, we have proposed an input interfacing scheme with differential output for integrated capacitive sensor applications. In the proposed scheme, the front-end interfacing is based on switched capacitor charge amplifier configuration using a fully differential operational transconductance amplifier and one differential capacitive sensor arrangement which provides differential output with minimum number of circuit components. In the back end, a sigma–delta ( $\Sigma \Delta $ ) modulator is integrated for modulated digital output. The signal conditioning circuit also includes gain programmability by selecting proper feedback capacitor and mismatch cancellation between the sensing capacitors through on-chip capacitors array. The complete application specific integrated circuit (ASIC) is designed and fabricated in United Microelectronics Corporation (UMC) $0.18-\mu \text{m}$ CMOS process technology. The fabricated ASIC is then integrated with a silicon-on-insulator microelectromechnical systems capacitive accelerometer to test and characterize the performance of the proposed scheme. The measured result shows that the sensitivity of the proposed circuit can be varied from 200 to 900 mV/g by changing the feedback capacitor. The integrated system is also tested with electrostatic actuation as well as with a vibrating shaker and the measurement results are presented.