Die Size Increase Research Articles

Enhancing FPGAs with Magnetic Tunnel Junction-Based Block RAMs

While plentiful on-chip memory is necessary for many designs to fully utilize an FPGA’s computational capacity, SRAM scaling is becoming more difficult because of increasing device variation. An alternative is to build FPGA block RAM (BRAM) from magnetic tunnel junctions (MTJ), as this emerging embedded memory has a small cell size, low energy usage, and good scalability. We conduct a detailed comparison study of SRAM and MTJ BRAMs that includes cell designs that are robust with device variation, transistor-level design and optimization of all the required BRAM-specific circuits, and variation-aware simulation at the 22nm node. At a 256Kb block size, MTJ-BRAM is 3.06× denser and 55% more energy efficient and its F max is 274MHz, which is adequate for most FPGA system clock domains. We also detail further enhancements that allow these 256 Kb MTJ BRAMs to operate at a higher speed of 353MHz for the streaming FIFOs, which are very common in FPGA designs and describe how the non-volatility of MTJ BRAM enables novel on-chip configuration and power-down modes. For a RAM architecture similar to the latest commercial FPGAs, MTJ-BRAMs could expand FPGA memory capacity by 2.95× with no die size increase.

Use of Wafer Applied Underfill for 3D Stacking

A key element for improving 3D IC stacking and packaging reliability is the choice of the right underfill (UF) material. The underfill is a specialized adhesive whose main purpose is locking together the top and bottom dice; it must fill the gap between bumps and between dice, while reducing the differential movement that would occur during thermal cycling. Traditional underfill processes are based on local dispensing after solder bump reflow (i.e., capillary dispensing), or before flip chip operation with no need of reflow (no flow underfill, NUF). In case of 3D stacking, such processes present some limitations: the need for a dispensing area (die size increase); material flow (spacing between dice), and cost (low throughput). After an introduction on typical underfill applications such as die-to-package and die-to-die assembly, we report the work done to assess the properties of several wafer applied underfill (WAUF) materials and their integration in 3D stacking. These materials were initially applied on silicon wafers in order to assess the minimum achievable thickness and material uniformity. The wafers were coated with different methods: spin coating and film lamination. After this initial assessment, the most promising materials were used for 3D stacking. The test vehicle used has Cu/Sn microbumps with a pitch of 40 μm. The quality of the materials is judged by electrical test, SAM (surface acoustic microscope), and X-SEM (scanning electron microscope).

Use of Wafer Applied Underfill for 3D Stacking

A key element for improving 3D stacking reliability is the choice of the right Underfill materials. The Underfill is a specialized adhesive that has the main purposes of locking top and bottom dies; it must fill the gap between bumps and between dies, while reducing the differential movement that would occur during thermal cycling. Traditional underfill processes are based on local dispensing after solder bump reflow (Capillary dispensing), or before flip chip operation with no need of reflow (No Flow Underfill, NUF). In case of 3D stacking, such processes present some limitations: need of a dispensing area (die size increase); material flowing (spacing between dies) and cost (low throughput). After an introduction on typical underfill applications like die-to-package and die-die assembly, we report the work done to assess the properties of several Wafer Applied Underfill (WAUF) materials and their integration in 3D stacking. These materials have been initially applied on silicon wafers in order to assess the minimum achievable thickness and the material uniformity. The wafers have been coated by using different methods: spin coating and film lamination. After this initial assessment, the most promising materials have been used for 3D stacking. The test vehicle used has Cu/Sn μbumps with a pitch of 40μm. The quality of the materials is judged by electrical test, SAM (Surface Acoustic Microscope) and X-SEM (Scanning Electron Microscope).