Device Mismatch Research Articles

All-Analytic Statistical Modeling of Constellations in (Optical) Transmission Systems Driven by High-Speed Electronic Digital to Analog Converters Part I: DAC Mismatch Statistics, Metrics, Symmetries, Error Vector Magnitude

This two-part work develops a comprehensive toolbox for the statistical characterization of nonlinear distortions of DAC-generated signal constellations to be transmitted over communication links, be they electronic (wireline, wireless) or photonic, Mach–Zehnder modulator (MZM)-based optical interconnects in particular. The all-analytic toolbox developed here delivers closed-form expressions for the second-order statistics (means, variances) of all relevant constellation metrics of the DACs’ building blocks and of DAC-driven MZM-based optical transmitters, all the way to the slicer in the optical receivers over a linear channel with coherent detection. The key impairment targeted by the model is the random current mismatch of the ASIC devices implementing the DAC drivers. In particular the (skew-)centrosymmetry of the DAC metrics is formally derived and explored. A key applicative insight is that the conventional INL/DNL (Integral NonLinearity/Differential NonLinearity) constellation metrics, widely adopted in the electronic devices and circuits community, are not quite useful in the context of communication systems, since these metrics are ill-suited to predict communication link statistical performance. To rectify this deficiency of existing electronic DAC metrics, we introduce modified variants of the INL|DNL, namely the integral error vector (IEV) and the differential error vector (DEV) constellation metrics. The new IEV|DEV represent straightforward predictors of relevant communication-minded metrics: error vector magnitude (EVM) treated here in Part I, and Symbol/Bit Error-Rates (SER, BER) treated in the upcoming Part II of this paper.

An offset calibration scheme for on-chip thermal profiling with differential temperature sensors

This paper introduces an on-chip analog calibration method tailored for differential temperature sensors in thermal monitoring applications. A three-step calibration process is proposed within a two-stage high-gain instrumentation amplifier to compensate for the output voltage offset due to device mismatches and on-chip temperature gradients. The calibration circuits were designed in a standard 65 nm CMOS process for simulation. Results indicate that an input-referred offset with a mean of 0.2 μV can be achieved after calibration, through which the standard deviation is greatly reduced from σ = 880.3 to σ = 5086 μV. Furthermore, the proposed analog offset calibration scheme has negligible impact on the sensitivity of the complete temperature sensor circuit, as shown by Monte Carlo and process-temperature corner simulation results.

A 2.41 ppm/°C bandgap voltage reference with second‐order curvature compensation

SummaryA current‐mode (CM) bandgap voltage reference (BGR) with second‐order curvature compensation is presented in this paper. The proposed CM BGR offers a simple compensation structure that requires only six additional transistors compared with traditional BGR designs, making it an attractive solution for low temperature coefficient (TC) voltage references. Proportional to absolute temperature (PTAT) current digital‐to‐analog converters (DACs) are used to suppress the effect of process variation and device mismatch on TC. The compensation signal is generated using the voltage difference of two bipolar junction transistor (BJT) emitter–bases whose currents are the sum and difference of the PTAT current and the zero to absolute temperature (ZTAT) current, respectively. The proposed CM BGR is designed with 0.18‐μm BIPOLAR CMOS DMOS process. A TC is 2.41 ppm/°C over a wide temperature range of −40°C to 150°C. The linear sensitivity of the supply voltage from 1.2 to 2 V is 0.027%/V. With an active area of 0.0721 mm2, it consumes 68 μA at room temperature. The integrated output noise from 0.1 to 10 Hz is 21.9 μV.

Gradient-descent hardware-aware training and deployment for mixed-signal neuromorphic processors

Mixed-signal neuromorphic processors provide extremely low-power operation for edge inference workloads, taking advantage of sparse asynchronous computation within spiking neural networks (SNNs). However, deploying robust applications to these devices is complicated by limited controllability over analog hardware parameters, as well as unintended parameter and dynamical variations of analog circuits due to fabrication non-idealities. Here we demonstrate a novel methodology for offline training and deployment of SNNs to the mixed-signal neuromorphic processor DYNAP-SE2. Our methodology applies gradient-based training to a differentiable simulation of the mixed-signal device, coupled with an unsupervised weight quantization method to optimize the network’s parameters. Parameter noise injection during training provides robustness to the effects of quantization and device mismatch, making the method a promising candidate for real-world applications under hardware constraints and non-idealities. This work extends Rockpool, an open-source deep-learning library for SNNs, with support for accurate simulation of mixed-signal SNN dynamics. Our approach simplifies the development and deployment process for the neuromorphic community, making mixed-signal neuromorphic processors more accessible to researchers and developers.

A 12-bit, 27.8-ps resolution, Anti-PVT variation multi-parallel sampling based coarse-fine TDC for LiDAR sensors

This paper presents a multi-parallel sampling based coarse-fine time-to-digital converter (TDC) with sub-gate delay resolution, large measurement range and high conversion rate for light detection and ranging (LiDAR) sensors. The fine-TDC is designed based on a voltage-controlled delay line (VCDL) but with multi-parallel sampling D flip-flop (DFF) groups to achieve a sub-gate delay resolution based on multi-phase interpolation. These DFF groups are triggered by several successively delayed sampling clocks that generated by a phase-locked loop (PLL) based multi-phase clock generator. The coarse-TDC composed of a coarse counter and a logical control circuit (LCC) is designed to enlarge the measurement range. The LCC is used to calibrate and guarantee the coarse counter neither over-counted nor under-counted. Since the delay of delay units in fine-TDC is also voltage-controlled by another PLL, the resolution of this proposed TDC is robust to process-voltage-temperature (PVT) variation. Besides, this proposed TDC architecture also has the property of dynamic element matching (DEM), which contributes to mitigate the impact of device mismatch and scramble the quantization noise. The post-layout simulations demonstrate a 12-bit, 27.8-ps time resolution, 0.86-LSB DNL, 0.92-LSB INL with 13.6-mW power consumption at 33.3-MS/s under a 1.8-V supply.

Nail-extraction device mismatch: an issue in developing countries intramedullary nail removal practice.

Intramedullary nail is the gold standard in the management of long bone diaphyseal fractures of tibia and femur. The jig of these nails has corresponding extraction device whose pitch for nail coupling come in various sizes. This unlike plate and screws may be difficult to predict preoperatively and may pose a problem during removal. Difficulties in removal may arise due to the proliferation of nail brands especially in developing countries. The study aims to identify the incidence of extraction device mismatch among orthopaedic surgeons in Nigeria as well as the indications and complications associated with intramedullary nail removal. A two-page questionnaire was administered to 87 orthopaedic surgeons attending the Annual General Meeting of the Nigerian Medical Association. The attitudes of the participants towards intramedullary nail were assessed. All participants agree to asymptomatic removal. Patients wish was the leading indication for asymptomatic removal among the participants. Sixty-one percent of the surgeons have had the need to remove a nail different from the brand in the hospital their practice. The commonest indication for symptomatic removal was infections. Forty-seven percent of the participant encountered nail extraction-device mismatch. The incidence of extraction device mismatch may portend a public health issue. There may be need for patient who had intra medullary nail insertion to be told their brand. We advocate for standardization of extraction device pitch for intramedullary nail.

Design of Fully Differential Amplification Circuit and Analysis of Related Parameters Based on Feedback Mechanism

In this paper, a new feedback-based mismatch reduction method is proposed for CMOS process-based differential circuit design. The method combines an active feedback circuit and a differential amplifier circuit to reduce the error caused by device mismatch by utilizing the feedback signal, which is calculated to achieve higher circuit performance and accuracy. Meanwhile, based on the actual circuit simulation in Candence, it is concluded that under the conditions of input voltage of 5V, operating current of 100mA, and the same transistor parameters, the circuit with the introduction of the feedback mechanism is able to achieve a maximum gain of about 10dB and a lower common mode rejection ratio at the same frequency compared with the circuit without feedback.

55 nm CMOS Mixed-Signal Neuromorphic Circuits for Constructing Energy-Efficient Reconfigurable SNNs

The development of brain-inspired spiking neural networks (SNNs) has great potential for neuromorphic edge computing applications, while challenges remain in optimizing power-efficiency and silicon utilization. Neurons, synapses and spike-based learning algorithms form the fundamental information processing mechanism of SNNs. In an effort to achieve compact and biologically plausible SNNs while restricting power consumption, we propose a set of new neuromorphic building circuits, including an analog Leaky Integrate-and-Fire (LIF) neuron circuit, configurable synapse circuits and Spike Driven Synaptic Plasticity (SDSP) learning algorithm circuits. Specifically, we explore methods to minimize large leakage current and device mismatch effects, and optimize the design of these neuromorphic circuits to enable low-power operation. A reconfigurable mixed-signal SNN is proposed based on the building circuits, allowing flexible configuration of synapse weights and attributes, resulting in enhanced SNN functionality and reduced unnecessary power consumption. This SNN chip is fabricated using 55 nm CMOS technology, and test results indicate that the proposed circuits have the ability to closely mimic the behaviors of LIF neurons, synapses and SDSP mechanisms. By configuring synaptic arrays, we established varied connections between neurons in the SNN and demonstrated that this SNN chip can implement Pavlov’s dog associative learning and binary classification tasks, while dissipating less energy per spike of the order of Pico Joules per spike at a firing rate ranging from 30 Hz to 1 kHz. The proposed circuits can be used as building blocks for constructing large-scale SNNs in neuromorphic processors.

Circuit-Level Memory Cell Simulation of Magnetic Bloch Line Racetrack Memory

The Bloch line racetrack memory (BL RTM) has recently been proposed as a novel device to overcome the problems of the conventional domain wall (DW) RTM such as stochastic shift and high shift threshold current due to process-induced roughness. In this work, we assess the performance of BL RTM memory cell by conducting circuit-level simulations. A micromagnetics-SPICE hybrid simulation framework is proposed and implemented as an optimal solution to guarantee both the computational efficiency and the micromagnetics-level accuracy. The feasibility of multi-bit BL memory operations is demonstrated as the stochastic Landau-Lifshitz-Gilbert (s-LLG) and Monte-Carlo simulations are carried out at room temperature to take into account the temperature effect and process-induced device mismatch. Furthermore, some crucial considerations in designing and optimizing the BL memory are addressed.

A 254-nW 20-kHz On-Chip RC Oscillator With 21-ppm/°C Minimum Temperature Stability and 10-ppm Long Term Stability.

This paper presents a temperature compensated RC oscillator (TC-RCO) designed in 130 nm CMOS technology using regular transistors. The TC-RCO uses constant transconductance biasing for first order temperature compensation. Device mismatch based offset correction and delay compensation techniques in the comparator are used to improve temperature instability by cancelling out second order effects. The oscillator achieves a minimum temperature stability down to 21 ppm/°C for a temperature range of -20 to 100 °C. In the lowest power mode, the oscillator consumes 254 nW power with a 1 V supply. The TC-RCO is operated in two modes, a low power mode that consumes an average of 254 nW and a high stability mode that consumes an average of 345 nW. A duty-cycling technique is used to correct offset after four cycles of oscillation. The oscillator exhibits long term stability of 10 ppm after 1 s integration time.

An Analytical MOS Device Model With Mismatch and Temperature Variation for Subthreshold Circuits

Subthreshold analog circuits are attractive for low-power, large-scale neuromorphic systems. However, subthreshold currents are exponentially sensitive to temperature and device mismatch, and a compact model that accounts for these effects is needed. We develop an analytical compact model with mismatch and temperature variation for subthreshold MOS devices. The model only requires an initial set of Monte Carlo (MC) simulations on individual devices for parameter extraction. Then the designer can use its parameterized analytical expressions for circuit design, instead of running repeated MC simulations on large circuits. We apply this model to a subthreshold current mirror design example. Good agreement between the developed model and Spectre simulations is achieved in a 28-nm fully-depleted silicon-on-insulator (FDSOI) process. The model is general and can also guide the design of other subthreshold circuits, such as low-power silicon neurons. It has been used to design Braindrop, the first neuromorphic chip programmed at a high level of abstraction.

0265 Validation Framework for Sleep Stage Scoring in Wearable Sleep Trackers and Monitors with Polysomnography Ground Truth

Abstract Introduction The rapid growth of point-of-care polysomnographic alternatives has necessitated standardized evaluation and validation frameworks. The current average across participant validation methods may overestimate the agreement between wearable sleep tracker devices and polysomnography (PSG) systems because of the high base rate of sleep during the night and the interindividual difference across the sampling population. Methods This study proposes an evaluation framework to assess the aggregating differences of the sleep architecture features and the chronologically epoch-by-epoch mismatch of the wearable sleep tracker devices and the PSG ground truth. An AASM-based sleep stage categorizing method was proposed to standardize the sleep stages scored by different types of wearable trackers. Sleep features and sleep stage architecture were extracted from the PSG and the wearable device’s hypnograms. Therefrom, a localized quantifier index was developed to characterize the local mismatch of sleep scoring. Results We evaluated different commonly used wearable sleep tracking devices with the data collected from 22 different subjects over 30 nights of 8-h sleeping. The proposed localization quantifiers can characterize the chronologically localized mismatches over sleeping time. The proposed framework not only characterizes the difference in the sleep stage distribution but also quantifies the chronologically localized mismatches over the sleeping time. Three major components of the framework consist of AASM-based sleep stage classification, sleep staging distribution analysis, and localized comparison analysis. The outperformance of the proposed method over existing evaluation methods was reported. Conclusion The proposed research extends our earlier work on evaluating commercial sleep trackers compared to PSG. The proposed evaluation method can be utilized to improve the sensor design and scoring algorithm. Support (if any) Nguyen, Quyen NT, et al. "Validation Framework for Sleep Stage Scoring in Wearable Sleep Trackers and Monitors with Polysomnography Ground Truth." Clocks & sleep 3.2 (2021): 274-288

Size matters - body size and acute device-implantation failure after LAAC

Abstract Funding Acknowledgements Type of funding sources: None. Introduction Patient-device mismatch in patients undergoing left atrial appendage closure (LAAC) may lead to failure to implant, dislocation, and cardiac tamponade. There is limited data about patient cohorts that are especially susceptible to these complications. Objective To analyse the association between body height, weight and acute complications due to probable device mismatch. Methods A retrospective analysis from a multicentre registry including consecutive patients undergoing LAAC was performed. Device related complications were defined as dislocation, failure to implant or cardiac tamponade requiring intervention. Results A total of 431 patients from 9 centres were included. Median age was 75 (interquartile range, IQR 70-79) years and 35.7% were female. Mean±SD body height was 171.3±8.8 cm and median weight was 80 (IQR 70-90) kg. Median CHADS-VASc score was 5 (IQR 3-5) and HAS-BLED score was 3 (IQR 3-4). Indications were bleeding (66.6%), stroke (9.7%) and other (23.6%). Acute device-related complications after LAAC occurred in 5.6% of cases (24/431): Failure to implant (3.0%), cardiac tamponade (2.1%), and dislocation (0.7%). Complications occurred significantly more often in the tercile with lowest body weight and highest body height (23.5% vs. 4.3%, p=0.01, Figure). Conclusion Acute device-related complications as sign of patient-device mismatch are most pronounced in patients with lowest body weight and highest body height.

Frequency-based CNN and attention module for acoustic scene classification

Acoustic scene classification (ASC) is an audio classification task that identifies the environment in which sounds are recorded. Audio-related machine learning algorithms suffer from the device mismatch problem; that is, when trained from audio data recorded from one device, the algorithms cannot generalize to audio samples recorded using another device. In this study, a novel convolutional neural network, called a frequency-aware convolutional neural network (FACNN), is introduced to solve the device mismatch problem by focusing on the frequency information of the audio samples. Furthermore, an attention module, called the frequency attention network (FANet), is introduced to generate an attention map based on the frequency information of the input feature maps. FANet helps the FACNN to focus on the important frequency information, thus improving performance. The proposed method is trained on the TAU Urban Acoustic Scenes 2019 Mobile development dataset and TAU Urban Acoustic Scenes 2020 Mobile development dataset. The proposed method achieves a state-of-the-art accuracy of 75.99% in the TAU Urban Acoustic Scenes 2019 Mobile development dataset and a competitive result of 72.6% in the TAU Urban Acoustic Scenes 2020 Mobile development dataset. In addition, a comparison of FANet with the convolutional block attention module (CBAM) and the squeeze-and-excitation network (SENet) was performed. The results show that FANet can mitigate the device mismatch problem by improving the performance of the unseen devices.

Efficient Statistical Parameter Extraction for Modeling MOSFET Mismatch

In this paper, we propose an efficient statistical parameter extraction method to accurately model the random device mismatch of MOSFETs. The key idea is to approximate the performance variations as mathematical functions of device mismatch. Based on these approximated functions and the electrical test data, we solve the unknown statistical parameters by nonlinear optimization. Our numerical experiments demonstrate that the proposed method can remarkably improve the modeling accuracy with affordable computational cost, compared against the state-of-the-art techniques.

Low power resource efficient CORDIC enabled neuron architecture using 45 nm CMOS technology

In this paper problem is addressed in the current study by providing resource-efficient CORDIC enabled neuron architecture (RECON) that can be customized to calculate both block of multiply-accumulate (MAC) unit and non-linear activation function (AF) operations. The CORDIC-enabled architecture implements MAC and AF operations using linear and trigonometric relationships, respectively. All physical parameters of the proposed design are built and verified using Cadence Virtuoso @ 45 nm technology. As compared to the conventional art of MAC design, our implementation of the signed fixed-point 8-bit MAC results in a 70% reduction in area, latency, and power product (ALP), as well as a 45 percent reduction in area, a 28% reduction in power dissipation, and a 20% reduction in latency. Both the process adjustments and the device mismatch are subjected to Monte-Carlo simulations. The proposed design is based on resource-intensive components such as multipliers and non-linear Activation Functions, modern hardware implementations of DNNs require more space (AFs). To access input features, weights, and biases, and improved on-chip quantized log2 based memory addressing approach is implemented. The bandwidth needs of DNNs' external memory are therefore decreased and dynamically adjusted. The Taylor series is also used to extract intensive higher speed and resource-efficient memory components for the various activation functions, and its order expansion has been altered for increased test accuracy. The MNIST dataset is used in earlier studies.

Analysis of Device Mismatches Effect on the Performance of UWB Receiver Front-End in Wireless Body Area Network Sensor Nodes

Today it is important to manufacture high quality integrated circuits which are insensitive to device mismatches. This paper presents an analysis of MOSFET transistors mismatches effect on the performance of UWB receiver front-end which constitute the most important part of Wireless Body Area Network sensor node. The receiver is based on Balun LNA with 25% fully differential double-balanced passive mixer. A PMOS and NMOS transistors mismatch models were proposed to determine LNA output offset voltage and mixer offset current respectively. The analysis result suggests that, to minimize NMOS current mismatch, and thus reducing second-order inter modulation distortion, the overdrive voltage must be maximized. A Monte Carlo and harmonic balance simulations were performed using 0.18µm CMOS process to evaluate the impact of mismatch as well as Vth mismatch on the receiver gain and IIP2. Simulation results show that IIP2 of the receiver is less sensitive to mixer NMOS mismatch but receiver gain is more sensitive. The receiver IIP2 confidence interval in case of NMOS mismatch is [24.674, 24.77]dBm and in case of NMOS Vth mismatch is [24.659, 24.857]dBm. This show the robustness of the proposed UWB receiver front end. Therefore the proposed circuit meets the requirement of UWB system perfectly which make it suitable for WBAN applications.

Effect of Device Mismatches in Differential Oscillatory Neural Networks

Analog implementation of Oscillatory Neural Networks (ONNs) has the potential to implement fast and ultra-low-power computing capabilities. One of the drawbacks of analog implementation is component mismatches which cause desynchronization and instability in ONNs. Emerging devices like memristors and VO2are particularly prone to variations. In this paper, we study the effect of component mismatches on the performance of differential ONNs (DONNs). Mismatches were considered in two main blocks: differential oscillatory neurons and synaptic circuits. To measure DONN tolerance to mismatches in each block, performance was evaluated with mismatches being present separately in each block. Memristor-bridge circuits with four memristors were used as the synaptic circuits. The differential oscillatory neurons were based on VO2-devices. The simulation results showed that DONN performance was more vulnerable to mismatches in the components of the differential oscillatory neurons than to mismatches in the synaptic circuits. DONNs were found to tolerate up to 20% mismatches in the memristance of the synaptic circuits. However, mismatches in the differential oscillatory neurons resulted in non-uniformity of the natural frequencies, causing desynchronization and instability. Simulations showed that 0.5% relative standard deviation (RSD) in natural frequencies can reduce DONN performance dramatically. In addition, sensitivity analyses showed that the high threshold voltage of VO2-devices is the most sensitive parameter for frequency non-uniformity and desynchronization.

Clinical Feasibility and Familiarization Effects of Device Delay Mismatch Compensation in Bimodal CI/HA Users.

Subjects utilizing a cochlear implant (CI) in one ear and a hearing aid (HA) on the contralateral ear suffer from mismatches in stimulation timing due to different processing latencies of both devices. This device delay mismatch leads to a temporal mismatch in auditory nerve stimulation. Compensating for this auditory nerve stimulation mismatch by compensating for the device delay mismatch can significantly improve sound source localization accuracy. One CI manufacturer has already implemented the possibility of mismatch compensation in its current fitting software. This study investigated if this fitting parameter can be readily used in clinical settings and determined the effects of familiarization to a compensated device delay mismatch over a period of 3-4 weeks. Sound localization accuracy and speech understanding in noise were measured in eleven bimodal CI/HA users, with and without a compensation of the device delay mismatch. The results showed that sound localization bias improved to 0°, implying that the localization bias towards the CI was eliminated when the device delay mismatch was compensated. The RMS error was improved by 18% with this improvement not reaching statistical significance. The effects were acute and did not further improve after 3 weeks of familiarization. For the speech tests, spatial release from masking did not improve with a compensated mismatch. The results show that this fitting parameter can be readily used by clinicians to improve sound localization ability in bimodal users. Further, our findings suggest that subjects with poor sound localization ability benefit the most from the device delay mismatch compensation.

A body‐driven rail‐to‐rail 0.3 V operational transconductance amplifier exploiting current gain stages

A body‐driven rail‐to‐rail 0.3 V operational transconductance amplifier exploiting current gain stages