Development Of IC Technology Research Articles

Research and optimization of the gain characteristics of cascode amplifiers

Abstract. With the continuous development of IC technology, high-performance operational amplifiers are widely used in various circuit systems such as high-speed Analog-to-Digital Converters (ADCs), Digital-to-Analog Converters (DACs), switched capacitor filters, bandgap voltage reference sources, precision comparators. The amplifier has become the core unit circuit of analog IC and mixed-signal IC design, and its performance directly affects the overall performance of the circuit and system. The design of high-performance operational amplifiers has always been one of the hotspots in the research of analog IC design in order to meet the needs of various application fields. Cascode Amplifier is a classic structure widely used in high-frequency and high-gain electronic circuits. This project aims to study the gain characteristics of cascode amplifiers, explore the main factors affecting their gain, and propose methods to optimize the gain. Through theoretical analysis and simulation, the influence of different parameters on gain is verified. Then the optimization strategy is summarized to provide a reference for actual circuit design.

INFTUENCE OF E-LEARNING ON THE DEVELOPMENT OF THE COUNTRY

With development of information and communication technologies in the world appears the question of changes in education system, the question of changes in the system of training, and retraining of competitive and highly skilled specialists for the modern labor market. One of the most promising and developing forms of modern training is the technology of e-learning. Each specialist and master affects not only his own financial life, but also the development of the whole country. That is why the problem of the impact of the development of IC technologies, in particular e-learning on the development of the country, is relevant. DOI: https://doi.org/10.28925/2414-0325.2017.3.105dv9

Strategies to Ensure Electromigration Reliability of Cu/Low-k Interconnects at 10 nm

A key element for future silicon IC technology development is the containment of electromigration – induced failure of Cu / low-k interconnects. Continued progress in meeting electromigration reliability requirements for future technology nodes will require a multi-faceted approach to the problem: first the development of effective process solutions to limit the impact of technology scaling on electromigration life-time reduction; and second, the provision of models of failure that are representative of circuit operation to determine realistic current-limiting design rules. We will show that process solutions involve limiting the rate of transport along interfaces and grain boundaries in the damascene trench architecture using metal capping layers and Cu alloys. Most models of electromigration failure have been developed using DC stress conditions, while circuits predominantly operate with non-DC (pulsed DC or AC) signals. Understanding the relationship between failure under DC and non-DC conditions is a necessary aspect of realistic reliability characterization. In this paper we review: our recent studies that establish the relationship between Cu microstructure, metallic capping and dilute Cu alloy additions and thereby identify effective scenarios for mitigation with technology scaling; and experimental studies of electromigration failure under non-DC stress that explore the physical mechanisms involved.

Packet triggered prediction based task migration for network-on-chip

The development of IC technology makes Network-on-Chip (NoC) an attractive architecture for future massive parallel systems. Task migration optimize the overall communication performance of NoCs since the changing phases of execution make static task mapping insufficient. It is well-known that the communication behavior of many applications are predictable, which makes it feasible to use prediction to guide task migration. The triggering of activating a task migration is also important. In this paper, we first defined and analyzed predictabilities of applications, and then compared different ways of triggering for migration. We then modified the Genetic Algorithm (GA) based task remapping and proposed two other task migration algorithms: Simple Exchange (SE) and Benefit Assess (BA). A mechanism called node lock is also used to reduce unnecessary and costly migrations. Simulation results on real applications from PARSEC benchmark suites show that the SE, BA and GA algorithms can reduce 21.4%, 34.0% and 34.9% of number of hops, and 17.3%, 27.2% and 26.3% in terms of average latency respectively, compared with the system without task migration; BA and SE reduce 72.0% and 78.7% of migrations without significant performance degradation compared with GA, and the node lock mechanism can further remove 37.3% and 46.0% of migrations while achieving almost the same performance.

The status and trend of novel process and technology in nano-IC manufacturing

The technology development of micro-nano electronics in global IC industry is summarized and reviewed in the present paper. There are many challenges and opportunities as the innovative devices and materials have gradually been applied to IC manufacture. As ITRS 2011 Roadmap shows that gate length will shrink to 20 nm in 2013, the industry mainstream manufacturing technologies of the nano-electronics seems moving toward the goal. It is well known that the IC technology development basically depends on material science. In Section 2, some new material and process technologies are highlighted, such as strained silicon, high K and metal gate, ultra-low K, 450 mm silicon wafer, and immersion lithography technologies are the foundation of IC manufacture. The process integration for advanced CMOS manufacture technology is discussed in Section 3. As an example, 20 nm process flow scheme is explained and some comparison is made to the precious generation technology. The main process flow difference between 28 nm technology and 20 nm technology is illustrated and some explanations are presented. In Section 4, 3D system packaging technology is introduced. Some preliminary TSV experimental data made by SMIC are shown. It is expected that 3D TSV Wide I/O would eventually be inevitable in 28 nm production and beyond. In Section 5, the research and development of nonvolatile memory are summarized, such as RRAM, PcRAM and MRAM. Some lab experimental and measurement results from SMIC are demonstrated. It is believed that PcRAM, which is relatively mature technology, mass production will probably come up in the mainland in a few years. In Section 6, a couple of new transistor architectures are introduced and some experimental data are demonstrated, such as local SOI and GAA, and some experimental data are shown. Finally, the comments for domestic R&D strategy in IC area are proposed to future IC R&D direction.

Nano-Motion X-Y Stage by Pneumatic Servo Spherical Bearing Actuators

With the development of IC technology, ultraprecise positioning actuators with nanometre-order resolution are in demand, especially for semiconductor stepper equipment. A prototype X-Y stage for ultraprecise positioning composed of six pneumatic servo spherical bearing actuators (PSSBAs) was developed and its specifications were evaluated especially focusing on the step response and its minimum resolution. The minimum positioning resolution of the prototype was 3 nm under the best conditions, and the positioning resolution as a practical specification was approximately 10 nm for all conditions, even without feedback controls. With a simple feedback control, the minimum resolution was improved to 1 nm, which is enough to meet the demands of current ultraprecise positioning technology.

The status and trend of novel process and technology in nano-IC manufacturing

The technology development of micro-nano electronics in global IC industry is summarized and reviewed in the present paper. There are many challenges and opportunities as the innovative devices and materials have gradually been applied to IC manufacture. As ITRS 2011 Roadmap shows that gate length will shrink to 20 nm in 2013, the industry mainstream manufacturing technologies of the nano-electronics seems moving toward the goal. It is well known that the IC technology development basically depends on material science. In Section 2, some new material and process technologies are highlighted, such as strained silicon, high K and metal gate, ultra-low K, 450 mm silicon wafer, and immersion lithography technologies are the foundation of IC manufacture. The process integration for advanced CMOS manufacture technology is discussed in Section 3. As an example, 20 nm process flow scheme is explained and some comparison is made to the precious generation technology. The main process flow difference between 28 nm technology and 20 nm technology is illustrated and some explanations are presented. In Section 4, 3D system packaging technology is introduced. Some preliminary TSV experimental data made by SMIC are shown. It is expected that 3D TSV Wide I/O would eventually be inevitable in 28 nm production and beyond. In Section 5, the research and development of nonvolatile memory are summarized, such as RRAM, PcRAM and MRAM. Some lab experimental and measurement results from SMIC are demonstrated. It is believed that PcRAM, which is relatively mature technology, mass production will probably come up in the mainland in a few years. In Section 6, a couple of new transistor architectures are introduced and some experimental data are demonstrated, such as local SOI and GAA, and some experimental data are shown. Finally, the comments for domestic R&D strategy in IC area are proposed to future IC R&D direction.

Developments of TaN ALD Process for 3D Conformal Coatings

AbstractThere is a growing interest in producing tantalum nitride (TaN) thin films for various industrial applications. For example, in microelectronics, the development of IC technology is driven by the need to increase both performance and functionality while reducing power and cost. This goal can be achieved by several solutions among which the introduction of architecture enhancements such as 3D integration. The most challenging step is the deposition of a conformal, continuous, and adherent diffusion barrier. In this work, atomic layer deposition (ALD) of TaN thin films is explored using the combination between the thermodynamical behavior of the precursor, mass transfer in the reactor, and the operating conditions. TaN thin film deposition on very complex shape substrates, such as nanodots, TSV, silicon nanowires, and carbon nanotubes, has been evaluated.

Imaging algorithm for synthetic aperture interferometric radiometer in near field

With the benefits of digital IC technology development, the synthetic aperture interferometric radiometer (SAIR) technique is growing fast and expanding to more and more application areas. The near field imaging detection is a potential application which has received increasing demand recently. Because the Fourier imaging theory of the traditional SAIR is based on far-field approximation, it will be invalid for near-field condition. This paper is devoted to establishing a new accurate imaging algorithm for near-field SAIR imaging. Firstly, the visibility function in near field is deduced and the relationship of which to far-field visibility function is analyzed. Then, a numerical method based on pseudo inverse and focal plane approximation is developed. The effectivity of this method is tested with imaging simulation of point source and extended source, and the superiority is also demonstrated by comparing with the existing phase-modified Fourier transform method. At last, the field experiment with one-dimensional SAIR instrument is performed to validate the practical feasibility of this method.

Through Silicon Via Technology: Cost effective Cu-TSV Interconnects by EMC3D and Technical Challenges with Cu-TSV

The development of IC technology is driven by the need to increase performance and functionality while reducing size, power and cost. The continuous pressure to meet those requirements has created innovative, small, cost-effective 3-D packaging technologies. 3-D packaging can offer significant advantages in performance, functionality and form factor for future technologies. Breakthrough in wafer level packaging using through silicon via technology has proven to be technologically beneficial. Integration of several key and challenging process steps with a high yield and low cost is key to the general adoption of the technology. This paper will outline the breakthroughs in cost associated with an iTSV or Via-Mid structure in a integrated process flow. Key process technologies enabling 3-D chip:Via formationInsulator, barrier and seed depositionCopper filling (plating),CMPWafer thinningDie to Wafer/chip alignment, bonding and dicing This presentation will investigate these techniques that require interdisciplinary coordination and integration that previously have not been practiced. We will review the current state of 3-D interconnects and the of a cost effective Via-first TSV integrated process.

Development and regional characteristics of the Hungarian information and communication sector (ICT)

The rapid development of IC technologies and in parallel the increasing demand for more information and knowledge from the actors of economy, institutions and members of society created the ICT-sector into the core of “new economy” and information society. This process got an important role in the major research topics in economic and social geography, thanks to the high innovation capacity of the sector, the new forms of organizing economic activities and the discussed spatial and social effects of the development. The rising ICT sector and new elements of information society implied a special interest not only from basic research, but even applied research areas, for example the emerging role of ICTs in regional development and regional policies and some sectoral policies (economy, education, health etc.). This process had a special role in the former COMECON area. The info-intensive activities had a crucial role in building up a new, market-led model of economy in the transition period. The new forms of communication offer to re-organize the personal connections, the local societies and created new “spaces and places” for new communities. The double modernisation effect of ICTs in converging countries in the period of transition (1989/1990 – 2004) had a serious impact on spatial processes. In our paper we concentrate on the role of ICTs in transforming Hungarian economy, increasing the competitiveness of the country. We try to describe the spatial structure of the sector and its part in forming the new regional structure of the country.

Lifetime modelling for microsystems integration: from nano to systems

Due to the rapid development of IC technology the traditional packaging concepts are making a transition into more complex system integration techniques in order to enable the constantly increasing demand for more functionality, performance, miniaturisation and lower cost. These new packaging concepts (as e.g. system in package, 3D integration, MEMS-devices) will have to combine smaller structures and layers made of new materials with even higher reliability. As these structures will more and more display nano-features, a coupled experimental and simulative approach has to account for this development to assure design for reliability in the future. A necessary “nano-reliability” approach as a scientific discipline has to encompass research on the properties and failure behaviour of materials and material interfaces under explicit consideration of their micro- and nano-structure and the effects hereby induced. It uses micro- and nano-analytical methods in simulation and experiment to consistently describe failure mechanisms over these length scales for more accurate and physically motivated lifetime prediction models. This paper deals with the thermo-mechanical reliability of microelectronic components and systems and methods to analyse and predict it. Various methods are presented to enable lifetime prediction on system, component and material level, the latter promoting the field of nano-reliability for future packaging challenges in advanced electronics system integration.

Progress in reliability research in the micro and nano region

Due to the rapid development of IC technology the traditional packaging concepts are making a transition into more complex system integration techniques in order to enable the constantly increasing demand for more functionality, performance and miniaturisation. These new concepts will have to combine smaller structures and layers made of new materials with even higher reliability. As these structures will more and more display nano-features, a coupled experimental and simulative approach has to account for this development to assure design for reliability in the future. A necessary “nano-reliability” approach as a scientific discipline has to encompass research on the properties and failure behaviour of materials and material interfaces under explicit consideration of their nano-structure and the effects hereby induced. It uses nano-analytical methods in simulation and experiment to consistently describe failure mechanisms on that length scale for more accurate and physically motivated lifetime prediction models for use on a larger (i.e. then the micro) scale. This paper deals with the thermo-mechanical reliability of microelectronic components and systems and methods to analyse and predict it. Various methods are presented to enable lifetime prediction on system, component and material level, the latter introducing the field of nano-reliability for nano-packaging in advanced electronics system integration.

Total TCAD strategy for DFM in IC technology development

The authors present some of the simulation tools available to IC technology and circuit designers and discuss their importance in a Design For Manufacturability (DFM) strategy. It is demonstrated how these simulators, when combined with Design Of Experiment (DOE) and Response Surface Methodology (RSM), can be used to increase engineering knowledge while at the same time reducing the number of simulations required to optimise a process. The idea of contour plotting response distribution parameters to help determine robust manufacturing conditions is also introduced together with a methodology of using simulation results to rapidly produce histograms of response distributions. An environment to help automate the above approach is presented, and its use as part of a DFM strategy is illustrated through an example of a process/device optimisation.

A pragmatic approach to integrated process/device/circuit simulation for IC technology development

A novel approach to integrated process/device/circuit simulation is proposed which allows pragmatic, computationally efficient IC technology CAD at the mixed-mode device/circuit level. The approach is demonstrated with a simulation system for advanced silicon bipolar technologies. This system comprises the process simulator SUPREM-3 integrated with the seminumerical mixed-mode device/circuit simulator MMSPICE by a program called SUMM. The integration is characterized by the unique evaluation of the physical (structure-dependent) parameters for the MMSPICE BJT model from a one-dimensional doping profile generated by SUPREM-3 without any optimization-based extraction. The capability of the application-specific SUMM/MMSPICE integrated system to reliably predict device characteristics and their sensitivities to process-flow variations is verified by measurements and by purely numerical simulations with PISCES-II. The utility of the system in IC technology development is exemplified by simulations. >

Research and development of IC technology in Japan: T. Sugano Fifth Solid State Circuits Conference — ESSCIRC 79, IEE Publn. 178, 139

Research and development of IC technology in Japan: T. Sugano Fifth Solid State Circuits Conference — ESSCIRC 79, IEE Publn. 178, 139

Research and development of IC technology in Japan : T. Sugano. Fifth Solid State Circuits Conference—ESSCIRC 79, IEE Publn.178, 139

Research and development of IC technology in Japan : T. Sugano. Fifth Solid State Circuits Conference—ESSCIRC 79, IEE Publn.178, 139

集積回路の発展とテレビジョン技術の変革

集積回路の発展とテレビジョン技術の変革