Destination Processors Research Articles

Training-Based Channel Estimation Algorithms for Dual Hop MIMO OFDM Relay Systems

In this paper, we consider minimum-mean-square error (MMSE) training-based channel estimation for two-hop multiple-input multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) relaying systems. The channel estimation process is divided into two main phases. The relay-destination channel is estimated in the first phase and can be obtained using well-known point-to-point MIMO OFDM estimation methods. In the second phase, the source-relay channel is estimated at the destination with the use of a known training sequence that is transmitted from the source and forwarded to the destination by a nonregenerative relay. To obtain an estimate of the source-relay channel, the source training sequence, relay precoder, and destination processor, require to be optimized. To solve this problem, we first derive an iterative algorithm that involves sequentially solving a number of convex optimization problems to update the source, relay, and destination design variables. Since the iterative algorithm may be too computationally expensive for practical implementation, we then derive simplified solutions that have reduced computational complexity. Simulation results demonstrate the effectiveness of the proposed algorithms.

A multiprocessor-oriented power-conscious scheduling algorithm for periodic tasks

With the rapid development of advanced technology in VLSI circuit designs, many processors could provide dynamic voltage scaling (DVS) to save power consumption when the supply voltage is allowed to be lower. In this paper, we propose a multiprocessor-oriented power-conscious scheduling algorithm for the real-time periodic tasks with task migration constrained scheme. We classify periodic tasks into fixed tasks and migration tasks, and limit the number of migration tasks and the number of destination processors which execute migration tasks. The proposed algorithm is made up of two steps. Firstly, choosing a processor to sort all of the periodic tasks in a non-increasing order according to task utilization, afterwards, allocating them to other processors. Secondly, scheduling the migration tasks with a virtual execution windows policy, and then scheduling the fixed tasks with EDF algorithm. The experiment results show that compared with arbitrary task migration policy and no task migration allowed policy, the power consumption in multiprocessor real-time periodic tasks scheduling is lowered significantly with the proposed algorithm.

Dynamic routing of data stream tuples among parallel query plan running on multi-core processors

In this paper, a method for fast processing of data stream tuples in parallel execution of continuous queries over a multiprocessing environment is proposed. A copy of the query plan is assigned to each of processing units in the multiprocessing environment. Dynamic and continuous routing of input data stream tuples among the graph constructed by these copies (called the Query Mega Graph) for each input tuple determines that, after getting processed by each processing unit (e.g., processor), to which next processor it should be forwarded. Selection of the proper next processor is performed such that the destination processor imposes the minimum tuple latency to the corresponding tuple, among all of the alternative processors. The tuple latency is derived from processing, buffering and communication time delay which varies in different practical parallel systems. Parallel system architectures that would be suitable as the desired multiprocessing environment for employing the proposed Dynamic Tuple Routing (DTR) method are considered and analyzed. Also, practical challenges and issues for the proper parallel underlying system are discussed. Implementation of the desired parallel system on multi-core systems is provided and used for evaluating the proposed DTR method. Evaluation results show that the proposed DTR method outperforms similar method such as the Eddies in terms of tuple latency, throughput and tuple loss.

An optimal scheduling algorithm for an agent-based multicast strategy on irregular networks

This paper describes an agent-based approach for scheduling multiple multicast on wormhole switch-based networks with irregular topologies. Multicast/broadcast is an important communication pattern, with applications in collective communication operations such as barrier synchronization and global combining. Our approach assigns an agent to each subtree of switches such that the agents can exchange information efficiently and independently. The entire multicast problem is then recursively solved with each agent sending message to those switches that it is responsible for. In this way, communication is localized by the assignment of agents to subtrees. This idea can be easily generalized to multiple multicast since the order of message passing among agents can be interleaved for different multicasts. The key to the performance of this agent-based approach is the message-passing scheduling between agents and the destination processors. We propose an optimal scheduling algorithm, called ForwardInSwitch to solve this problem. We conduct extensive experiments to demonstrate the efficiency of our approach by comparing our results with SPCCO, a highly efficient multicast algorithm reported in literature. We found that SPCCO suffers link contention when the number of simultaneous multiple multicast becomes large. On the other hand, our agent-based approach achieves better performance in large cases.

Optimizing Communications of Dynamic Data Redistribution on Symmetrical Matrices in Parallelizing Compilers

Dynamic data redistribution is used to enhance data locality and algorithm performance by reducing interprocessor communication in many parallel scientific applications on distributed memory multicomputers. Since the redistribution is performed at runtime, there is a performance tradeoff between the efficiency of the new data decomposition for a subsequent phase of an algorithm and the cost of redistributing data among processors. In this paper, we present a processor replacement scheme to minimize the cost of interprocessor data exchange during runtime. The main idea of the proposed technique is to develop a replacement function for reordering logical processors in the destination phase. Based on the replacement function, a realigned sequence of destination processors can be derived and is then used to perform data decomposition in the receiving phase. Together with local matrix and compressed CRS vectors transposition schemes, the interprocessor communication can be eliminated during runtime. A significant improvement of this approach is that the realignment of data can be performed without interprocessor communication for special cases. The second contribution of the present technique is that the complicated communication sets generation could be simplified by applying local matrix transposition. Consequently, the indexing cost could be reduced significantly. The proposed techniques can be applied in both dense and sparse applications. A generalized symmetric redistribution algorithm is also presented in this work. To analyze the efficiency of the proposed technique, the theoretical analysis proves that up to (p-1)/p data transmission cost can be saved. For general cases, the symmetric redistribution algorithm saves 1/p communication overheads compared with the traditional method. Experimental results also show that the proposed techniques provide superior performance in most data redistribution instances

A fault-tolerant message passing algorithm and its hardware implementation

A message passing algorithm for processor arrays that can tolerate any number of faulty blocks, which form any shape, is presented. Each message is delivered to its destination, provided that the destination processor is not surrounded by faults. In this case the message is returned to its source processor. Only local knowledge of faults is demanded. The hardware implementation of this algorithm leads to a message passing coprocessor which is allocated at each processor of the array. No need for high silicon overhead is required for the implementation of the message passing coprocessor. This coprocessor executes only the fault tolerant message passing algorithm presented here. The usage of the proposed coprocessor improves the general processing efficiency, as well as, the performance reliability under faulty conditions.

A generalized processor mapping technique for array redistribution

In many scientific applications, array redistribution is usually required to enhance data locality and reduce remote memory access in many parallel programs on distributed memory multicomputers. Since the redistribution is performed at runtime, there is a performance trade-off between the efficiency of the new data decomposition for a subsequent phase of an algorithm and the cost of redistributing data among processors. In this paper, we present a generalized processor mapping technique to minimize the amount of data exchange for BLOCK-CYCLIC(kr) to BLOCK-CYCLIC(r) array redistribution and vice versa. The main idea of the generalized processor mapping technique is first to develop mapping functions for computing a new rank of each destination processor. Based on the mapping functions, a new logical sequence of destination processors can be derived. The new logical processor sequence is then used to minimize the amount of data exchange in a redistribution. The generalized processor mapping technique can handle array redistribution with arbitrary source and destination processor sets and can be applied to multidimensional array redistribution. We present a theoretical model to analyze the performance improvement of the generalized processor mapping technique. To evaluate the performance of the proposed technique, we have implemented the generalized processor mapping technique on an IBM SP2 parallel machine. The experimental results show that the generalized processor mapping technique can provide performance improvement over a wide range of redistribution problems.

ON MESSAGE PACKAGING IN TASK SCHEDULING FOR DISTRIBUTED MEMORY PARALLEL MACHINES

In this paper, we report a performance gap betweeen a schedule with small makespan on the task scheduling model and the corresponding parallel program on distributed memory parallel machines. The main reason of the gap is the software overhead in the interprocessor communication. Therefore, speedup ratios of schedules on the model do not approximate well to those of parallel programs on the machines. The purpose of the paper is to get a task scheduling algorithm that generates a schedule with good approximation to the corresponding parallel program and with small makespan. For this purpose, we propose algorithm BCSH that generates only bulk synchronous schedules. In those schedules, no-communication phases and communication phases appear alternately. All interprocessor communications are done only in the latter phases, and thus the corresponding parallel programs can make better use of the message packaging technique easily. It reduces many software overheads of messages form a source processor to the same destination processor to almost one software overhead, and improves the performance of a parallel program significantly. Finally, we show some experimental results of performance gaps on BCSH, Kruatrachue's algorithm DSH, and Ahmad et al's algorithm ECPFD. The schedules by DSH and ECPFD are famous for their small makespans, but message packaging can not be effectively applied to the corresponding program. The results show that a bulk synchronous schedule with small makespan has advantages that the gap is small and the corresponding program is a high performance parallel one.

THE VECTOR MULTIPROCESSOR

The Vector Multiprocessor brings to the multiprocessor what vectorization brought to the single processor. In addition to the usual complement of logic and arithmetic units, each processor contains a programmable communication unit with registers that communicate directly with comparable registers in neighboring processors via an n-dimensional interconnection network. Interprocessor communication tasks are performed to and from these registers in the same way that computational tasks are performed on a uniprocessor. Communication is shown to be optimal for a large class of communication tasks. Elements are transmitted, in parallel, to their destination processors at an average rate of one per communication cycle. This result, called O(1) access, is used to develop a balanced communication system where local and global access are comparable. It is also used to support the vector parallel paradigm where all arrays are uniformly distributed and the user interface looks like a uniprocessor interface. Both coarse- and fine-grain performance models are provided, which demonstrate the unexpected result that communication is asymptotically negligible compared to computational time. Finally, three performance models are presented for the spherical harmonic transform, which is the most communication-intensive part of climate model dynamics.

Efficient Algorithms for Block-Cyclic Redistribution of Arrays

The block-cyclic data distribution is commonly used to organize array elements over the processors of a coarse-grained distributed memory parallel computer. In many scientific applications, the data layout must be reorganized at run-time in order to enhance locality and reduce remote memory access overheads. In this paper we present a general framework for developing array redistribution algorithms. Using this framework, we have developed efficient algorithms that redistribute an array from one block-cyclic layout to another. Block-cyclic redistribution consists of index set computation , wherein the destination locations for individual data blocks are calculated, and data communication , wherein these blocks are exchanged between processors. The framework treats both these operations in a uniform and integrated way. We have developed efficient and distributed algorithms for index set computation that do not require any interprocessor communication. To perform data communication in a conflict-free manner, we have developed direct indirect and hybrid algorithms. In the direct algorithm, a data block is transferred directly to its destination processor. In an indirect algorithm, data blocks are moved from source to destination processors through intermediate relay processors. The hybrid algorithm is a combination of the direct and indirect algorithms. Our framework is based on a generalized circulant matrix formalism of the redistribution problem and a general purpose distributed memory model of the parallel machine. Our algorithms sustain excellent performance over a wide range of problem and machine parameters. We have implemented our algorithms using MPI, to allow for easy portability across different HPC platforms. Experimental results on the IBM SP-2 and the Cray T3D show superior performance over previous approaches. When the block size of the cyclic data layout changes by a factor of K , the redistribution can be performed in O( log K) communication steps. This is true even when K is a prime number. In contrast, previous approaches take O(K) communication steps for redistribution. Our framework can be used for developing scalable redistribution libraries, for efficiently implementing parallelizing compiler directives, and for developing parallel algorithms for various applications. Redistribution algorithms are especially useful in signal processing applications, where the data access patterns change significantly between computational phases. They are also necessary in linear algebra programs, to perform matrix transpose operations.

Operation and performance of an ATM based demonstrator for the sequential option of the ATLAS trigger

This paper describes an implementation on a small scale demonstrator of the sequential option for the ATLAS trigger. This demonstrator is built around an ATM switch connecting source modules, destination processors, a supervisor and a monitor. The source modules emulate a group of detector read-out buffers. We describe the hardware and software architecture of the system. We investigate the performance of the demonstrator in various configurations and with different sets of input parameters. Finally, we discuss the scaling of the results to the design of a large trigger system for ATLAS.

Heterogeneous process migration: the Tui system

Heterogeneous process migration is a technique whereby an active process is moved from one machine to another. It must then continue normal execution and communication. The source and destination processors can have a different architecture, that is, different instruction sets and data formats. Because of this heterogeneity, the entire process memory image must be translated during the migration. Tui is a migration system that is able to translate the memory image of a program (written in ANSI-C) between four common architectures (m68000, SPARC, i486 and PowerPC). This requires detailed knowledge of all data types and variables used with the program. This is not always possible in non-type-safe (but popular) languages such as ANSI-C, Pascal and Fortran. The important features of the Tui algorithm are discussed in great detail. This includes the method by which a program's entire set of data values can be located, and eventually reconstructed on the target processor. Performance figures demonstrating the viability of using Tui to migrate real applications are given. © 1998 John Wiley & Sons, Ltd.

Application-level load migration and its implementation on top of PVM

The development and experiment of a load (process) migration scheme conceptually similar to moving house is described. The basic idea is to migrate a process by starting a new process on another processor with checkpoint data prepared by the old process itself but transferred automatically by the migration system. The new process will then unpack the data and resume the computation. The migration mechanism of our facility is implemented by a set of library calls on top of PVM. It performs functions such as freezing and unfreezing communications, checking load conditions, selecting destination processors, starting new processes and receiving migrated data. Before migrating, a process needs to freeze communication, handle pending messages in the receive buffer and pack checkpoint data. Besides the usual merits of concurrency, location transparency and the absence of residual dependency, our scheme solves the incoming message problem at the application level and is portable and easy to use in a heterogeneous environment. Our experiment shows that our facility can help to utilize 74% of idle CPU cycles of a network of workatations with less than 6% overhead on their normal operations. © 1997 by John Wiley & Sons, Ltd.

Calculating controller area network (can) message response times

Controller Area Network (CAN) is a well-designed communications bus for sending and receiving short real-time control messages at speeds of up to 1Mbit/sec. One of the perceived drawbacks to CAN has been the inability to bound accurately the worst-case response time of a given message (i.e., the longest time between queueing the message and the message arriving at the destination processors). This paper presents an analysis to bound such latencies. A benchmark is used to illustrate the application of this analysis.

NIFDY

In this paper we present NIFDY , a network interface that uses admission control to reduce congestion and ensures that packets are received by a processor in the order in which they were sent, even if the underlying network delivers the packets out of order. The basic idea behind NIFDY is that each processor is allowed to have at most one outstanding packet to any other processor unless the destination processor has granted the sender the right to send multiple unacknowledged packets. Further, there is a low upper limit on the number of outstanding packets to all processors.We present results from simulations of a variety of networks (meshes, tori, butterflies, and fat trees) and traffic patterns to verify NIFDY 's efficacy. Our simulations show that NIFDY increases throughput and decreases overhead. The utility of NIFDY increases as a network's bisection bandwidth decreases. When combined with the increased payload allowed by in-order delivery NIFDY increases total bandwidth delivered for all networks. The resources needed to implement NIFDY are small and constant with respect to network size.

Calculating controller area network (CAN) message response times

Controller Area Network (CAN) is a well designed communications bus for sending and receiving short real-time control messages at speeds of up to 1Mbit/sec. One of the perceived drawbacks to CAN has been the inability to bound accurately the worst-case response time of a given message (i.e. the longest time between queueing the message and the message arriving at the destination processors). This paper presents analysis to bound such response times, including the costs of error handling and re-transmission.

Holistic schedulability analysis for distributed hard real-time systems

This paper extends the current analysis associated with static priority pre-emptive based scheduling to address the wider problem of analysing schedulability of a distributed hard real-time system; in particular it derives analysis for a distributed system where tasks with arbitrary deadlines communicate by message passing and shared data areas. A simple TDMA protocol is assumed, and analysis developed to bound not only the communications delays, but also the delays and overheads incurred when messages are processed by the protocol stack at the destination processor. The paper illustrates how a window-based analysis technique can be used to find the worst-case response times of a distributed task set. An extended example illustrating the application of the analysis is presented.

FTN topology and protocols

Abstract We have developed a network called FTN that satisfies the requirements for a large class of fault tolerant applications in distributed processing. (N denotes the number of devices and m = ⌈log2N⌉). The network has a high fault tolerance: up to m−2 faulty processors can be tolerated. The fault tolerance is high and optimal. The criteria of optimality is the following: the number of vertex disjoint paths is equal to the minimal degree in the graph (m−1). We have developed algorithms to provide routing in both faulty and nonfaulty systems. The paths generated by the algorithms are nearly the shortest paths for any two source and destination processors. The network can be constructed for a system of an arbitrary size. We developed an algorithm which can add a new processor at the small cost of modifying only O(m) edges. The O(m) diameter implies a low transit delay. A multiplexing/demultiplexing protocol can utilize up to m−1 nonblocking paths between any two processors to achieve a high throughput. In general the network has much better fault tolerance than the recently reported Incomplete Cube, can be designed for any number of processors in contrast to the Boolean Cube, and it has a significantly lower cost than the Generalized Hypercube network in terms of the link count.

Using the dual path property of omega networks to obtain conflict-free message routing

A strategy for dealing with communication conflicts that occur in omega networks is presented. The strategy operates by implementing the dual path property of omega networks, which allows the source and destination processors to reverse roles for some of the messages that are being transmitted. For certain message patterns, such a reversal produces a modified message pattern for which the network routes are disjoint. For a circuit switching mode in which the network links and switches are bidirectional, the disjoint set of routes for modified message pattern can be used to achieve conflict-free message transmission for the original message pattern. This strategy is investigated, and an efficient algorithm to determine whether it can be successfully applied to a given message pattern is presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The representation of multistage interconnection networks in queuing models of parallel systems

A major component of a parallel machine is its interconnection network (IN), which provides concurrent communication between the processing elements. It is common to use a multistage interconnection network (MIN) that is constructed using crossbar switches and introduces contention not only for destination addresses but also for internal links. Both types of contention are increased when nonlocal communication across a MIN becomes concentrated on a certain destination address, the hot-spot . This paper considers analytical models of asynchronous, circuit-switched INs in which partial paths are held during path building, beginning with a single crossbar and extending recursively to MINs. Since a path must be held between source and destination processors before data can be transmitted, switching networks are passive resources and queuing networks that include them do not therefore have product-form solutions. Using decomposition techniques, the flow-equivalent server (FES) that represents a bank of devices transmitting through a switching network is determined, under mild approximating assumptions. In the case of a full crossbar, the FES can be solved directly and the result can be applied recursively to model the MIN. Two cases are considered: one in which there is uniform routing and the other where there is a hot-spot at one of the output pins. Validation with respect to simulation for MINs with up to six stages (64-way switching) indicated a high degree of accuracy in the models.