Design In Terms Of Performance Research Articles

Open-Source Ethernet MAC IP Cores for FPGAs: Overview and Evaluation

Field-Programmable Gate Arrays (FPGAs) can be found in an increasing number of application domains, such as the telecom industry, the automotive electronics sector, or automation technology as well as in the area of reconfigurable computing. In recent years, it can be observed that the open-source idea which is known from the software domain for a long time also became popular in the world of hardware and FPGA design. In the era of the Internet of Things, many of today’s electronic devices implement some kind of network interface with Ethernet being known as one of the most widely used network standards. Thus, there is consequently a high demand on available Ethernet implementations for FPGA platforms. The goal of this work is to survey available open-source Ethernet MAC IP cores, evaluate existing designs in terms of performance, resource utilization, code quality, or maturity, and to present and summarize the evaluation results herein. Furthermore, advantages of commercial solutions and related publication work are discussed. To the authors’ best knowledge, this is the first publication that evaluates and compares existing open-source Ethernet MAC IP cores on a large scale. This work should help designers to select an appropriate open-source Ethernet MAC for an FPGA design and shows possible pitfalls and things to pay attention when using an open-source IP core in general. Finally, the authors would like to show that the open-source community can be also very helpful in the world of hardware in terms of design reuse or time to market.

Cooperative Roundabout Control Strategy for Connected and Autonomous Vehicles

Intersections in the urban network are potential sources of traffic flow inefficiency. Existing intersection control mostly adopts the “cross” flow pattern model, while the use of the roundabout circular flow pattern is rather sparse. Connected and autonomous vehicle (CAV) technologies can enable roundabouts to better compete with traditional intersection designs in terms of performance. This study proposes a roundabout control strategy for CAVs to enhance intersection performance while ensuring vehicle safety. A hierarchical framework is developed to decouple the flow-level performance objective and vehicle-level safety constraints to achieve computational tractability for real-time applications. It entails developing a roundabout flow control model to optimize merge-in flows, a merge-in decision model to generate vehicle passing sequence from the optimal flows, and a virtual platoon control model to achieve safe and stable vehicle operations in a circular roundabout platoon. The performance of the proposed roundabout control strategy is illustrated through numerical studies and compared to existing intersection control methods. Its stability and safety characteristics are also demonstrated.

Securing Interruptible Enclaved Execution on Small Microprocessors

Computer systems often provide hardware support for isolation mechanisms such as privilege levels, virtual memory, or enclaved execution. Over the past years, several successful software-based side-channel attacks have been developed that break, or at least significantly weaken, the isolation that these mechanisms offer. Extending a processor with new architectural or micro-architectural features brings a risk of introducing new software-based side-channel attacks. This article studies the problem of extending a processor with new features without weakening the security of the isolation mechanisms that the processor offers. Our solution is heavily based on techniques from research on programming languages. More specifically, we propose to use the programming language concept of full abstraction as a general formal criterion for the security of a processor extension. We instantiate the proposed criterion to the concrete case of extending a microprocessor that supports enclaved execution with secure interruptibility. This is a very relevant instantiation, as several recent papers have shown that interruptibility of enclaves leads to a variety of software-based side-channel attacks. We propose a design for interruptible enclaves and prove that it satisfies our security criterion. We also implement the design on an open-source enclave-enabled microprocessor and evaluate the cost of our design in terms of performance and hardware size.

Power-Efficient Heterogeneous Many-Core Design With NCFET Technology

Multi-/many-core, homogeneous or heterogeneous architectures, using the existing CMOS technology are inevitably approaching the limit of attainable power efficiency due to the fundamental limits in scaling. Negative Capacitance Field-Effect Transistor (NCFET) is rapidly emerging as an alternative technology that promises a multi-fold increase in the power efficiency of transistors, yet is compatible with the existing CMOS fabrication process. NCFET incorporates a ferroelectric (FE) layer within the transistor's gate stack, which exhibits a negative capacitance effect amplifying the internal voltage. NCFET has been in detail studied in both physics and devices/circuits communities where its superiority has been demonstrated in semiconductor measurements. However, the full promise of NCFET remains unmodeled and unquantified unless the research is further continued to the microarchitecture and system levels. This article, for the first time, explores system- and application-level benefits of NCFET-based multi-/many-core designs in terms of performance and power-efficiency compared to state-of-the-art FinFET-based designs. This exploration is done first through analytical modeling in which we extend Amdahl's law for NCFET multi-/many-cores, and then through quantitative modeling. The latter is achieved through RTL- and system-level simulations of NCFET-based multi-cores. The analytical modeling shows that a novel type of technology-based heterogeneity in which cores with the same microarchitecture but different FE thickness are combined is highly beneficial. Our exploration shows that this novel heterogeneity increases the power-efficiency by up to 3.5× over homogeneous systems and even achieves 8.3% better performance and 20% higher power-efficiency than conventional heterogeneity in the microarchitecture without having to cope with the complexity of managing different microarchitectures.

Narrowband aperture coupled waveguide to microstrip transition for space applications

Background/Objectives: To design, analyze and fabricate aperture coupled waveguide to microstrip transition for Ka-Band where energy is coupled through slot in ground plane and a metal patch placed over the substrate. Methods: Impedance matching approach has been adopted for transition design. Microstrip line is inserted into the waveguide through aperture acting as a probe. Followed by inductive line and transformer line for impedance translation between waveguide and microstrip line. Waveguide transition has been designed using Ansoft High Frequency Structure Simulator (HFSS) full-wave EM simulator. Findings: Designed transition shows return loss performance better than 15 dB and insertion loss better than 0.5 dB for back to back configuration over a frequency band of 34 – 36 GHz. Transition is fabricated on RT5580 Duroid substrate (2r= 2:2) with substrate thickness 0.254 mm. Measured results show return loss better than 25 dB and insertion loss less than 1 dB over a frequency band of 34-36 GHz. Table 2 shows comparison of present design with previously reported designs in terms of performance. Novelty/Applications: Comparison of the presented transition shows superior performance to previously reported transition designs in terms of transition bandwidth and insertion loss. Aperture coupled transitions can be widely used for space applications where hermetic sealing is required and it saves extra effort for sealing. Certain RF circuit applications require narrowband waveguide transitions to attain required performance, in this case aperture coupled transition can be a good option and its integration with RF circuits is also easy. Fabricated transition design results show good agreement with simulated results so it can be concluded that design is tolerant to fabrication errors. Transition has been fabricated using standard PCB process so production of such transition can be done easily without requirement of any special facility for fabrication. Keywords: Aperture coupled transition; waveguide; microstrip; kaBand;hermetically sealed

Post Occupancy Evaluation in the Senate Room, Faculty of Engineering, Hasanuddin University, Gowa

In higher education institutions, an effective and efficient communication is an important competitive advantage. Most of the communication is carried out in various meeting room environments. In terms of creating the right space for meetings, flexibility, easy use, and supporting university productivity, meeting rooms must be specially designed according to the architectural standard of space requirements. The Senate Room in the Faculty of Engineering, of Hasanuddin University, is one of the many rooms that are designed especially for meeting activities within the faculty. It is located on the 2nd floor of the Center of Technology (CoT) Building, with a capacity of 64 seats, and an area of 180 m2. This room is arranged in a two-way theater or proscenium type, with lined tables and flat floors. This study aims to: 1) Identify the characteristics of the elements that shape and fill the room; 2) Analyze the effect of technical space planning on the functional aspects of users, and 3) Evaluate spatial design performance in terms of functional aspects. The research method used is the Post Occupancy Evaluation with qualitative data analysis. The population in this study is the users of the room as the subjects 0f space as the subject of research and the Senate Room of Engineering Faculty as the object of research. The results showed a discrepancy between the standards and needs of users both functional and technical aspects. The results of this study are expected to contribute practical insights to architectural design, specifically related to the creation of meeting room interiors.

AHEAD: Automatic Holistic Energy-Aware Design Methodology for MLP Neural Network Hardware Generation in Proactive BMI Edge Devices

The prediction of a high-level cognitive function based on a proactive brain–machine interface (BMI) control edge device is an emerging technology for improving the quality of life for disabled people. However, maintaining the stability of multiunit neural recordings is made difficult by the nonstationary nature of neurons and can affect the overall performance of proactive BMI control. Thus, it requires regular recalibration to retrain a neural network decoder for proactive control. However, retraining may lead to changes in the network parameters, such as the network topology. In terms of the hardware implementation of the neural decoder for real-time and low-power processing, it takes time to modify or redesign the hardware accelerator. Consequently, handling the engineering change of the low-power hardware design requires substantial human resources and time. To address this design challenge, this work proposes AHEAD: an automatic holistic energy-aware design methodology for multilayer perceptron (MLP) neural network hardware generation in proactive BMI edge devices. By taking a holistic analysis of the proactive BMI design flow, the approach makes judicious use of the intelligent bit-width identification (BWID) and configurable hardware generation, which autonomously integrate to generate the low-power hardware decoder. The proposed AHEAD methodology begins with the trained MLP parameters and golden datasets and produces an efficient hardware design in terms of performance, power, and area (PPA) with the least loss of accuracy. The results show that the proposed methodology is up to a 4X faster in performance, 3X lower in terms of power consumption, and achieves a 5X reduction in area resources, with exact accuracy, compared to floating-point and half-floating-point design on a field-programmable gate array (FPGA), which makes it a promising design methodology for proactive BMI edge devices.

A real-time FPGA accelerated stream processing for hyperspectral image classification

Realizing real-time classification of hyperspectral imagery has attracted researchers across various scientific and engineering disciplines. Several time-critical applications of high-resolution hyperspectral imaging require analysis of hyperspectral imagery with minimal turnaround time. In this regard, field-programmable gate arrays (FPGAs) provide cost-effective performance over the other high-performance reconfigurable computing systems. Developing such efficient systems poses several technical challenges such as designing and validating the FPGA architecture. A rapid prototyping approach offers several benefits in designing and developing FPGA architectures. This paper proposes a rapid prototyping method for the design and implementation of a multi-class support vector machine (MSVM) algorithm for real-time hyperspectral imagery classification using a low-cost FPGA system. We have evaluated design performance in terms of overall accuracy, resource utilization as well as timing requirements using four different datasets containing airborne, drone, and ground-based hyperspectral imagery. Experimental results show that the proposed FPGA design performs classification under strict real-time constraints.

Metamodel-based robust collaborative optimization for the suspension parameters of rail vehicles

ABSTRACTThis work deals with multi-objective optimization for the suspension parameters of railcars and proposes an optimization strategy combining the collaborative optimization method and the metamodel method to optimize the suspension parameters of railcars. In this strategy, the system-level optimization and subsystem-level optimization problems are efficiently calculated by the collaborative optimization method, and the metamodel replaces the actual model in the subsystem-level to improve the convergence and robustness of the optimization algorithm. Finally, an optimal combination of suspension parameters is determined by the effective implementation of the proposed optimization method, and compared with the original design in terms of performance and robustness. Here, the lateral running stability and vertical running smoothness of railcars were increased by 10.96% and 10.1%, respectively, and the derailment coefficient and the reduction ratio of wheel weight of railcars were increased by 6.14% and 6.36%, respectively. The optimization results show that the dynamic performance of railcars is improved remarkably with the robust collaborative optimization of the suspension parameters, and the reliability and effectiveness of the proposed robust collaborative optimization method for the suspension parameters' optimization of the railcars have also been verified.Abbreviation: SBD: simulation-based design; DOF: degree of freedom; RCO: robust collaborative optimization

Large direct drive generators: the induction machine as an alternative to permanent magnet machines

Design of direct drive power take off in renewable energy generators tends to focus on force density, naturally leading to the use of relatively expensive permanent magnet machines. Elsewhere in the industrial landscape, induction machines traditionally rule as they are low cost and robust. In this study, the design of a generator for use in an open centred tidal turbine is presented as a case study to directly compare induction and permanent magnet machines. Mechanical constraints in the turbine design enforce a large magnetic gap in the generator, which inherently limits the power density and power factor. A comparison between the permanent magnet design and the induction design in terms of performance and economy has been presented.

Hardware MPI message matching: Insights into MPI matching behavior to inform design

SummaryThis paper explores key differences of MPI match lists for several important United States Department of Energy (DOE) applications and proxy applications. This understanding is critical in determining the most promising hardware matching design for any given high‐speed network. The results of MPI match list studies for the major open‐source MPI implementations, MPICH and Open MPI, are presented, and we modify an MPI simulator, LogGOPSim, to provide match list statistics. These results are discussed in the context of several different potential design approaches to MPI matching–capable hardware. The data illustrate the requirements for different hardware designs in terms of performance and memory capacity. This paper's contributions are the collection and analysis of data to help inform hardware designers of common MPI requirements and highlight the difficulties in determining these requirements by only examining a single MPI implementation.

48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-32 and Radix-23 Design Approaches

In this paper, we propose a reconfigurable (RC) fast Fourier transform (FFT) design in a systematic design scheme. The RC design bricks are mainly proposed to arbitrarily concatenate to support FFT-point required. Meanwhile, we show three developed design techniques, including six-type RC processing element, systematic first-in first-out reuse arrangement, and section-based twiddle factor generator to elaborate our FFT design. In a design/implementation example, it can support up to 2187 FFT-point manipulation and 48 RC modes. It also supports 32 operating modes defined in 3GPP-LTE standard. In application-specified integrated circuit implementation with TSMC 90-nm CMOS technology, our design work occupies a core area of 1.664 mm2 and consumes 35.2 mW under maximal clock frequency of 188.67 MHz. This paper also has outstanding design performance in terms of speed-area ratio and power-frequency ratio for comparison reference.

A Real-Time FPGA-Based Accelerator for ECG Analysis and Diagnosis Using Association-Rule Mining

Telemedicine provides health care services at a distance using information and communication technologies, which intends to be a solution to the challenges faced by current health care systems with growing numbers of population, increased demands from patients, and shortages in human resources. Recent advances in telemedicine, especially in wearable electrocardiogram (ECG) monitors, call for more intelligent and efficient automatic ECG analysis and diagnostic systems. We present a streaming architecture implemented on Field-Programmable Gate Arrays (FPGAs) to accelerate real-time ECG signal analysis and diagnosis in a pipelining and parallel way. Association-rule mining is employed to generate early diagnostic results by matching features of ECG with generated association rules. To improve performance of the processing, we propose a hardware-oriented data-mining algorithm named Bit_Q_Apriori . The corresponding hardware implementation indicates a good scalability and outperforms other hardware designs in terms of performance, throughput, and hardware cost.

Optimum design methodologies for pile foundations in London

Given the importance of pile foundations in geotechnical engineering for supporting high-significance structures such as bridges, high-rise buildings, power plant stations, offshore platforms and museums, it becomes a necessity to find the best pile foundation design in terms of performance and economy. The number of piles required might exceed several hundreds or even thousands while the pile foundation cost might exceed 20% of the construction cost of the superstructure. In this work the problem of finding optimized designs of pile foundations is examined and is performed in accordance to two design code recommendations, namely Eurocode 7 and DIN 4014. The proposed structural optimization procedure is implemented in two real-world cases both located in London, UK in order to assess the efficiency of the proposed design formulation.

A theoretical model for the electrical conductivity of core–shell nano-composite electrode of SOFC

Abstract A nano-composite electrode with a core–shell structure is superior to the traditional design in terms of performance and durability. But the theory for the electrical conductivities influenced by the core–shell structure is lacking, hindering its theoretical analysis and modeling activity. Combining the physical picture of the core–shell structure and the percolation based conductivity theory, explicit expressions for the ionic and electronic conductivities of the composite electrode are derived. The new model reveals the relationship between the ionic and electronic conductivities of the electrode and its compositions. Numerical results on the percolating threshold, electronic conductivities and I–V curves for the Ni-coated YSZ anode are shown to be in good agreement with the experimental data. The proposed conductivity model may be used for in-depth analysis and design optimization of the core–shell electrode.

Integrated phase II/III clinical trials in oncology: A case study

Integrated phase II/III trial designs implement the phase II and phase III aspects of oncology studies into a single trial. Despite a body of literature discussing the merits of integrated phase II/III clinical trial designs within the past two decades, implementation of this design has been limited in oncology studies. We provide a brief discussion of the potential advantages and disadvantages of integrated phase II/III clinical trial designs in oncology and provide an example of the operating characteristics of a Radiation Therapy Oncology Group (RTOG) trial. We review the differences among proposed integrated phase II/III designs. Then, we illustrate the use of the design in a brain tumor trial to be conducted by the RTOG and examine the impact of association between endpoints on design performance in terms of type I error, power, study duration, and expected sample size. Although integrated phase II/III designs should not be used in all situations, under appropriate conditions, significant gains can be achieved when using integrated phase II/III designs, including smaller sample size, time and resources savings, and shorter study duration. Data submission without delay and sufficient evaluation of intermediate endpoints are assumed. Although there are potential benefits in using phase II/III designs, there also may be disadvantages. We recommend running design simulations incorporating theoretical and practical issues before implementing an integrated phase II/III design.

A new methodology for evaluating sustainable product design performance with two-stage network data envelopment analysis

Sustainable product design has been considered as one of the most important practices for achieving sustainability. To improve the environmental performances of a product through product design, however, a firm often needs to deal with some difficult technical trade-offs between traditional and environmental attributes which require new design concepts and engineering specifications. In this paper, we propose a novel use of the two-stage network Data Envelopment Analysis (DEA) to evaluate sustainable product design performances. We conceptualize “design efficiency” as a key measurement of design performance in terms of how well multiple product specifications and attributes are combined in a product design that leads to lower environmental impacts or better environmental performances. A two-stage network DEA model is developed for sustainable design performance evaluation with an “industrial design module” and a “bio design module.” To demonstrate the applications of our DEA-based methodology, we use data of key engineering specifications, product attributes, and emissions performances in the vehicle emissions testing database published by the US EPA to evaluate the sustainable design performances of different automobile manufacturers. Our test results show that sustainable design does not need to mean compromise between traditional and environmental attributes. Through addressing the interrelatedness of subsystems in product design, a firm can find the most efficient way to combine product specifications and attributes which leads to lower environmental impacts or better environmental performances. This paper contributes to the existing literature by developing a new research framework for evaluating sustainable design performances as well as by proposing an innovative application of the two-stage network DEA for finding the most eco-efficient way to achieve better environmental performances through product design.

Precision-Aware Self-Quantizing Hardware Architectures for the Discrete Wavelet Transform

This paper presents designs for both bit-parallel (BP) and digit-serial (DS) precision-optimized implementations of the discrete wavelet transform (DWT), with specific consideration given to the impact of depth (the number of levels of DWT) on the overall computational accuracy. These methods thus allow customizing the precision of a multilevel DWT to a given error tolerance requirement and ensuring an energy-minimal implementation, which increases the applicability of DWT-based algorithms such as JPEG 2000 to energy-constrained platforms and environments. Additionally, quantization of DWT coefficients to a specific target step size is performed as an inherent part of the DWT computation, thereby eliminating the need to have a separate downstream quantization step in applications such as JPEG 2000. Experimental measurements of design performance in terms of area, speed, and power for 90-nm complementary metal-oxide-semiconductor implementation are presented. Results indicate that while BP designs exhibit inherent speed advantages, DS designs require significantly fewer hardware resources with increasing precision and DWT level. A four-level DWT with medium precision, for example, while the BP design is four times faster than the digital-serial design, occupies twice the area. In addition to the BP and DS designs, a novel flexible DWT processor is presented, which supports run-time configurable DWT parameters.

Design of high performance multimedia software for a mobile device with hardware accelerators

This paper describes the design of multimedia software for a mobile device consisting of software and hardware decoders and accelerators for achieving the best video performance. The hardware system of the mobile device consists of multi format codec subsystem and color space converter. The multi format codec (MFC) supports the encoding and decoding of video/image data in five different formats. The multimedia software is designed so that it makes use of the hardware accelerators in the most efficient way. In the case of video formats that are not supported by the MFC, the multimedia application makes use of software video decoders. The paper gives an analysis of several design configurations and brings out the best design in terms of performance and processor usage for displaying video on mobile devices. An experimental analysis and results is given that demonstrates the efficiency and usefulness of the design.

Investigating the effects of fine-grain three-dimensional integration on microarchitecture design

In this article we propose techniques that enable efficient exploration of the 3D design space, where each logical block can span more than one silicon layer. Fine-grain 3D integration provides reduced intrablock wire delay as well as improved power consumption. However, the corresponding power and performance advantage is usually underutilized, since various implementations of multilayer blocks require novel physical design and microarchitecture infrastructure to explore 3D microarchitecture design space. We develop a cubic packing engine which can simultaneously optimize physical and architectural design for efficient vertical integration. This technique selects the individual unit designs from a set of single-layer or multilayer implementations to get the best microarchitectural design in terms of performance, temperature, or both. Our experimental results using a design driver of a high-performance superscalar processor show a 36% performance improvement over traditional 2D for 2--4 layers and 14% over 3D with single-layer unit implementations. Since thermal characteristics of 3D integrated circuits are among the main challenges, thermal-aware floorplanning and thermal via insertion techniques are employed to keep the peak temperatures below threshold.