Design-time Techniques Research Articles

Responsible composition and optimization of integration processes under correctness preserving guarantees

Enterprise Application Integration deals with the problem of connecting heterogeneous applications, and is the centerpiece of current on-premise, cloud and device integration scenarios. For integration scenarios, structurally correct composition of patterns into processes and improvements of integration processes are crucial. In order to achieve this, we formalize compositions of integration patterns based on their characteristics, and describe optimization strategies that help to reduce the model complexity, and improve the process execution efficiency using design time techniques. Using the formalism of timed DB-nets – a refinement of Petri nets – we model integration logic features such as control- and data flow, transactional data storage, compensation and exception handling, and time aspects that are present in reoccurring solutions as separate integration patterns. We then propose a realization of optimization strategies using graph rewriting, and prove that the optimizations we consider preserve both structural and functional correctness. We evaluate the improvements on a real-world catalog of pattern compositions, containing over 900 integration processes, and illustrate the correctness properties in case studies based on two of these processes.

Towards designing a green data center farm for Internet services: Iran’s case study

Energy consumption has become a critical design factor in today's data centers. In recent years, extensive research has been done to address power---performance trade-off in data centers considering both IT equipments and cooling infrastructures (e.g., thermal-aware task scheduling, server consolidation, load balancing and geographical load balancing to name a few). This paper introduces a design-time technique that targets energy-efficient design of a green data center farm in Iran. Workload predictions, geographical maps of wind speed and solar radiation, data center and renewable resources configurations are used as a priori to design an energy-efficient data center farm for Internet services. The proposed problem is mathematically formulated as a nonlinear optimization problem and is effectively solved using a coordinate descent-based method. We also show that with some minor modification, our proposed technique can be applied at run-time for the purpose of change management. The experimental results show that the proposed method can lead to 11.6 % cost saving on average over conventional approaches.

Lifetime Reliability Enhancement of Microprocessors

Ensuring lifetime reliability of microprocessors has become more critical. Continuous scaling and increasing temperatures due to growing power density are threatening lifetime reliability. Negative bias temperature instability (NBTI) has been known for decades, but its impact has been insignificant compared to other factors. Aggressive scaling, however, makes NBTI the most serious threat to chip lifetime reliability in today's and future process technologies. The delay of microprocessors gradually increases as time goes by, due to stress and recovery phases. The delay eventually becomes higher than the value required to meet design constraints, which results in failed systems. In this article, the mechanism of NBTI and its effects on lifetime reliability are presented, then various techniques to mitigate NBTI degradation on microprocessors are introduced. The mitigation can be addressed at either the circuit level or architectural level. Circuit-level techniques include design-time techniques such as transistor sizing and NBTI-aware synthesis. Forward body biasing, and adaptive voltage scaling are adaptive techniques that can mitigate NBTI degradation at the circuit level by controlling the threshold voltage or supply voltage to hide the lengthened delay caused by NBTI degradation. Reliability has been regarded as something to be addressed by chip manufacturers. However, there are recent attempts to bring lifetime reliability problems to the architectural level. Architectural techniques can reduce the cost added by circuit-level techniques, which are based on the worst-case degradation estimation. Traditional low-power and thermal management techniques can be successfully extended to deal with reliability problems since aging is dependent on power consumption and temperature. Self-repair is another option to enhance the lifetime of microprocessors using either core-level or lower-level redundancy. With a growing thermal crisis and constant scaling, lifetime reliability requires more intensive research in conjunction with other design issues.

Skew Management of NBTI Impacted Gated Clock Trees

Negative bias temperature instability (NBTI) has emerged as the dominant failure mechanism for PMOS devices in nanometer integrated circuit (IC) designs, thus limiting their lifetime. There are several existing research works that mitigate impact of NBTI on gate delay and reliability. However, its impact on one of the most important components of modern IC design-the clock tree-has not been researched enough. Clock gating impacts the extent of NBTI-induced V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> degradation of clock buffers leading to nonuniform NBTI degradation and, thus, increased clock skew. In this paper, we propose a practical design-time technique of modifying the clock gating implementation by selecting NAND or NOR gate as output stage of integrated clock gating cells with the objective of minimizing NBTI-induced clock skew. This selection intelligently modulates the signal probability and delay equations of clock signal paths with no extra hardware penalty. We formulate the skew minimization problem as an integer linear program which determines the optimal NAND or NOR assignment of clock gating buffer. Experimental results demonstrate the effectiveness of our method as the NBTI-induced clock skew is reduced by more than 74% compared to the traditional method. The impact of voltage and temperature variation on the proposed technique was analyzed and we observed reduced but still significant reduction in clock skew under variation as compared to the traditional clock gating technique.

Design time, run time, and artificial intelligence techniques for mobility of user interface

Abstract Advancement in technology provides opportunities to user as well as challenges for application development organization. User interfaces which were design for specific device tend to be developed for various devices. Users are busy people, when they move among different context would like to move application with them. The current trend of users demanding mobile graphic user interface to support their daily life and work has led to a new generation of techniques. Design time technique provides better usability as compare to run time technique. On the other hand artificial intelligence technique like agent provides better flexibility and usability as compare to others. In this paper we have compared these techniques in the context of mobility of user interface.