Design Of Switched-capacitor Filters Research Articles

Switched-capacitor decimation filter design using time-multiplexing and polyphase decomposition of transfer functions with low denominator orders

A new switched-capacitor decimation filter design technique is presented. Based on a combination of the polyphase decomposition of IIR low-pass transfer functions having small denominator order and time-multiplexed operational transconductance amplifiers, the filter presents very low sensitivity to transfer function coefficients. It suits analog front-end systems by providing signal conditioning and relaxing the filtering requirements in converting between continuous-time and discrete-time signals. A prototype decimation filter has been designed and fabricated in a standard CMOS process to verify the proposed approach. In fully differential design, the filter has a die area of 2.8mm2, dissipates 67.2mW out of a 5V power supply and achieves a dynamic range of 58dB at 1% THD. Experimental measurements are found in close agreement with theory.

An approximation algorithm to improve capacitance matching in the design of SC filters

A critical issue in the design of switched-capacitor (SC) filters is the capacitance matching, because the filter coefficients depend on capacitance ratios. The most successful design method to achieve an accurate capacitance matching employs a parallel arrangement of identical unit capacitors to implement each filter capacitor. However, this procedure can be directly applied only if the filter coefficients can be written as rational numbers, since each capacitor is implemented as an integer number of unit capacitors in parallel. This paper presents a systematic procedure, with low computational effort, to approximate the filter coefficients by integer ratios causing acceptable errors in the filter frequency response, whereas keeping the total number of unit capacitors small, in order to save die area. This procedure was applied in the design of a sixth-order SC band-pass filter, which has been fabricated in a 0.35 μm CMOS technology. The fabricated filter occupies an area of 0.913 mm2, exhibits low sensitivity to fabrication process deviations and has an output dynamic range of 79.2 dB.

Design of a Low-Voltage High-Speed Switched-Capacitor Filters Using Improved Auto Zeroed Integrator

Design of a Low-Voltage High-Speed Switched-Capacitor Filters Using Improved Auto Zeroed Integrator

Integrated CMOS GSM baseband channel selecting filters realized using switched capacitor finite impulse response technique

A problem of the design and optimization of analog channel selecting filters, which are needed in wireless communication systems, is considered and evaluated in this paper on an example of the baseband GSM (global system for mobile telephony) channel filter. Two versions of this filter, both designed by the authors using switched-capacitor finite impulse response (SC FIR) technique, are presented and compared to each other as well as to other concurrent designs. In order to fully and plausibly compare the both filter versions (the newer and the elder one), the authors decided to design and fabricate both filters using the same technology, i.e., the technology of the elder filter version, which is the two metal, two poly CYE CMOS 0.8 μm process. The conclusions, which have been drawn, are, however, general and to a large extent technology independent. Although both presented filters are switched-capacitor (SC) finite impulse response (FIR) systems [Dąbrowski A, Cetnarowicz D, Długosz R, Pawłowski P. Design and optimisation of integrated CMOS FIR SC channel filter for a GSM Receiver, European Conference on Circuit Theory and Design, Helsinki, 28–31 August 2001. p I.265; Długosz R, Dąbrowski A, Pawłowski P. Design and measurement results of the GSM SC FIR channel filter realized in CMOS 0.8 μm technology. In: 9th international conference mixed design of integrated circuits and systems, 2002. p. 607–12] they essentially differ to each other as they are based on two quite different SC FIR delay line structures. In the first filter version Gillingham delay elements [Gillingham P. Stray-free switched-capacitor unit delay circuit. Electron lett 1984;20(7):308–10] are used, while in the second version even and odd delay elements [Dąbrowski A. Multirate and multiphase switched-capacitors circuits, London: Chapman & Hall; 1997; Dąbrowski A, Menzi U, Moschytz GS. Design of switched-capacitor FIR filters with application to a low-power MFSK receiver. IEE Proceedings-G 1992;139(4):450] are alternately connected to form the delay line. In this way an interesting comparison of these two SC delay line concepts has been possible. It should also be stressed that the frequency responses of both presented filters have been designed using the same technique, i.e., the Kaiser window of order N = 31. The upper frequency is in both cases equal to 500 kHz and the frequency of the controlling clock generator is equal to 1 MHz. The filter with Gillingham delay elements dissipates 30 mW with the 3 V supply voltage and occupies 2.2 mm 2. On the contrary, the even–odd SC FIR filter dissipates 18 mW only with the 3 V supply voltage and occupies 2.4 mm 2. Moreover, the newer filter version has the stopband attenuation greater by about 10 dB than the previous version.

Exploiting the high-frequency performance of low-voltage low-power SC filters

This paper investigates the design of low-voltage low-power switched-capacitor (SC) filters for high-frequency applications by using the clock-booster approach. In particular, our proposed SC filter architecture uses single-ended double-sampling integrator cells based on low-voltage operational transconductance amplifiers which take advantage of dynamic biasing and the clock-booster technique to drive the switch transistors. To validate its high-frequency capability, two low-pass elliptic SC filters respectively with a corner frequency of 6 and 8-MHz, were designed in a 0.35-/spl mu/m CMOS process. Both are suitable for telecom applications and can operate with a power supply as low as 1.5 V, while dissipating 11 mW. Measurements showed that for an output amplitude of 1 V/sub pp/, their total harmonic distortions were maintained well below -40 dB in their bandwidths. Comparisons with other SC filter implementations in the literature, which highlight the quality of our implementation are also provided.

Corrections to "Improved structures for programmable filters: application in a switched-capacitor adaptive filter design"

Corrections to "Improved structures for programmable filters: application in a switched-capacitor adaptive filter design"

Improved structures for programmable filters: application in a switched-capacitor adaptive filter design

In designing switched-capacitor (SC) filters for high-frequency operation, there is a tradeoff to be made between the gain and the speed of the operational amplifiers (op amps). Taking into account this fact, we present in this paper new structures (an SC integrator and an SC gain stage) which relax the constraint requirements on the op amp while achieving improved performance accuracy. These structures use the double-sampled technique, which increases by a factor of two the maximum speed of operation and correctly operate even with low dc-gain op amps. In order to effectively use all features (low sensitivity to op-amp imperfections) of these SC building blocks in the implementation of an adaptive filter, we also describe an offset-cancelled tunable SC gain stage based on four-quadrant analog multiplier cells. Numerical results are reported to confirm the viability of the proposed design method, and techniques to further improve the adaptive filter electrical characteristics are discussed.

Design and Analytical Study of Strays-Insensitive Switched-Capacitor Filters

Use of analog circuit elements in active networks have become very common and the demand for their miniaturization is increasing day by day. Though several methods are available for the miniaturization of these elements through large scale integration on single chips, the performance is not very satisfactory in low-frequency applications, due to the presence of parasitic capacitance that is comparable to the capacitance of active elements. As a result, the desired response gets deviated and also noise is involved. In this paper, an attempt has been made to devise methods for the elimination or reduction of the influence of these parasitic capacitances on filter circuits.

Design and analysis of bilinear digital ladder filters

Methods for designing bilinear switched-capacitor (SC) ladder filters are well known. However, they cannot be directly extended to digital filters because of the delay-free loops allowed in SC filters. In the present paper, design methods for low-sensitive bilinearly transformed voltage-current ladder filters are developed. The matrix approach for SC filter design is extended to digital filters, and the delay-free loops are eliminated. Design equations for general order low-pass, high-pass, bandpass, bandstop, and allpass filters are obtained in a simple closed form. The design procedure gives a canonical number of delays and a number of distinct multipliers equal to the number of reactive elements in the prototype. A number of test filters are analyzed with respect to magnitude sensitivity, magnitude response with respect to coefficient quantization, occurrence of limit cycles, stability, quantization noise levels, and structural complexity. The results are compared to wave digital filters (WDF), and cascade-form filters. It is found that bilinear digital ladder filters (BDLF) in most cases perform better than WDFs, while they at the same time have a simpler structure.

Switched-capacitor filter design using the composite discrete integrator

This paper describes the design of switched-capacitor (SC) filters by the use of a discrete integrator called the composite discrete integrator (CDI). Despite the fact that the CDI is more complicated than well-known integrators such as the bilinear discrete integrator (BDI) and the lossless discrete integrator (LDI), it offers high frequency advantages by minimizing discrete integrator errors. Cascade, inverse-follow-the-leader-feedback (IFLF), and ladder filter design techniques are presented. Simulation results of the filter examples are also given.

Systematic method for design of switched-capacitor filters

A method is proposed for the design of switched-capacitor filters (SCFs) from analogue RLC filters (ARF) via the linear transformation (LT) and the equivalent voltage-controlled source transformation (EVCST). Seven basic building blocks are described for the design of any general SCF. The method is especially well suited for the design of bandpass and lowpass SCFs. An example is given to illustrate the efficiency of the technique.

Theory and design of LDI lattice digital and switched-capacitor filters

The paper presents a new method for the exact design and synthesis of lossless discrete-integrator (LDI) lattice digital and switched-capacitor (SC) filters. In the proposed design method, the entire digital and SC filter synthesis is performed directly in the discrete-time z-domain without any recourse to the concept of a continuous-time analogue prototype reference filter. Two LDI lattic e digital filter structures are proposed, one of which employs a Foster-type and the other a Cauer-type (leapfrog) configuration. Both of these structures require at most n+1 digital multipliers and n+1 unit delays, where n represents the order of the transfer function to be realised. Similarly, the corresponding LDI lattice SC filters require at most n+2 operational amplifiers (single- or double-ended). A practical example is given to illustrate the design method and to compare the hardware requirement and the magnitude-frequency response sensitivity in the passband of the LDI lattice digital and SC filters with those of the corresponding bilinear LDI ladder digital and SC filters. It is shown that the proposed lattice filters exhibit superior sensitivity features despite their low hardware requirements.

Design of switched-capacitor FIR filters with application to a low-power MFSK receiver

Finite impulse response (FIR) switched-capacitor (SC) filters for minimum frequency-shift keying (MFSK) demodulation techniques have been developed and are discussed. The proposed filters comprise combinations of the following building blocks: sample-and-hold circuits, even-odd delay circuits, Gillingham delay circuits, recharge memory elements, Lee-Martin summer circuits, recharge summer circuits, and rotator switches. These are described in the paper. Furthermore, composite SC filter structures are derived using a morphological approach. The FIR SC filter structures are compared and evaluated with respect to the required chip area when implemented in 3 μm CMOS technology, and, by computer simulation, with regard to bit error probability when used in an MFSK receiver. It is shown that the receiver performance is independent of the FIR filter structure used. Furthermore, using the FIR filters, and for a given bit error probability, the required signal-to-noise ratio (SNR) is actually 3 dB lower than for a typical commercial MFSK receiver (e.g. an MB87002).

Design of stable active-RC and switched-capacitor filters having variable magnitude characteristics using a unified approach

In this paper, a unified approach is presented which will enable one to design both analog and switched-capacitor filters having variable characteristics. The common features for both the designs are: (i) the same signal-flow graph representation is possible; and (ii) the range of the variable to ensure stability is determined in a similar fashion. Only the actual implementations are different in both cases.

Two-dimensional switched capacitor filter design system for real-time image processing

The author presents a new method of switched capacitor (SC) network design for two-dimensional real-time filtering. A model of such a network is presented with a computer design system for 2-D SC filters. This system uses a novel compact matrix description of a 2-D network that is fast and efficient. The problem of 2-D filter design is reduced to the problem of 1-D multiport SC network synthesis. This SC network is obtained with the use of a lossless nonreciprocal prototype circuit. A 2-D high-emphasis filter illustrates the operation of this system. Such a filter can be realized as a single CMOS chip and, in comparison with digital realization, a considerable reduction in cost and power consumption can be achieved.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design of switched-capacitor and wave digital filters with linear phase and high amplitude selectivity

A design technique, and the associated algorithm, are presented for selective linear-phase low-pass and high-pass sampled data filters. The resulting filter transfer functions are particularly suitable for realization as leap-frog lossless discrete integrator (LDI) switched-capacitor structures and also in wave digital form. Due to the specific form of the transfer function, the filters generally have no lumped-element counterparts. The technique leads to an optimum compromise between amplitude selectively and passband phase linearity under the restriction of a prescribed form of the transfer function, and allows the use of finite j omega -axis zeros of transmission for achieving high amplitude selectivity. The transfer functions presented are also capable of realization as distributed microwave filters, but these require the use of coupled-wire networks in the form of distributed Brune sections, if j omega -axis zeros of transmission are introduced. >

Switched-capacitor cascaded-biquad bandpass filters from MCPER functions

The multiple-critical-pole equiripple rational (MCPER) transfer functions are compared with the elliptic transfer functions in the design of bandpass switched-capacitor (SC) filters realized as a cascade of noninteracting biquads. Filters designed using the two classes of functions are investigated in terms of passband sensitivity, total capacitance, group delay, dynamic range, and noise. The results show that MCPER transfer functions allow the design of SC filters with superior performance, especially lower passband sensitivity. >

CMOS switched-current ladder filters

The design and implementation of switched-current (SI) ladder filters is described. The basic current-mode circuits, including the SI differential integrator/summer are developed. The SI integrator/summer is shown to be directly analogous to the switched-capacitor (SC) integrator/summer; thus, all the synthesis techniques developed for the design of SC filters can be used to synthesize SI filters. Signal flowgraph synthesis of SI ladder filters is presented. The nonideal characteristics of SI ladder filters that limit their accuracy are evaluated. Clock-feedthrough and device mismatch induced errors are more severe in the present SI circuit configurations than in SC circuits. A standard digital 2- mu m n-well CMOS process has been used to implement two high-order ladder filters. Simulations accurately predict the measured results of the first integrated SI filters. The area and power dissipation are comparable to those obtained with the switched-capacitor technique. >

A switched capacitor bidirectional associative memory

A bidirectional associative memory using switched-capacitor (SC) filter techniques (SCBAM) is introduced and verified experimentally. The discrete-time equation that characterizes SC filter design is shown to be applicable in recalling m stored vector pairs that can be encoded in a correlation matrix M. The elements of M (and M/sup T/) are represented by the values of the capacitor ratios used in the SCBAM. The SCBAM exhibits similar error correcting properties as the normal BAM, making it a good candidate for analog VLSI neural network implementations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

On the design of optimal switched-capacitor filters based on the use of lossy frequency-dependent negative-resistance prototype structures

The paper introduces a new relatively stray-insensitive switched-capacitor filter (SCF) based on lossy frequency-dependent negativeresistance (FDNR) structures. The filter is derived by use of the lossless discrete integrator (LDI) and the backward-difference analogue-discrete (s-z) frequency transformations. An optimisation technique is used both to eliminate the distortion of the frequency response caused by the s-z transformations, and to deal with total capacitance minimisation—an important practical problem. The importance of these filter structures include their relative economy in realisation, leading to relatively low silicon utilisation compared with most standard SCF design techniques, and their very low sensitivity to parasitic capacitances.