Design Of Signal Processing Systems Research Articles

Automated design of embedded digital signal processing systems on SOC platform

The object of the study is the procedures for automated design and analysis of digital signal processing algorithms on the SoC technology platform. The subject of the study is models, methods and procedures for designing and optimal selection of SoC components for the implementation of digital signal processing algorithms for audio spectrum. The aim of the study is to develop models and procedures for determining the possibilities of a compromise distribution of signal processing algorithm computations in the cycle of computer-aided design on the SoC technology platform in terms of performance and the feasibility of using hardware and software algorithms realization. The article solves the following tasks: consideration of the procedures for interacting the processor core with programmable logic as part of system-on-chip systems; development of procedures for computer-aided design and analysis of signal processing systems using programming languages and hardware description languages for the implementation of embedded systems. The following methods are being used: implementation of digital signal processing algorithms in the C programming language and high-level synthesis tools for realizing IP blocks, diagnostic experiment by generating test signal patterns, and analysis of the processing results at the system output. The results achieved. Based on the analysis of the procedures for the interaction of the processor core and programmable logic on the selected SoC platform, a model of the audio spectrum signal processing system is designed. The practical implementation was performed based on the Vivado/Vitis/Vitis HLS CAD tool stack. The proposed model was verified using a programmable test signal generator and analyzing the obtained characteristics of digital filters at the system output. Conclusions. The article analyzes the principles of designing embedded information processing systems implemented in system-on-chip. The principles of building and analyzing digital signal processing systems based on system-on-chip containing programmable logic and processor parts are considered. The developed methods have been tested on the algorithms of CIC and FIR filters on the technological platform of SoC FPGA of the ZYNQ-7000 family of Xilinx company.

Design of a Digital Array Signal Processing System with Full Array Element

For the application of a digital array signal processing system with a high sampling rate and large bandwidth, and considering the constraints of limited resources (performance, volume, power consumption, weight, etc.), this paper proposes a design and implementation method of broadband digital array signal processing system based on radio frequency system on a chip. The system focuses on multi-channel synchronization under a high sampling rate and multi-channel amplitude and phase calibration under large bandwidth to form an all-digital, low-power, multi-channel, high-speed, large bandwidth hardware platform suitable for broadband digital array signal processing. Through the implementation of the Multiple-Input Multiple-Output phased-array digital beamforming algorithm, the test conducted verifies that the system has superior signal processing performance of the broadband digital array.

Highly sensitive, ultra-reliable flexible piezoelectret sensor for non-contact sitting motion tracking and physiological signal monitoring

Non-contact, cost-effective, multifunctional and robust monitoring platform without mechanical wearing burden is highly desired to enhance the immersive experience for users during the long-term health management. However, most reported intelligent electronics in human life need to be adhered conformably to key human body parts for accurate signal detection, giving rising to activity interference and wearing burden in the long-term usage. Herein, a highly sensitive flexible film pressure sensor with a folded structure configuration assembled from irradiation-cross linked polypropylene (IXPP) piezoelectret film featured with piezoelectric-like dynamic electrical output attributes are reported. Such simple folded structure incorporated specially into the device design endows the piezoelectric film sensor with merits such as enhanced sensitivity, high signal-to-noise ratio and excellent anti-interference capacity. Consequently, the sensor can achieve a linear pressure sensitivity of 92 pC/kPa over a wide pressure range of 0.6–62.4 kPa, a pressure resolution of 0.98%, and fast response/recovery time of 40 ms. The flexible piezoelectric film sensors are embedded into cushions and attached to the back of chairs for application demonstrations of non-contact sensing. Remarkably, low-frequency human motion and weak physiological signal detection are achieved in a non-contact mode by a highly sensitive piezoelectric sensing principle in an all-in-one configuration, simplifying the signal processing and monitoring system design. A vital sign monitoring system based on the intelligent cushion is further developed to unlock the health status of sedentary crowd. This is the first work that ever use commercially available irradiated cross-linked polypropylene (IXPP) film to design pressure sensor and such sensors are successfully connected to the commercial “C-life” smart home ecosystem, presenting strong practicability and application prospects of such films in smart households and remote healthcare beyond the laboratory.

Design of an Electrochemical Biosensor Signal Processing System for Uric Acid Detection Platform

<p>本論文提出一個應用於尿酸檢測平台之電化學生物感測器信號處理系統設計，其主要目的是要設計一個簡易使用的尿酸檢測平台，透過pH感測試片，對於尿液檢體進行檢測，將檢測結果所回饋之電壓信號，經由所開發之信號處理系統，將測得結果以無線傳輸至手機，最後，透過手機之APP將pH值顯示出來。 在系統設計方面，我們採用EMF32微處理器晶片為控制核心，並採用超極生技公司之pH感測試片，將待量測之尿液檢體滴在試片上，而該試片會將檢測結果反應出電壓信號，透過晶片內之ADC接收後，轉變為數位訊號，再經由UART傳出訊號給藍芽模組，藍芽接收到訊號後再以無線方式傳送到手機，最後，由手機APP顯示數值即可得知尿酸之pH值，同時，這個檢測結果也會傳送到雲端資料庫中。 在系統驗證方面，我們採用pH感測試片針對不同pH標準液進行量測，將所測試結果，建立出pH值之校正曲線，並將檢測結果與商用酸鹼檢測儀之檢測結果進行比較驗證。實驗結果顯示本論文所提出之尿酸檢測平台，具有檢測速度快、操作簡便、與高準確度等特點。</p> <p> </p><p>In this paper, an electrochemical biosensor signal processing system for uric acid detection platform is proposed to detect the pH value of urine. In the proposed platform, the measured urine is dropped on a pH sensor strip, and the strip will generate a voltage value corresponding to the measured urine pH value. Then, the voltage will be transmitted to the phone in wireless after measured by the proposed signal processing system. Finally, the pH value of the measured urine will be shown on the phone and be recorded in the cloud. In the system design, the EMF32 chip is used as the control unit, the UltraE pH strip is used for urine pH measurement, the Bluetooth module is used to perform the wireless data transmission, and the phone is used to show the measured results. In the system verification, we use the UltraE pH strip to measure a set of different pH standard solution to establish a calibration curve. Based on the calibration curve, the proposed system can perform the urine pH measurement. In comparison with the results measured by the commercial acid-base detector, the proposed system has the advantages of high speed, small size, simple operation, and easy portability.</p> <p> </p>

Processing of the Quench Detection Signals for CS Model Coil of CFETR

The Center Solenoid Model Coil (CSMC) is a pre-research project of CFETR, and its task is to design and manufacture the CS superconducting model coil to gain wider experience in solving the related technical problems existing in design and construction of CFETR CS coils. The expected achievement is to charge the CSMC up to the operation current of 47.65 kA and the maximum magnetic field to 12 T with a swift rump rate of 1.5 T/s without quench. Although adequate operational margins have been taken into in the design to avoid the quenches, such events cannot be completely excluded in the life of the CSMC. In order to prevent quench from damaging the CSMC, the quench detection by voltage measurements plays an important role in the protection of the CSMC during commissioning and operation scenarios. To improve the accuracy and reliability of CSMC quench detection, an all-digital quench detection system based on FPGA has been designed for the processing of quench detection signals. This paper describes the design of the quench detection signal processing system, including the composition of quench detection units, the auxiliary compensation for further denoising, the discriminant of quench, and the safety interlock system.

Low Area and Power-Efficient FPGA Implementation of Improved AM-CSA-IIR Filter Design for the DSP Application

Digital Signal Processing (DSP) grew enormously in the past few decades and it was extensively practiced for numerous engineering applications like biomedical signal processing, radar signal processing, adaptive antenna design, intelligent control, etc. In DSP, the Finite Impulse Response (FIR) filter and Infinite Impulse Response (IIR) filter plays a vital role in the design of a complex signal processing system. Generally, The FIR filters are stable, linear in phase, with fewer finite-precision errors and easy to implement. However, most of the IIR filters are used in signal processing applications due to the less computational complexity which is compared to the FIR filters. Moreover, the IIR filter requires only fewer filter coefficients and requires only less amount storage registers. In this research, an IIR filter is implemented with Array multiplier and Carry Skip Adder (CSA) to improve hardware utilization. The IIR filter input is generated randomly which is stored in Random Access Memory (RAM). Similarly, the coefficient is generated by utilizing the Parks-McClellan algorithm where the generated value is stored in Read Only Memory (ROM). The proposed AM-CSA IIR (Array Multiplier-Carry Skip Adder Infinite Impulse Response) filter performances are evaluated in terms of filter output, Input Output Block (IOB), Look Up Table (LUT), Flip Flops (FF), slices, delay, and fractional delay. Overall the proposed design attained LUT= 115 (0.0564%), FF=40 (0.01%) and IOB= 22 (3.77%) and reduced fractional delay of about 0.0057ns.

A Brain-Inspired In-Memory Computing System for Neuronal Communication via Memristive Circuits

Brain-inspired approaches can efficiently analyze the activities of biological neural networks and solve computationally hard problems with energy efficiencies unattainable with von Neumann architectures, indicating a significant improvement in the understanding of neuronal communications and functionalities. Here, we present a brain-inspired multimodal signal processing system with organic memristor arrays that can potentially integrate the signal sensory, storage, and computation. To facilitate the multimodal signal processing system design, we used four components. First, we present a multimodal signal sensory module mainly responsible for multimodal (iconic, echoic, olfactory, muscular, and gustatory) signal collection, fusion, and storage. Second, a high-density cross-point memristive synapse array is constructed after fabrication of the albumin protein memristor to realize the dense connectivity between layers of computing, data storage, and communication. Third, considering the structure and function of the brain region, we demonstrate a general learning module for hierarchy learning, which can recognize and imagine multimodal information. Finally, the necessary peripheral circuit module (consisting of winnerless competition function circuit, analog-to-digital converter, digital-to-analog converter, pulse modulator, etc.) is designed. Notably, our system can capture massive amounts of data every second and perform in situ processing of multimodal signals. This study is expected to help achieve the deep integration of nano materials into neuromorphic computing systems and energy-efficient integrated circuits.

Ultra-fast tunable optoelectronic half adder/subtractor based on photonic crystal ring resonators covered by graphene nanoshells

This paper reports a new design of a tunable optoelectronic half adder/subtractor. Two photonic crystal (PhC) ring resonators are used to realize the proposed structure. Several silicon rods surrounded by silica rods covered with graphene nanoshells (GNSs) form every PhC ring resonator. Setting the chemical potential of GNS with an appropriate gate voltage, we can tune the PhC resonant mode as desired. The plane wave expansion technique is used to study the photonic band structure of the fundamental PC microstructure, and the finite-difference time-domain method is employed in the final design for solving Maxwell's equations to analyze the light propagation inside the structure. We systematically study the effects of physical parameters on the transmission reflection and absorption spectra. By optimizing the geometric dimensions, resonant absorption peaks can be excited at the same time for GNSs. Our numerical results also reveal the maximum time response is about 0.8 ps. The 200 µm2 area of the proposed half adder/subtractor makes it the building block of every photonic integrated circuit. Also, the design of various fast signal processing systems in optical communication networks is possible due to using tunable GNSs in PhC ring resonators. This study can introduce the use of two-dimensional materials in the design and implementation of logic circuits.

Review of Partial Discharge Signal Processing and Monitoring System using Virtual Instrument Software

Most of Partial Discharge (PD) processing systems have been developed using virtual instrument to analyse raw measured PD signal. However, some of researchers had neglected the denoising or recognition technique and only focussed on PD location estimation and vice versa This paper reviews an overview of denoising recognition techniques, denoising analysis, PD sensors, location methods and type of virtual instruments in published PD signal processing signal system. A perfect PD analysis system is more beneficial if both PD denoising and locating are applied in the system. Based on this review, the new design of PD signal processing system based on DWT denoising technique and RC sensor using LabVIEW Software for underground power cable using SCTM as PD location algorithm is proposed.

Software synthesis from dataflow schedule graphs

The dataflow-model of computation is widely used in design and implementation of signal processing systems. In dataflow-based design processes, scheduling—the assignment and coordination of computational modules across processing resources—is a critical task that affects practical measures of performance, including latency, throughput, energy consumption, and memory requirements. Dataflow schedule graphs (DSGs) provide a formal abstraction for representing schedules in dataflow-based design processes. The DSG abstraction allows designers to model a schedule as a separate dataflow graph, thereby providing a formal, abstract (platform- and language-independent) representation for the schedule. In this paper, we introduce a design methodology that is based on explicit specifications of application graphs and schedules as cooperating dataflow models. We also develop new techniques and tools for automatically synthesizing efficient implementations on multicore platforms from these coupled application and schedule models. We demonstrate the proposed methodology and synthesis techniques through a case study involving real-time detection of people and vehicles using acoustic and seismic sensors.

Guest Editorial: Special Section on the Design and Implementation of Signal Processing Systems

Guest Editorial: Special Section on the Design and Implementation of Signal Processing Systems

Nonlinear distortion of angle modulation signal in output power amplifiers

The output power amplifier is operated in nonlinear mode to increase its efficiency, at which the signal is distorted more. The goal is to analyze effects of nonlinearity on the modulating signal of angle-modulated signal distortions for single-ended and push-pull output power amplifiers with memory and without it. The amplifier characteristic ic(vBE) is preset by the cubic polynomial. The output voltage of memoryless amplifier uout(t) is found by Ohm's law. And in case with amplifier with memory, the output voltage uout(t) is found by Complex amplitude method with a Fourier series of function ic(t). The output voltage uout(t) is represented as the narrowband process with envelope of the waveform U1(t) and initial phase Ф1(t) to determine the angular modulation law Ф1(t) at the amplifier output. The function U1(t) is defined as combination of in-phase А(t) and quadrature В(t) components. The distortion estimate based on Total Harmonic Distortion (THD). The measurement of THD is defined as the ratio of the RMS amplitude of a set of higher harmonic frequencies to the RMS amplitude of the first harmonic. The spectrum of function Ф1(t) is represented a Fourier series. In single-ended memoryless amplifier and non-cutoff mode, the THD decreases as m increases and THD of modulating signal is {37.6; 18.8; 6.3%} at m {0.5; 1; 3}. In cutoff mode, the smallest THD is {15.18; 5.13%} at m {1; 3} as θ = 140o. In push-pull memoryless amplifier and θ = 90o, the THD is {22.2; 11.1; 3.7%} at m {0.5; 1; 3} which is 1.7 times less than in a single-ended amplifier without cutoff. This is due to compensation even-order harmonic of amplified signal at the output of a pushpull amplifier. In this case of memoryless amplifier, the transistor load is a parallel RLC circuit. The distortion decreases under m increases at first (up m is 1.5), but then rapidly increases (from m is 1.7). This is due to increase of the parasitic harmonics level caused by the nonlinearity of the phase-frequency characteristic of RLC circuit. The calculations show that THD of modulating signal is 3.35, 9.02 and 22.88 % at Q = 10 and m {0.5; 1; 3}, respectively. In cutoff mode, the smallest THD is at θ = 90o and it does not depend on θ at large values of m. In push-pull amplifier with memory, the THD is 2.8, 2.5 and 3.0 times less than for a singleended amplifier without cutoff at Q {2.5; 5; 10}, respectively. The results of this paper can be used for the design of signal processing systems.

Design and Simulation of Sensor Signal Processing System

In particular, the popularity of personal notebooks makes personal notebooks more rapid development, and sensor processors for cars, microwave ovens and other products are more useful, and have a great impact on the design of these products. Because of the rapid development of sensors, there are various sensors, which makes the data manual of these sensors have many different formats, so many sensor systems have their own the data use manual is different. There is also in the sensor acquisition of the signal process often mixed with noise and various interference signals. In order to solve this problem, many scientists at home and abroad have done a lot of research on this aspect. In this paper, compensation method, filtering method and noise suppression method are used to improve the signal-to-noise ratio and resolution of the sensor. And through the experimental practice, the results show that the sensor signal processing system can eliminate the noise, improve the signal-to-noise ratio and improve the resolution of the sensor, and also achieve good results in practical application.

Passive-Active Flowgraphs for Efficient Modeling and Design of Signal Processing Systems

In dataflow representations for signal processing systems, applications are represented as directed graphs in which vertices represent computations and edges correspond to buffers that store data as it passes among computations. The edges in the dataflow graph are single-input, single-output components that manage data transmission in a first-in, first-out (FIFO) fashion. In this paper, we formulate the vertices and edges into concepts called “active blocks” and “passive blocks”, respectively in the graph representation. Computation in the dataflow graph is represented as “active blocks”, while the concept of dataflow buffers is represented as “passive blocks”. Like dataflow edges, passive blocks are used to store data during the intervals between its production and consumption by actors. However, passive blocks can have multiple inputs and multiple outputs, and can incorporate operations on and rearrangements of the stored data subject to certain constraints. We define a form of flowgraph representation that is based on replacing dataflow edges with the proposed concept of passive blocks. We present a structured design methodology for utilizing this new form of signal processing flowgraph, and demonstrate its application to improving memory management efficiency, and execution time performance.

Implementation of digital and analog modulation systems using FPGA

<p><span>FPGA (Field Programmable Gate Array) based implementations of digital and analog modulation techniques play a vital rule in the design of signal processing system. The performance and flexibility provided by reconfigurable computing speeds up the development process in signal processing implementations using FPGA. Different methods for digital and analog modulation are designed in this paper by usinSg System Generator tools & Vivado. Then all designed systems are implemented successfully in an FPGA hardware via the NEXYS 4 DDR with ARTIX 7 XC7A100T. A comparison between five types of digital modulation techniques is discussed in terms of resources utilization in FPGA hardware. And also, the implementation of analog modulations in FPGA is contributed in this work. The hardware implementation shows that the number of slice LUTs in ASK modulation is 0.07% while in FSK modulation is 0.13% of the total number of slice LUTs. And also, the number of bounded IO that used for PSK modulation is 4.8% while in PM modulation is 61.4% of the total number bounded IO.</span></p>

Design and implementation of a real-time digital signal processing system using PIC24 microcontroller and wireless GUI control

In this paper, a real-time Digital Signal Processing (DSP) system is designed and implemented by using a PIC24 microcontroller circuit and a C# GUI application running on PC. The wireless communication between the PIC24 subsystem and the GUI subsystem is implemented via Bluetooth modules on the subsystems. The DSP system first digitises an input square signal of a certain frequency through an on-chip ADC of PIC24 microcontroller, then uses different FIR digital filters to extract certain harmonics of the input signal, and outputs it as a sinusoidal signal to an on-chip DAC as well as sends the sampled data and filtered data over Bluetooth to the GUI. The GUI, besides plotting the input and output wave forms, can provide a means of controlling all functionalities of the system through a developed communication protocol. The design and implementation for the proposed DSP system are successfully demonstrated by experimental results. The hardware and software co-design method can be extended to other industrial applications and used as a good paradigm of engineering education for college students.

Design and implementation of a real-time digital signal processing system using PIC24 microcontroller and wireless GUI control

In this paper, a real-time Digital Signal Processing (DSP) system is designed and implemented by using a PIC24 microcontroller circuit and a C# GUI application running on PC. The wireless communication between the PIC24 subsystem and the GUI subsystem is implemented via Bluetooth modules on the subsystems. The DSP system first digitises an input square signal of a certain frequency through an on-chip ADC of PIC24 microcontroller, then uses different FIR digital filters to extract certain harmonics of the input signal, and outputs it as a sinusoidal signal to an on-chip DAC as well as sends the sampled data and filtered data over Bluetooth to the GUI. The GUI, besides plotting the input and output wave forms, can provide a means of controlling all functionalities of the system through a developed communication protocol. The design and implementation for the proposed DSP system are successfully demonstrated by experimental results. The hardware and software co-design method can be extended to other industrial applications and used as a good paradigm of engineering education for college students.

Design and Implementation of Signal Processing System for Radio Spectrometer Based on Casper and Simulink

基于Casper硬件平台的射电望远镜数字系统正在被广泛应用.在Simulink中通过调用Casper模块可以实现复杂的数字信号设计，加快FPGA开发射电望远镜系统的效率.利用Casper模块和Simulink中Xilinx模块设计射电望远镜单元样机的数字信号处理单元，完成子带的抽取、下变频和整体频谱分析等功能.在Casper通用硬件平台ZYNQ7020上进行相关功能的仿真，验证了利用Casper模块和Xilinx模块设计基于FPGA的射电望远镜单元样机信号处理系统的可行性和高效性.

Editor’s Note: Special Issue on Design and Implementation of Signal Processing Systems

Editor’s Note: Special Issue on Design and Implementation of Signal Processing Systems

FPGA implementation of fast digital FIR and IIR filters

SummaryThe demand for digital signal processing optimized solutions grows drastically in the modern years, especially in the field of communication and modern signal processing circuits. The finite impulse response (FIR) and an infinite impulse response (IIR) filters play a crucial role in the design of any complex signal processing system. This paper exemplifies the conventional moving average (MA) FIR filters, fast MA FIR filters using look‐ahead arithmetic, the conventional IIR filters using combination of integrator and comb sections (CIC) method, and the fast IIR filters using look‐ahead arithmetic in detail. Altera EP4CE115F29C7 field‐programmable gate array (FPGA) device using Quartus II 13.1 synthesis tool has been used to implement these filters. The performance metrics like the number of Logic Elements (LEs), the performance, and the power immoderation simulation results are compared with the normal and fast MA FIR and IIR filters, respectively. The first‐order IIR conventional filter has 153.4 MHz performance shown in simulation result, the same filter with look‐ahead level 1 has 189.79 MHz performance, and the fast filter with level 2 has 199.96 MHz performance. In addition, with the MA FIR filters, an 8‐tap MA FIR filter using CIC method has 166.09 MHz performance, the same filter using look‐ahead with level 1 has 167.22 MHz performance, and the same filter using look‐ahead with level 2 has 168.56 MHz performance. The proposed FIR and IIR filter is designed efficiently in terms of speed for the application of VLSI signal processing environment.