RF Integrated Circuit Design Research Articles

Bayesian Optimization Approach for RF Circuit Synthesis via Multitask Neural Network Enhanced Gaussian Process

An RF integrated circuit design heavily relies upon experienced experts to iteratively tune the circuit parameters. A Bayesian optimization (BO) method is explored in existing works for automated analog and RF circuit synthesis. The overall performance can be further improved by constructing a model to exploit the correlation among different circuit specifications. In this article, we propose a BO approach for RF circuit synthesis via a multitask neural network enhanced Gaussian process (MTNN-GP). We present a novel multioutput GP model, in which the kernel functions of multiple outputs are constructed from a multitask neural network with shared hidden layers and task-specific layers. Therefore, the correlation between the outputs can be captured by the shared hidden layers. Our proposed MTNN-GP-based BO method is compared with several state-of-the-art BO methods on three real word RF circuits and achieves best performance. The experimental results demonstrate the effectiveness and efficiency of our proposed method.

CMOS-Compatible MESFETs for High Power RF Integrated Circuits

Metal semiconductor field effect transistors (MESFETs) have been fabricated using a 45-nm silicon-on-insulator CMOS technology available from Global Foundries. MESFETs with gate lengths of 200 nm show good manufacturability with well-controlled run-to-run variations. The DC and RF performance of devices with different drain access lengths are compared to illustrate the design trades between high breakdown voltage and high frequency operation. Two applications of the MESFETs for RF integrated circuit design are presented. The first demonstrates integrated n-channel MOSFET-MESFET cascode amplifiers that combine the enhanced voltage operation of the MESFET with the high frequency capability of the scaled MOSFET. The resulting small-signal amplifiers demonstrate cut-off frequencies of 50 GHz when operated with supply voltages of 6 V, significantly higher than the nominal 1 V breakdown voltage of the CMOS transistors. The second application demonstrates a watt-level MESFET power amplifier integrated with a CMOS current steering digital-to-analog converter (DAC). The MESFET serves as the RF output device, while the 4-bit CMOS DAC enables average power tracking. Both examples demonstrate the design flexibility enabled by the CMOS-compatible MESFETs.

Impact of Fin Width Scaling on RF/Analog Performance of Junctionless Accumulation-Mode Bulk FinFET

In this article, the RF and analog performance of junctionless accumulation-mode bulk FinFETs is analyzed by employing the variation of fin width so that it can be used as a high-efficiency RF integrated circuit design. The RF/analog performance evaluation has been carried out using the ATLAS 3D device simulator in terms of evaluation of figure-of-merits metrics such as transconductance (g m ), gate-to-source/drain capacitances (C gg ), cutoff frequency (f T ), and maximum frequency of oscillation (f max ). Apart from RF/analog performance investigation, the variation of ON-current to OFF-current ratio (I ON /I OFF ) and transconductance generation factor (g m /I ds ) have also been carried out. From this study, it is observed that smaller fin width of the device improves its performance.

General Chair's Welcome IMS2013

On behalf of the 2013 International Microwave Symposium (IMS2013) Steering Committee, it is my privilege to welcome attendees to Seattle and invite you to attend the IMS to be held the week of 2 June 2013. Colocated with IMS as part of Microwave Week are the Radio- Frequency Integrated Circuit Symposium (RFIC) (www.rfic2013.org) and the Automatic Radio-Frequency Techniques Group (ARFTG) Microwave Measurement Conference (www. arftg2013.org). RFIC brings focus to the technical accomplishments in RF circuits, systems, and devices and showcases the latest innovations in RF integrated circuit design. RFIC is held Sunday, 2 June through Tuesday, 4 June. The ARFTG Microwave Measurement Conference is a single-day event that will be held on Friday, 7 June. ARFTG is focused on the RF and microwave test and measurement community. We received over 950 papers and a large number of workshop and short course proposals. Following a rigorous review process provided by the 270 members of the Technical Paper Review Committee with 40 subcommittees, the Technical Program Committee has crafted an excellent program. Topics include circuit theory, passive components, active components, systems and applications, and emerging technologies.

Analog/RF Performance of Si Nanowire MOSFETs and the Impact of Process Variation

In this paper, the analog/RF performance of Si nanowire transistors (SNWTs) and the impact of process variation are investigated for the first time. Analog/RF figures of merit of SNWTs are studied, including transconductance efficiency gm/Id, intrinsic gain gm/gd, cutoff frequency ft , and maximum oscillation frequency fmax. The results indicate that SNWTs exhibit superior intrinsic RF scaling capability and are suitable for low-power analog/RF applications. The impact of nanowire cross-sectional shape fluctuation that is caused by process variation is studied and found to be relatively severe, and the acceptable variation tolerance for RF integrated circuit design is given

Modeling and characterization of SiGe HBT low-frequency noise figures-of-merit for RFIC applications

We present the first systematic experimental and modeling results of noise corner frequency (f/sub C/) and noise corner frequency to cutoff frequency ratio (f/sub C//f/sub T/) for SiGe heterojunction bipolar transistors (HBTs) in a commercial SiGe RF technology. The f/sub C/ and f/sub C//f/sub T/ ratio are investigated as a function of operating collector current density, SiGe profile, breakdown voltage, and transistor geometry. We demonstrate that both the f/sub C/ and f/sub C//f/sub T/ ratio can be significantly reduced by careful SiGe profile optimization. A comparison of the f/sub C/ and f/sub C//f/sub T/ ratio for high breakdown and standard breakdown voltage devices is made. Geometrical scaling data show that the SiGe HBT with A/sub E/=0.5/spl times/2.5 /spl mu/m/sup 2/ has the lowest f/sub C/ and f/sub C//f/sub T/ ratio compared to other device geometries. An f/sub C/ reduction of nearly 50% can be achieved by choosing this device as the unit cell in RF integrated-circuit design.

Noise-gain tradeoff in RF SiGe HBTs

A new analytical expression of associated gain is derived using linear noisy two-port theory, and used to explain a previous experimental observation of lower (worse) associated gain in SiGe HBTs featuring lower (better) noise. For present RF applications of SiGe HBTs operating at frequencies comparable to or smaller than f T / β , β must be increased through SiGe profile optimization to further reduce noise. This noise improvement, however, necessarily results in a degradation of associated gain, as experimentally observed. The implications of the noise-gain tradeoff on RF integrated circuit design are discussed.

An MOS transistor model for RF IC design valid in all regions of operation

This paper presents an overview of MOS transistor modeling for RF integrated circuit design. It starts with the description of a physical equivalent circuit that can easily be implemented as a SPICE subcircuit. The MOS transistor is divided into an intrinsic part, representing mainly the active part of the device, and an extrinsic part responsible for most of the parasitic elements. A complete charge-based model of the intrinsic part is presented. The main advantage of this new charge-based model is to provide a simple and coherent description of the DC, AC, nonquasi-static (NQS), and noise behavior of the intrinsic MOS that is valid in all regions of operation. It is based on the forward and reverse charges q/sub f/ and q/sub r/ defined as the mobile charge densities, evaluated at the source and at the drain. This intrinsic model also includes a new simplified NQS model that uses a bias and frequency normalization allowing one to describe the high-order frequency behavior with only two simple functions. The extrinsic model includes all the terminal access series resistances, and particularly the gate resistance, the overlap, and junction capacitances as well as a substrate network. The latter is required to account for the signal coupling occurring at RF from the drain to the source and the bulk, through the junction capacitances. The noise model is then presented, including the effect of the substrate resistances on the RF noise parameters. All the aspects of the model are validated for a 0.25-/spl mu/m CMOS process.

Design rule development for microwave flip-chip applications

This paper presents a novel experimental approach for the analysis of factors to be considered when designing a flip-chip package. It includes the design of an experiment and statistical analysis of the outputs and uses both test-structure measurements and full-wave simulation techniques in the 1-35-GHz frequency range. The most significant factors are found to be, from the most to least important, the length of the area where the device and substrate overlap (referred to as conductor overlap), the bump diameter, and the width of the coplanar-waveguide transmission-line launch. These results are valid for conductor overlaps between 300-500 /spl mu/m. For a lower value (120 /spl mu/m), the significance level of the overlap decreases and the bump height also becomes significant. Test-structure measurements in the 120-200-/spl mu/m overlap range validate this result and demonstrate the decrease in the significance level. The substrate thickness in the 10-25-mil interval is found to be statistically insignificant, therefore, it can be eliminated from further analysis. This approach provides a foundation for development of a set of design rules for RF and microwave flip-chip similar to RF integrated-circuit design rules.