Design Of Oscillator Research Articles

Toward 10-watt-level single-frequency fiber laser oscillators

High-power single-frequency laser oscillators are in great demand for some specific applications, such as quantum information and laser interferometer gravitational-wave observatories, where 10-watt or even 100-watt-level narrow-linewidth lasers with extremely low noise levels are required. In this paper, we present numerical investigations on the power scalability of single-frequency distributed Bragg reflector (DBR) ytterbium-doped phosphate fiber lasers and identify the low-quantum-defect operation approach to 10-watt single-frequency laser oscillators with the best figure of merit, defined by the ratio of the laser efficiency to the quantum defect. This research offers valuable insights for the design and development of high-power single-frequency DBR fiber laser oscillators at many other wavelengths.

Design of an X-band high-efficiency coaxial relativistic klystron oscillator packaged with permanent magnet

Design of an X-band high-efficiency coaxial relativistic klystron oscillator packaged with permanent magnet

Design and simulation of a tunable parity-time symmetric optoelectronic oscillator utilizing integrated components

Non-Hermitian photonics, relaying on parity-time (PT) symmetry, have shown promise in achieving mode selection for optical or microwave single-mode oscillation. Typically, a PT-symmetric system is constructed using two coupled loops with identical geometry. This article utilizes the PT-symmetry property to select a single frequency mode in an optoelectronic oscillator (OEO). However, traditional OEO implementations often involve discrete components, limiting widespread adoption due to factors such as size, weight, power consumption, and cost. Our aim in this paper is to leverage integrated components within the OEO loop. The proposed structure incorporates an integrated micro-ring resonator (MRR) with a high-quality factor (Q-factor) that serves both as a modulator and a resonator. Additionally, we suggest employing an adjustable integrated power splitter utilizing a micro heater to balance the gain and loss of two mutually coupled OEO loops. In this configuration, two integrated photo detectors (PD) are also utilized. In this setup, the single-frequency mode can be easily identified by simultaneously utilizing the properties of PT-symmetry and an integrated high-Q-factor resonator, obviating the need for a narrowband microwave filter. By adjusting the center frequency of the microwave photonic filter (MPF), the frequency of the generated signal can be tuned over a wide range. For instance, setting the generated frequency of the microwave signal to 11.5 GHz results in a measured phase noise of − 76.5 dBc/Hz at a 10-kHz offset frequency, with a side mode suppression ratio (SMSR) of 40 dB.

Sinusoidal oscillator parametrically forced to robust hyperchaotic states: the lumpkin case

The objective of this paper is to showcase the capability of the conventional circuit structure known as the Lumpkin oscillator, widely employed in practical applications, to operate in robust chaotic or hyperchaotic steady states. Through numerical analysis, we demonstrate that the generated signals exhibit a significant level of unpredictability and randomness, as evidenced by positive Lyapunov exponents, approximate entropy, recurrence plots, and other indicators of complex dynamics. We establish the structural stability of strange attractors through design and practical construction of a flow-equivalent fourth-order chaotic oscillator, followed by experimental measurements. The oscilloscope screenshots captured align well with the plane projections of the approximate solutions derived from the underlying mathematical models.

Compact low-repetition-rate femtosecond optical parametric oscillators enabled by Herriott cells

We report the design and characterization of a femtosecond optical parametric oscillator containing an intracavity Herriott cell. Pumped by a 49.16-MHz Yb:fiber laser, the signal wavelength could be tuned over 1440-1530 nm, with the Herriott cell containing 81% of the free-space cavity length required for synchronous operation. We also report a 12.29-MHz OPO using a sub-harmonic pumping approach, extending the Herriott cell OPO concept to low-repetition-rate cavities.

A method to design a fast chaotic oscillator using CCTA

This article introduces a novel method for designing a fast chaotic oscillator using a CCTA (Current Conveyor Transconductance Amplifier) based on Chua's circuit. The proposed method uses innovative configurations and advanced simulation techniques to overcome challenges in high-speed operation, nonlinear dynamics, and Analog Building Block (ABB) selection. The design begins with nonlinear negative resistance, essential for Chua's diode characteristics, including two negative resistances, NR1 and NR2. The circuit integrates one CCTA block, two grounded capacitors, two fixed resistors, one inductor, and one potentiometer. It is simulated using PSPICE with IC (Integrated Circuit) macro-models and 180nm CMOS (Complementary Metal Oxide Semiconductor) technology. Various chaotic waveforms and attractors are produced, validating the theoretical and mathematical predictions. By varying the resistance values (1450Ω, 1650Ω, 1800Ω, 1950Ω), the circuit exhibits different chaotic behaviors, such as large limit cycles, double-scroll attractors, Rossler-type attractors, and I-periodic attractors. FFT (Fast Fourier Transform) analysis confirms the highest dominant operating frequency of 37.5MHz. A Monte Carlo simulation with 100 runs shows maximum voltage variations in the chaotic waveforms of 5.21 % and 4.61 % across the capacitors, demonstrating robustness and reliability. This design offers significant advancements in implementing high-frequency chaotic oscillators, with potential applications in various fields requiring chaotic signal generation.•A novel design of Chua's diode and Chua's chaotic oscillator using only one CCTA block is presented in this paper.•The proposed chaotic oscillator achieves the highest operating frequency of 37.5MHz.•The proposed circuit is simulated using commercially available ICs (MAX435 and AD844) and CMOS 180nm technology in PSPICE to confirm its workability.

Design, Simulation, and Cold Test of a W-Band Radial Rectangular Concentric Grating Backward Wave Oscillator

Design, Simulation, and Cold Test of a W-Band Radial Rectangular Concentric Grating Backward Wave Oscillator

Electronically Tunable Sinusoidal Oscillator Using Only Single Current-Controlled Current Conveyor Trans-Conductance Amplifier

This work presents a wide frequency range sinusoidal oscillator design that relies on only one active component, a current-controlled current conveyor trans-conductance amplifier, and a few passive components. It just employs two grounded and non-floating capacitors and one resistor to complete the procedure. This design has the advantage of allowing the oscillation frequency and condition to be adjusted not only electronically, but also separately, without affecting the values of any passive components. To verify the functionality and usefulness of the developed sinusoidal oscillator circuit, ORCAD PSPICE simulations are done using 0.18 um process parameters for complementary metal oxide semiconductor technology. The obtained results demonstrate its application to a wide range of frequency generation without the need for additional components, hence validating the theoretical expectation.

A Quadrature Oscillator with a Frequency-Tuned Distributed RC Network Analysis

This paper introduces an innovative two-stage distributed RC oscillator design, enhancing the noise performance and frequency stability for compact electronic devices. This work significantly reduces the comparator noise and improves system reliability by implementing a novel approach to increase the signal transition slope, coupled with optimized resistor and capacitor configurations. The study employs a quadrature oscillator topology and a precise reference voltage generation method, effectively addressing the challenges of mismatch and noise performance. A 469.2 kHz quadrature oscillator with two-stage distributed RC is implemented with a 0.18 μm CMOS process, achieving a FoM of −160 dBc/Hz at 100 Hz with a stable −20 dB roll-off in the phase noise and an Allan deviation floor of less than 0.7 ppm.

[formula omitted] methodology applied to ring oscillators

This work presents a ring oscillator design flow that calculates the transistor’s dimensions and bias currents that meet the oscillation frequency and phase noise requirements using only pre-calculated tables and MATLAB scripts. The methodology combines look-up tables, the gm/ID methodology, and the square root of the delay K. Results indicate a significant correlation between calculation and simulations with a variation percentage of the frequency oscillation from 2.3% up to 29% for oscillators designed in a TSMC 180 nm CMOS technology.

Inverse design of a Mamyshev oscillator with MW peak power by a particle swarm optimization algorithm

In this study we demonstrate implementation of a particle swarm optimization algorithm for inverse design of a fiber Mamyshev oscillator. We perform an extensive search in high-dimensional space of cavity parameters to maximize the output pulses’ peak power after external compression. The best obtained pulses have peak power exceeding 2 MW, energy >140nJ, and duration <40fs, and exhibit capabilities of handling ∼75π nonlinear phase accumulation.

Design and Analysis of Ultra-low Power Voltage Controlled Oscillator in Nanoscale Technologies

In latest wired and wireless communication equipment, VCO (voltage-controlled oscillator) is the major building block and particularly used as the stable high frequency clock generator. VCO performance is measured through frequency range, power supply used, area occupied, power consumption, delay, and phase noise. VCO is the cascaded of odd number of inverter stages in a ring format, hence it is also articulated as a ring oscillator. Today’s portable communication devices are battery operated. Hence, low power and area efficient designs play a key role in battery life enhancement and device size reduction. Device scaling improves the effective silicon area utilization, but it leads to more leakages. Therefore, low power techniques along with the technology scaling is the best way of low power designs. In this article, discussed various low power schemes. The ring oscillator designs are carried out in various nano meter scaled technologies such as 180nm, 90nm,65nm and 45nm. A 5-stage ring oscillator is implemented in each technology along with low power schemes, simulated in Cadence virtuoso, and noted power, delay, and area. Observed that the proposed ring oscillator with sleepy keeper technique generated a stable frequency of oscillations in the range of 1GHz-2GHz. A control voltage of 1.8V to 0.4V is applied and targeted the power less than 30mW and delay in 0.25p sec.

Characterization of Out-of-Plane Curved Fluidic Oscillators

A novel fluidic oscillator design, in which the oscillator is curved along the primary flow direction, was evaluated. The effects of mass flow rate, hydraulic diameter, aspect ratio, curvature radius, surface roughness, inlet orientation, and nonconstant curvatures were experimentally investigated. Measurements of the oscillation Strouhal number, discharge coefficient, spreading angle, and sweeping angle were used to characterize the jet. The resulting oscillators were found to fall into one of three categories: oscillated at the same frequency and sweep angle as conventional flat oscillators; oscillated at a slightly higher frequency and lower sweep angle than flat oscillators; or no dominant oscillation frequency detected and with no sweeping action. An unsteady Reynolds-averaged Navier–Stokes computational fluid dynamics simulation revealed fundamental differences in the internal flow mechanisms between flat and curved oscillators that drive the sweeping jet. The curvature between 37.5 and 62.5% of the total length, or the region from the inlet nozzle to halfway through the main chamber, was a primary factor influencing the response type of a design. Due to the curvature of these oscillators, they have the ability to be used in geometrically constrained spaces, such as the leading edge of wings and turbine vanes.

A low power varactor based digitally controlled oscillator design in 180 nm CMOS technology

This paper reports two distinct architectures for digitally-controlled oscillators (DCOs) utilizing MOS varactor, designed in TSMC 180 nm CMOS technology. The first DCO design employs a CMOS inverter, while the second design features a Three-Transistors (3T) NAND gate as a delay stage inverter. Using these delay stages, three-bit, five-bit, and seven-bit controlled DCO circuits have been designed. For the inverter-based DCO circuit, the frequency spans from 4.844 to 2.708 GHz, 2.523 to 0.853 GHz, and 1.364 to 0.253 GHz, with a power consumption of 0.958 mW, 1.597 mW, and 2.236 mW for three-bit, five-bit, and seven-bit DCO variants, respectively. Further, the 3T-NAND gate-based DCO circuit exhibits oscillation frequencies ranging from 2.024 to 0.517 GHz, 0.867 to 0.131 GHz, and 0.341 to 0.033 GHz, with the resulting power consumption of 0.335 mW, 0.559 mW, and 0.782 mW. Equally significant, the proposed inverter-based DCO attains phase noise of − 102.61 dBc/Hz@1MHz, − 99.65 dBc/Hz@1MHz, and − 117.54 dBc/Hz@1MHz, accompanied by corresponding figures of merit (FoM) 174.94 dBc/Hz, 161.27 dBc/Hz, and 165.10 dBc/Hz for three-bit, five-bit, and seven-bit control words, respectively. For the 3T-NAND gate-based DCO, phase noise levels register at − 93.51 dBc/Hz@1MHz, − 113.07 dBc/Hz@1MHz, and − 106.96 dBc/Hz@1MHz, with FoM values of 160.23 dBc/Hz, 166.70 dBc/Hz, and 150.30 dBc/Hz for three-bit, five-bit, and seven-bit DCO variants, respectively. The comprehensive analysis of the proposed DCOs demonstrates the power supply variations, phase noise deviations, and frequency variations. The reported DCOs perform better with regard to output frequency range, power consumption, and overall FoM.

Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology

This article presents the design and optimization of a tunable quadrature differential LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop (DFF) frequency divider. The VCO is designed for the low-power and low-phase-noise applications of 2.4 GHz IoT/BLE receivers and wireless sensor devices. The proposed design comprises the proper stacking of an LC VCO and a DFF frequency divider and is simulated using a TSMC 65 nm CMOS technology, and it has a tuning range of 4.4 to 5.7 GHz. The voltage headroom is preserved using a high-impedance on-chip passive inductor at the tail for filtering and enabling true differential operation. The VCO and frequency divider consume as low as 2.02 mW altogether, with the VCO section consuming only 0.47 mW. The active area of the chip including the pads is only 0.47 mm2. The designed VCO achieved a much better phase noise of −118.36 dBc/Hz at a 1 MHz offset frequency with 1.2 V supply voltages. The design produced a much better FoM of −196.44 dBc/Hz compared to other related research.

A miniature tunable quadrature shadow oscillator with orthogonal control

This article presents a new design of a quadrature shadow oscillator. The oscillator is realized using one input and two outputs of a second-order filter cell together with external amplifiers in a feedback configuration. The oscillation characteristics are controlled via the external gain without disturbing the internal filter cell, following the concept of the shadow oscillator. The proposed circuit configuration is simple with a small component-count. It consists of, two voltage-different transconductance amplifiers (VDTAs) along with a couple of passive elements. The frequency of oscillation (FO) and the condition of oscillation (CO) are controlled orthogonally via the dc bias current and external gain. Moreover, with the addition of the external gain, the frequency range of oscillation can be further extended. The proposed work is verified by computer simulation with the use of 180 nm complementary metal–oxide–semiconductor (CMOS) model parameters. The simulation gives satisfactory results of two sinusoidal output signals in quadrature with some small total harmonic distortions (THD). In addition, a circuit experiment is performed using the commercial operational transconductance amplifiers LM13700 as the active components. The circuit experiment also demonstrates satisfactory outcome which confirms the validity of the proposed circuit.

Oscillator design for high efficiency DC-DC of micro direct methanol fuel cell

This paper develops a novel oscillator with wide output frequency range, continuous frequency adoption, anti-electromagnetic interference (EMI), and high precision in order to achieve the high energy conversion efficiency of DC-DC for micro direct methanol fuel cell (μDMFC). The oscillator employs the state of art including frequency jitter, slope compensation, and digital trimming to perform the load mode control and detection module, thus linearly adjusting the operating frequency and modulation according to the load. Based on the 0.18 μm microelectronics process, the transient output of the presented oscillator during continuously turning on exports a stable voltage square wave. The jitter frequency ranges only about −1.66% to +4.3% of the base frequency. Moreover, the oscillator can adjust the typical output frequency linearly from 100 kHz to 1 MHz continuously based on the light or heavy load state. The oscillator yields stable performance under EMI with the jittering rate ranges from −31.82% to 36.2%. The quantitative results validates the wide frequency range, continuous frequency adoption, anti-EMI, and high precision of the oscillator. The oscillator solves the low energy conversion efficiency of the μDMFC DC-DC. The oscillator will achieve high energy conversion efficiency and stable output voltage of μDMFC for practical application.

Design analysis and experimental validation of relaxation oscillator-based circuit for R–C sensors

Relaxation oscillator-based circuits are widely used for interfacing various resistive and capacitive sensors. The electrical equivalent of most resistive and capacitive sensors is represented using a parallel combination of resistor and capacitor. The relaxation oscillator-based circuits are not suitable for parallel R–C sensors. In this paper, we propose a modified circuit for parallel R–C sensors. The proposed relaxation oscillator-based circuit is based on a dual-slope and charge transfer technique to measure the resistance and capacitance of parallel R–C sensors separately. In addition, the paper provides a detailed analysis and design considerations for the oscillator design by taking into account the various sources of non-idealities. A method to reduce the error by using single-cycle averaging is also introduced. To verify the analyzed design criteria, the circuit is tested with multiple operational amplifiers with different non-idealities. Experimental results verify the performance of the proposed circuit. The circuit is tested for a range from 10 pF to 42 pF and 100 kΩ to 1 MΩ for parallel R–C sensors with an error of less than 1.5%. The circuit is tested with a fabricated water-level sensor. The result confirms the efficacy of the proposed circuit.

A Subthreshold Biased CMOS Ring Oscillator Model Design in 180-nm Process

In this paper, a 180-nm CMOS ring oscillator design, made with halo-implanted transistors and operating in the weak inversion region, is proposed, based on an undergraduate integrated circuit design course methodology for building logic gates and comparing simulated results with reviewed literature data. Halo-implanted channel transistors have a steeper and less distorted voltage characteristic curve compared to uniformly doped channel ones, which makes them a more appropriate option when designing asynchronous digital integrated circuits aimed at low bias and low power. Three gate models were created using weak inversion and pull-up and pull-down networks made with halo-implanted transistors. The results of the study and simulation of the three inverter digital gate topologies showed that the NOT inverter model, as expected, had a higher frequency than the NAND and NOR inverter models. The ring oscillators made with the NOT inverter came up with an 8.25-MHz switching frequency as well as a dynamic power close to 270 nW. A comparison with other ring oscillators from previous studies is also shown.

Design and Implementation of Self-Limiting Two-Stage LC Oscillators Using Cascade Structure of Monolithic CCIIs as Active Elements

This paper presents the structure and principle of operation of two circuit configurations of self-limiting LC oscillators using monolithic positive second-generation current conveyors (CCII+s), that are implemented using Current-Feedback Operational Amplifiers (CFOAs) with an available compensation pin (Z). The proposed LC oscillators are synthesized using a systematic approach in the design of analog electronic circuits and can be considered as variants of the basic three-point oscillators, implemented using transistors (BJTs or FETs). Based on the analysis of the structure and electrical parameters of the CFOAs with a compensation pin (Z), electronic circuits of oscillators with two-stage amplifier blocks are synthesized. The characteristic equations and self-oscillation conditions are derived for the obtained analog circuits, and recommendations for designing circuits with arbitrary frequencies are defined. To verify the efficiency of the proposed LC oscillators, an experimental study is performed in the frequency range from 100 kHz to 10 MHz. The CFOAs AD844A with an external terminal z of the internal current conveyor are used as active elements. The obtained experimental results well match the results of the simulation modelling and the parameters based on the derived analytical expressions. The developed LC oscillators are intended to be used in schematic configurations of gas sensors based on surface acoustic wave (SAW) resonators.