Design Of Operational Transconductance Amplifier Research Articles

Analysis of an operational trans-conductance amplifier with positive feedback

In this paper, we present an analysis of an operational trans-conductance amplifier (OTA) with two positive feedback. The direct current (DC) transfer function is obtained by analyzing the OTA using the drain current in the weak inversion region. The analysis results were verified through comparison with SPICE simulations, and the characteristics of the DC transfer function analysis for the OTA design are well matched with the simulation results. The designed OTA dissipates a low power of 41.4 nW, and features the slew rate is improved by 436% compared to a conventional OTA without two positive feedback. Additionally, a DC gain and a unity-gain bandwidth is improved by 36 dB and 6.7 times, respectively. The OTAs are designed for the 0.18 μm complementary metal–oxide–semiconductor (CMOS) process.

A 0.8-Volt 29.52-μW Current Mirror-Based OTA Design for Biomedical Applications

An operational trans-conductance amplifier (OTA) is a fundamental component of electronic appliances. This paper introduces a novel design of OTA for minimal power, low voltage applications. The proposed OTA comprises an ultra low power current mirror design with enhanced bandwidth. The proposed OTA circuit is operated at 0.8[Formula: see text]V, contributing input noise of 26.33[Formula: see text]nV/(Hz)[Formula: see text] with a power of [Formula: see text]W. The additional parameters of new OTA are DC gain (87.32[Formula: see text]dB), common mode rejection ratio (145.47[Formula: see text]dB), gain bandwidth (4.73[Formula: see text]MHz), phase margin (36.56[Formula: see text]). These figures are significantly improved as compared to conventional OTAs. Analog-to-digital convertor (ADC) is also designed as an application of the proposed OTA. The improvements offered by ADC in terms of power and bandwidth are also compared with state of the art.

Hybrid Inverter-Based Fully Differential Operational Transconductance Amplifiers

Inverter-based Operational Transconductance Amplifiers (OTAs) are versatile and friendly scalable analog circuit blocks. Especially for the new CMOS technological nodes, several recent applications have been extensively using them, ranging from Analog Front End (AFE) to analog-to-digital converters (ADC). This work tracks down the current advances in inverter-based OTAs design, comparing their basic fully differential structures, such as Nauta (N), Barthelemy (B), Vieru (V) and Mafredini (M) ones, and, in addition, mixing them up to propose new fully differential single-ended and two-stage hybrid versions. The new herein-proposed fully differential hybrid OTAs are the composition of Barthelemy/Nauta (B/N), Barthelemy/Manfredini (B/M), Nauta/Vieru (N/V), and Manfredini/Vieru (M/V) OTAs. All OTAs were designed using the same Global Foundries 180 nm open-source PDK and their performances are compared for post-layout simulations.

Design methodology for general enhancement of a single-stage self-compensated folded-cascode operational transconductance amplifiers in 65 nm CMOS process

The problems resulting from the use of nano-MOSFETs in the design of operational trans-conductance amplifiers (OTAs) lead to an urgent need for new design techniques to produce high-performance metrics OTAs suitable for very high-frequency applications. In this paper, the enhancement techniques and design equations for the proposed single-stage folded-cascode operational trans-conductance amplifiers (FCOTA) are presented for the enhancement of its various performance metrics. The proposed single-stage FCOTA adopts the folded-cascode (FC) current sources with cascode current mirrors (CCMs) load. Using 65 nm complementary metal-oxide semiconductor (CMOS) process from predictive technology model (PTM), the HSPICE2019-based simulation results show that the designed single-stage FCOTA can achieve a high open-loop differential-mode DC voltage gain of 65.64 dB, very high unity-gain bandwidth of 263 MHz, very high stability with phase-margin of 73°, low power dissipation of 0.97 mW, very low DC input-offset voltage of 0.14 uV, high swing-output voltages from −0.97 to 0.91 V, very low equivalent input-referred noise of 15.8 nV/Hz, very high common-mode rejection ratio of 190.64 dB, very high positive/negative slew-rates of 157.5/58.3 V⁄us, very fast settling-time of 5.1 ns, high extension input common-mode range voltages from −0.44to 1 V, and high positive/negative power-supply rejection ratios of 75.5/68.8 dB. The values of the small/large-signal figures-of-merits (𝐹𝑜𝑀s) are the highest when compared to other reported FCOTAs in the literature.

Miller compensated four-stage OTA with Q-reduction for wide range of load capacitors

This paper proposes a four-stage miller compensated Operational Transconductance Amplifier (OTA) with Q-reduction. The multi-stage OTA is an ideal choice for the submicron CMOS technology. The main challenge in multi-stage OTA design with low quiescent current is the increased number of high impedance nodes. These high impedance nodes create stability issues. Usually, the multi-stage OTA requires the compensation capacitor in the order of pF which consumes more chip area; moreover, it reduces the bandwidth of the OTA. The proposed four-stage OTA uses a single miller capacitor Cm along with a feed-forward capacitor Cf. The four-stage OTA uses only 500fF of total compensation capacitors to stabilize a complex four-stage OTA. The proposed OTA uses multiple feed-forward paths to enhance the small-signal and the large-signal performances of the OTA. The four-stage OTA achieves a better transient response with the settling time of 510ns under low quiescent power of 63.6μW for the wide range of load capacitors of 5pF to 100pF.

Are CMOS Operational Transconductance Amplifiers Old Fashioned? A Systematic Review

Operational Transconductance Amplifiers (OTAs) are essential building blocks in analog circuits. Since the early years of integrated circuit science, OTAs have been used in industry and researched in academia. Over the years, a number of techniques and approaches to OTA design have been observed in the literature. With this systematic review, we aim to provide a overview of top journal papers published from 2017 to 2021 containing OTA design. In our investigation we initially found 128 manuscripts and 24 primary studies of OTA design. A set of 10 different techniques have been found. Furthermore, we also evaluate used technology, inversion level and characterization process. With this study we contribute to highlight recent OTA design innovations.

A 0.6-V 11-uW PVT tolerant DTMOS inverter based OTA

This paper presents the design of a process-voltage-temperature (PVT) variation tolerant inverter-based operational transconductance amplifier (OTA) employing both a dynamic threshold MOS (DTMOS) technique and a constant voltage biasing (CVB) scheme. The proposed inverter-based OTA offers a higher bandwidth due to implemented DTMOS technique, which realizes higher input transconductance value than a conventional inverter-based OTA design. Simulation results show that the proposed OTA achieves superior slow-slow (SS) corner performance under PVT variations than the conventional inverter-based OTA while consuming only 11-uW and providing a figure of merit (FoM) of 7.0-MHz.pF/uA. As a result, DC gain and unity-gain bandwidth (UGBW) of the proposed OTA improve by 27% and 32% at SS corner under the PVT variations, respectively.

Low-voltage bulk-driven flipped voltage follower-based transconductance amplifier

A low voltage high performance design of operational transconductance amplifier is proposed in this paper. The proposed architecture is based on bulk driven quasi-floating gate metal oxide semiconductor field effect transistor (MOSFET) which supports low voltage operation and improves the gain of the amplifier. Besides to this the tail current source requirement of operational transconductance amplifier (OTA) is removed by using the flipped voltage follower structure at the input pair along with bulk driven quasi-floating gate MOSFET. The proposed operational transconductance amplifier shows a five-fold increase in direct current (DC) gain and 3-fold increase in unity gain bandwidth when compared with its conventional bulk driven architecture. The metal oxide semiconductor (MOS) model used for amplifier design is of 0.18 um complementary metal oxide semiconductor (CMOS) technology at supply of 0.5 V.

Design of operational transconductance amplifier with Gate-All-Around Nanosheet MOSFET using experimental data from room temperature to 200 °C

In this work, a Gate-All-Around Nanosheet transistor (GAA-NSH) is used to design an operational transconductance amplifier (OTA) operating from room temperature to 200 °C. A simulation model for the transistor was created using Verilog A language including a lookup table (LUT) with current response and capacitance data obtained from measurement of fabricated devices. Two OTA designs were made, for supply voltages (VDD) of 2.1 V and 1.5 V. The first design was analyzed at room temperature (25 °C) with different bias points that defined the transistors efficiency (gm/ID) of the first stage input differential pair and current mirror load. A comparison with other OTA projects using FinFET and Tunnel FET (TFET) devices was performed considering similar gm/ID for all designs. The GAA-NSH design presents a larger voltage gain than the FinFET design (71.8 dB vs. 67.6 dB), while consuming less power (544.5uW vs. 1.41mW) and utilizing smaller devices and an overall smaller area footprint. Improvements are a consequence of the superior gate electrostatic coupling of the GAA-NSH transistors that can be seen through the improved transconductance and output conductance values. Compared with the TFET device, the GAA-NSH presents a tradeoff between Bandwidth and power consumption. Finally, the second OTA designed is analyzed from room temperature to 200 °C, and a decrease of the voltage gain and GBW was observed due to the mobility degradation at high temperature.

Design of high speed 2-stage OTA for high capacitive load of 120 pF and 2.96 V

High speed operational transconductance amplifier (OTA) is used to drive high capacitive loads to reduce the charging time while providing adequate gain and stability. A 2-stage amplifier is proposed to provide high slew rate and sufficient gain and stability. 45 nm process technology is used to compare performance with differential and telescopic amplifier designs. Resistive feedback and noise-gain compensation techniques are used to drive 120 pF load of a row driver circuit used in an active pixel sensor and provide 2.96 V at output for a high slew rate of 2.2 V/μs.

Design of high gain and high bandwidth operational transconductance amplifier (OTA)

ABSTRACT A novel operational transconductance amplifier (OTA) having high gain and high bandwidth for high-speed analog communication techniques and precision filtering is designed in this paper. The designed OTA uses β-multiplier-based current biasing scheme with folded cascode amplifier scheme in order to improve the small signal models and the DC gain of circuit. The OTA design was carried out using TSMC 65 nm CMOS technology using Cadence Virtuoso tool with 1 V supply voltage and 10 pf capacitive load. The output DC gain was found to be approximately 75.3 dB. In addition, the unity gain frequency for the designed OTA was found to be around 200 MHz. Superior common mode rejection ratio, power supply rejection ratio and slew rates along with compact chip area and low power are other salient features of the designed OTA. The designed OTA can be employed in order to design high performance analog circuits like data converters, phase-locked loops, etc.

Low voltage high performance super class AB OTA design using SCCM and DTMOS with enhanced slew rate and DC gain

This paper presents two low voltage high performance super class AB Operational Transconductance Amplifiers (OTAs) along with the second stage. The proposed OTA-I implements self cascode current mirrors (SCCMs) as the active load to provide high output swing. And the flipped voltage followers (FVFs) based adaptive biasing technique for the differential input stage to provide an additional current boosting and offers significantly improved slew rate and dynamic characteristics. Proposed OTA-II is the DTMOS implementation of proposed OTA-I suitable for low voltage operation. It utilizes the body effect and offers a more enhanced performance with minimized power consumption. The small-signal analysis shows the improvements achieved in dc gain and gain-bandwidth product (GBW). The second-order universal MISO filter realized using the proposed OTAs validates its competency. The simulation results are obtained using Mentor Graphics Eldospice tool with TSMC 0.18 ​μm technology. The proposed OTA-I (±0.75 ​V) and the proposed OTA-II (±0.5 ​V) provides dc gain as 105.66 ​dB and 108.15 ​dB with greatly improved average slew rate by factor 216 to 339 and enhanced GBW by factor 16 to 120 with reduced power dissipation as compared to conventional class A OTA. Besides, it also provides an improvement in the common-mode rejection ratio (CMRR). The figure of merit of proposed OTAs is 9621 [(MHz).pF/mW] and 50322[(V/μs).pF/mW] respectively for the load capacitor of 10 ​pF, and shows significant improvement compared to prior work. To authenticate the robustness of proposed OTAs, Monte Carlo and Corner analyses done with Process-Voltage-Temperature variations.

Design and analysis of current mirror OTA in 45 nm and 90 nm CMOS technology for bio-medical application

This paper proposed a design and performance analysis of current mirror operational transconductance amplifier (OTA) in 45 nm and 90 nm complementary metal oxide semiconductor (CMOS) technology for bio-medical application. Both OTAs were designed and simulated using Synopsys tools and the simulation results were analysed thoroughly. The OTAs were designed to be implemented in bio-potential signals detection system where the input signals were amplified and filtered according to the specifications. From the comparative analysis of both OTAs, the 45 nm OTA managed to produce open loop gain of 45 dB, with common mode rejection ratio (CMRR) of 93.2 dB. The 45 nm OTA produced only 1.113 μV√Hz of input referred noise at 1 Hz. The 45 nm OTA also consumed only 28.21 nW of power from ± 0.5 V supply. The low-power consumption aspect displayed by 45 nm OTA made it suitable to be implemented in bio-medical application such as bio-potential signals detection system where it can be used to amplify and filter the electrocardiogram (ECG) signals.

Analysis of subthreshold SOI FinFET based two stage OTA for low power

In this paper, subthreshold design and analysis of Silicon on Insulator Fin Field Effect Transistor (SOI FinFET) based two stage Operational Transconductance Amplifier (OTA) is presented for low power and low supply voltage in nanometre regime. The OTA design optimization is achieved by $$g_{m}/I_{D}$$ methodology which helps to determine the device aspect ratios. Compactness is achieved by using nanometre FinFET technology. The OTA design is simulated using 30 nm SOI FinFET Berkeley Short-channel IGFET Common Multi-gate (BSIM-CMG) model, with bias current and supply voltage of 20 nA and $$\pm 0.5 V$$ ;respectively. The simulation results in subthreshold regime of FinFET based two stage OTA has a gain of 57 dB with a phase margin of 69.81 degree, Common Mode Rejection Ratio (CMRR) of 61.55 dB and power consumption of 108 nW.

Design and implementation of sub 0.5‐V OTAs in 0.18‐μm CMOS

SummaryA family of bulk‐driven CMOS operational transconductance amplifiers (OTAs) has been designed for extremely low supply voltages (0.3‐0.5 V). Three OTA design schemes with different gain boosting techniques and class AB input/output stages are discussed. A detailed comparison among these schemes has been presented in terms of performance characteristics such as voltage gain, gain‐bandwidth product, slew rate, circuit sensitivity to process/mismatch variations, and silicon area. The design procedures for all the compared structures have been developed. The OTAs have been fabricated in a standard 0.18‐μm n‐well CMOS process from TSMC. Chip test results are in good agreement with theoretical predictions and simulations.

An Ultra-Low-Voltage Bulk-Driven Analog Voltage Buffer with Rail-to-Rail Input/Output Range

This paper presents a low-voltage high driving capability rail-to-rail Class-AB CMOS bulk-driven (BD) operational transconductance amplifier (OTA) for analog voltage buffer with minimal current consumption. The proposed OTA design consists of adaptively biased Class-AB differential input stage to improve the effective transconductance and adaptive load relying on nonlinear current mirrors, configured in partial positive feedback mode to enhance the overall gain. In addition, because of adaptive bias and load configuration, the load-driving capability of OTA increases for a large change in differential input. The circuit is designed using UMC 65-nm CMOS process node and is operated at supply voltage of 0.5 V with a standby current consumption of 4.25 $$\upmu $$μA. Simulation results show that the buffer based on the proposed BD-OTA achieves an average slew rate of 93.2 mV/$$\upmu $$μs for a capacitive load of 100 pF, which is nearly 29 times that of conventional OTA with 13$$\%$$% increment in quiescent power dissipation.

A High Slew-Rate Adaptive Biasing Hybrid Envelope Tracking Supply Modulator for LTE Applications

A linear-switch mode hybrid envelope tracking (ET) supply modulator utilizing adaptive biasing and gain enhanced current mirror operational transconductance amplifier (OTA) with class AB output stage in parallel with a switching regulator is presented. In comparison to a conventional OTA design with similar quiescent current consumption, proposed approach improves positive and negative slew rate from 50 to 93.4 V/ $\mu \text{s}$ and −87 to −152.5 V/ $\mu \text{s}$ , respectively, dc gain from 45 to 67 dB while consuming same amount of quiescent current. The proposed hybrid supply modulator achieves 83% peak efficiency, power-added efficiency (PAE) of 42.3% at 26.2 dBm for a 10-MHz 7.24-dB peak-to-average power ratio (PAPR) long-term evolution (LTE) signal and improves PAE by 8% at 6 dB back off from 26.2-dBm power amplifier (PA) output power with respect to fixed supply. With a 10-MHz 7.24-dB PAPR quadrature-phase shift keying LTE signal the ET PA system achieves adjacent channel leakage ratio (ACLR) of −37.7 dBc and error vector magnitude (EVM) of 4.5% at 26.2-dBm PA output power, while with a 10-MHz 8.15-dB PAPR 64QAM LTE signal the ET PA system achieves ACLR of −35.6 dBc and EVM of 6% at 26-dBm PA output power without digital predistortion. The proposed supply modulator core circuit occupies 1.1-mm2 die area, and is fabricated in a 0.18- $\mu \text{m}$ CMOS technology.

Low Noise Low Power CMOS Telescopic-OTA for Bio-Medical Applications

The preamplifier block is crucial in bio-medical signal processing. The power intensive Operational Transconductance Amplifier (OTA) is considered, and the performance of preamplifier is studied. A low noise and low power telescopic OTA is proposed in this work. To reduce the noise contribution in the active load transistors, source degeneration technique is incorporated in the current stealing branch of the OTA. The OTA design optimization is achieved by g m / I d methodology, which helps to determine the device geometrical parameters (W/L ratio). The proposed design was implemented in CMOS 90 nm with bias current and supply voltage of 1.6 µA and 1.2 V, respectively. The post layout simulation results of the proposed amplifier gave a gain of 62 dB with phase margin 57°, CMRR 78 dB, input referred noise 3.2 µVrms, Noise Efficiency Factor (NEF) 1.86 and power consumption of 1.92 µW.

Variable-Mirror Amplifier: A New Family of Process-Independent Class-AB Single-Stage OTAs for Low-Power SC Circuits

This paper presents a new family of Class-AB operational transconductance amplifier (OTA) circuits based on single-stage topologies with non-linear current amplifiers. The proposed variable-mirror amplifier (VMA) architecture is mainly characterized by generating all Class-AB current in the output transistors only, by exhibiting very low sensitivity to both technology and temperature deviations, and by avoiding the need for any internal frequency-compensation mechanism. Hence, this family of OTAs is well-suited for low-power switched-capacitor circuits and specifically optimized for switched-OpAmp fast on-off operation and multi-decade load-capacitance specifications. Analytical expressions valid in all regions of operation are presented to minimize VMA settling time in discrete-time circuits. Also, a complete OTA design example integrated in 0.18 $\mu\text{m}$ 1P6M MiM 1.8 V CMOS technology is supplied with detailed simulation and experimental results. Compared to resistor-free state-of-art Class-AB OpAmp and OTA literature, the proposed architecture returns the highest measured figure-of-merit value.

Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET

As the gate lengths of FinFETs are scaled into nano meter regime, spatial variations in oxide thickness (Tox) and junction depth (Xj) of source/drain (S/D) doping profile will largely decide the performance of digital and analog circuits that can fall below or above the desired value. Of particular importance is operational transconductance amplifier (OTA), where the crucial analog figures of merit (FOM) such as differential mode gain (ADM), common mode gain (ACM) and common mode rejection ratio (CMRR) decide the suitability of its use at nanometer regime. In the present work, we have studied the analog performance variation of low-k (dual-k) underlap FinFET based single stage OTA with spatial variation in Tox and Xj of S/D profile. Enhanced and variation less threshold voltage and mobility of dual-k underlap FinFET due to of better screening of longitudinal field and pronounced volume inversion effect, are studied in detail. It is observed that at 16nm gate length the best case ADM, ACM and CMRR of low-k (dual-k) FinFET based OTA are 34.2dB (42.3dB), 26dBm (18dBm), 68.2dB (84.2dB) respectively. Subsequently, the spatial variation of Tox and Xj leads to worst case change in ADM and ACM of low-k (dual-k) FinFET based OTA by −6.8dB (−2.2dB) and +28.2dBm (+31.3dBm) respectively. The negligible deterioration in ACM of dual-k FinFET OTA transforms into CMRR improvements of 37% at this worst case condition as compared to CMRR of low-k FinFET OTA. Furthermore, with gate length scaling, the FOM and their percentage change with Tox and Xj of dual-k FinFET OTA are much better than that of low-k FinFET OTA.