Design Of Operational Amplifier Research Articles

CMOS operational amplifier design for industrial and biopotential applications: Comprehensive review and circuit implementation

This paper provides a detailed exploration of CMOS operational amplifiers (Op-Amps) aimed at enhancing understanding of their development, design, and application. To achieve this, a comprehensive examination of the common characteristics, parameters, and bibliographic reviews of Op-Amps, distinguishing among various chosen operational amplifiers. A comprehensive bibliographic review of the operational amplifier's keywords between 2008 and 2018 has also been conducted. A bibliometric analysis of 4997 documents from the Web of Science (WOS) Collection is conducted using VOSviewer software. Furthermore, an analysis and comparison of these Op-Amps across functional aspects relevant to industrial and biomedical applications, emphasising the salient characteristics of each technique. After the survey, a novel Op-Amp design is proposed, incorporating a differential amplifier at the first stage, along with a compensating capacitor and a high gain stage. The biasing circuitry is replaced with an active load resistor (MOS transistor), simplifying layout design, and reducing the amplifier's area and power consumption compared to traditional two-stage designs. The power source for this design is 3.3 V. This designed operational amplifier achieved a gain of 62.9449 dB, a high CMRR of 92.8079 dB, and a unity gain bandwidth of 33 MHz, and the optimised layout area is 0.001476 μm2. The proposed circuit was designed and simulated utilising the Cadence Virtuoso 180 nm CMOS process. The simulation results show that the desired criteria have been met. Additionally, the challenges and future possibilities in analog circuits, laying the groundwork for research in both analogue and digital circuits to tackle complex real-world issues have been addressed.

Design of High Gain Single Stage Telescopic Cmos Operational Amplifier

A need for high gain operational amplifiers (op-amps) exists for certain applications. This requires research in the area of its gain without affecting other parameters drastically. In this paper, high gain single stage Telescopic CMOS operational amplifier has been designed and verified, using PSPICE simulation software. The designed circuit operates at ±5V power supply in the 1µm CMOS technology. The simulation results show that the proposed single stage Telescopic CMOS op-amp has an open loop gain of 77.777dB, unity gain frequency of 7.3054MHz, ICMR of -0.248V to 4.4120V and output voltage swing of 7688.8 times to that of input. A 2pF load capacitor is applied in performing a stable phase margin of 80.669°. As result shows that the designed circuit has high gain, which is used for various applications where very large gain is required to amplify weak signals, such as heart beat in medical instrumentations. The total power consumed by the device is 0.589mW. This shows that the power consumed by the device is too small. Therefore, this device can operate for longer duration of time. The smaller the power dissipation the better the device is. Low power operation is a very important quality factor for batteries that should supply the system for hours or days to power more and more electronic systems.

Enhancing the design of a two-stage CMOS operational amplifier utilising the Bat Algorithm

ABSTRACT The increasing demand for high-performance two-stage CMOS Op-Amps in electronic, communications, and biomedical applications necessitates their operation with wide bandwidth, high voltage gain, and low power consumption. By leveraging the Bat Algorithm global search and local exploration capabilities, the study demonstrates a significant improvement in the amplifier’s overall performance. This design of a two-stage CMOS Op-Amp using 0.18 µm TSMC technology, powered by a ± 1.8 V supply voltage. The simulation outcomes were gathered using the PSPICE software (version 17.4). These design strategies prove highly efficient, achieving high gain, high frequency, and low power consumption. Additionally, the paper showcases the execution and simulation results of a two-stage CMOS Op-Amp based on the Bat Algorithm, utilising MATLAB for this purpose. The employment of the BA results in substantial enhancements in performance metrics. Specifically, the Unity Gain Bandwidth sees a doubling in its value, the voltage gain rises by 20%, power consumption falls by 39.1%, and the Common Mode Rejection Ratio improves by 20% compared to a two-stage CMOS Op-Amp designed without the BA. The findings underscore the BA potency as a robust optimisation method for boosting the performance of a two-stage CMOS Op-Amp.

A Compact Model for Carbon Nanotube Field Effect Transistors Incorporating Temperature Effects and Application for Operational Amplifier Design

Semiconducting carbon nanotubes (CNTs), characterized by high carrier mobility and atomic thickness, are considered ideal channel materials for building high-performance and ultimate-scale field-effect transistors for future electronics. Here, we present a data-calibrated compact model of CNT field-effect transistors (CNTFETs) that incorporates temperature effects using the virtual source approach. The proposed model also includes the self-heating effect. Temperature effect was characterized by the influence of temperature on devices, achieved through establishing a temperature-dependent semi-empirical model of carrier mobility and carrier velocity. The proposed model can be easily implemented in a simulator. We designed a two-stage operational amplifier (OPAMP) using the proposed model at 32 nm technology. Compared with other studies, the designed CNTFET-based OPAMP demonstrates lower power consumption, which is beneficial for exploring the biological applications of low-power analog circuits in portable electronic devices. Furthermore, the impact of thermal variations on the design of OPAMP, as per the proposed model, was delineated. Investigations revealed that our circuit maintains a high common mode rejection ratio, which diminishes as the temperature increases and exhibits a moderate gain value that escalates with temperature.

Design and implementation of a preset operational amplifier based on basic digital and analog hybrid circuit

In the vast landscape of electronic engineering, the indispensable roles of both analog and digital circuits are unequivocally recognized. Analog circuits, with their foundational principles, are extensively harnessed in areas encompassing audio, video, power systems, and particularly, amplifiers. Conversely, digital circuits, integral to modern-day technological advancements, are dominantly present in computing platforms, telecommunication systems, control mechanisms, and data storage infrastructures. Amplifiers, a cornerstone in analog circuit designs, principally focus on magnifying the amplitude of input signals, whether it be in terms of voltage or current. This amplification process hinges on the strategic configuration of electronic elements such as transistors, resistors, and capacitors. This paper endeavors to marry the attributes of digital and analog circuits. Through the adept utilization of fundamental electronic components, an innovative amplifier design capable of preset amplification ratios is birthed. The practicality and efficacy of this amplifier are rigorously validated via its hands-on assembly and experimental testing in a laboratory setting. Results consistently underscore the amplifiers adeptness in delivering precise signal amplification, conforming to its predetermined ratios. Such a design, rooted in its simplicity yet offering profound versatility, beckons further exploration. It stands as a beacon for potential future adaptions, tailored to suit a gamut of applications, and is poised to seamlessly dovetail into more sophisticated circuit systems.

Analysis of a Low-Power OTA-Based Neural Amplifier Design for EEG Signal Acquisition

This paper presents the design of an efficient operational transconductance amplifier (OTA) to be explicitly used for electroencephalogram (EEG) signal acquisition in neural amplifiers (NAs). The central objective of this study revolves around addressing the fundamental compromise between noise and power in the design of NAs. The overarching goal is to effectively mitigate this trade-off by introducing novel approaches. The proposed design’s novelty lies in utilizing an adaptive biasing technique instead of the traditional current mirror biasing technique. Furthermore, the conventional input differential pair of the OTA is modified to employ a self cascode flipped voltage follower (SCFVF), which eventually reduces power consumption of the NA to 0.822 [Formula: see text]W. Additionally, notable improvements in noise performance are achieved and found to be 624.9 nV/[Formula: see text] at 1 Hz. The gain and bandwidth range of the input low-noise amplifier is 54.2 dB and 2.8 Hz–207 Hz, respectively, which effectively amplifies low-amplitude noisy incoming signals, addressing the specific requirements of EEG signal acquisition.

Design of BJT-JFET Operational Amplifiers on the Master Slice Array

The use of dual-gate field-effect transistors located on the base matrix crystal MH2XA031, controlled by a p–n junction needed to reduce the input current of operational amplifiers is studied. Typical circuits of operational amplifiers, containing: source repeaters connected to the inputs of the operational amplifier on complementary bipolar transistors; input differential stage on p-JFET with a “current mirror” load on n–p–n-transistors; input differential in the form of a “folded cascode” on a p-JFET are analyzed. To minimize the input current, it is re commended to use bootstrapped feedback to keep the drain-to-source voltage of the input JFETs low, independent of the input common-mode voltage, and to connect only the top gate of the dual-gate JFET to the op-amp input. The electrical circuits for MH2XA031 elements and the results of circuit simulation of the developed amplifiers, called OAmp10J, OAmp11.1, OAmp11.2, are presented. Accounting the established features of the input stages and operating modes of active elements in circuit design will allow to create an operational amplifier with the required combination of basic parameters.

Innovative Design and Application Analysis of Integrated Operational Amplifiers

Operational amplifiers in integrated circuits come in many varieties and numbers and are an essential part of electronic systems. Its performance directly affects the accuracy and effectiveness of the whole system. As the market demand for operational amplifiers in different fields is growing day by day, according to different kinds of demand, people have designed a variety of operational amplifier structure. This paper describes the basic characteristics of operational amplifiers and analyzes three basic structures that are extremely relevant for modification circuits. The common-source, common-gate circuit structure op-amp has the advantages of high gain, high input common-mode range, high output swing, and high overall gain bandwidth, so it has been adopted as the most commonly used architecture today and in the future. The current improvements in operational amplifier design are mainly focused on two-stage operational amplifiers, and less on multi-stage operational amplifiers. The folded common source and common gate operational amplifier circuits are characterized by good frequency characteristics, comparatively low power consumption and high bandwidth per unit gain. The demands on the performance of operational amplifiers will become higher and more varied, and more excellent improved circuits are needed.

Improving noise levels based on amplifier structure analysis

As the core component of electronic circuits, amplifiers play a pivotal role in fields such as communications, medical care, audio processing, instrumentation, scientific research and military technology. However, the noise problem of the amplifier has a direct impact on the reliability and accuracy of the system, how to reduce the impact of noise is crucial. This paper aims to study and solve noise problems in amplifier design. The first part focuses on the design of operational amplifiers. By adjusting the circuit structure and introducing current mirrors, the noise of the input and output stages is successfully reduced and the amplifier performance is improved. The second part focuses on the design of instrumentation amplifiers, introducing kT/C noise elimination technology, chopper modulation structure solves the noise and aliasing problems in switched capacitor instrumentation amplifiers and improve performance.

A Survey of Ultra-Low-Power Amplifiers for Internet of Things Nodes

This paper investigates CMOS operational transconductance amplifier (OTA) design methodologies suitable for Internet of Things nodes. The use of MOS transistors in the subthreshold of the body terminal for signal input or bias, as well as newer inverter- and digital-based techniques, is considered. Solutions from the authors’ work are utilized as main case examples. State-of-the-art ultra-low-power OTAs are then thoroughly compared using a data-driven approach. According to the findings, digital- and inverter-based solutions have the lowest area occupation and superior small-signal performance but are inherently susceptible to process, supply, and temperature (PVT) variations. The only “analog” approach suitable for a sub-0.6 V supply is body driving in conjunction with subthreshold bias. It offers competitive large-signal performance and, more importantly, is less sensitive to PVT variations at the expense of silicon area.

Design Specification and Simulations of a Miller compensated Operational Amplifier with 75dB Gain

This paper presents a two-stage Miller compensated operational amplifier design using cadence 55nm CMOS technology. This circuit provides a single ended output due to mirror pole is implemented while the input of this operational amplifier is differential. A biasing circuit is also designed and attached with this amplifier. This operational amplifier provides a gain of 75.41dB while the phase margin is off 70o. The Gain bandwidth of this operational amplifier is 9.5MHz. The power consumption of this overall circuit including the biasing circuit is 154.69µW. The other performance parameters are also analyzed and provide in this paper. The mathematical calculation for the circuits is also presented. Due to medium power consumption and higher gain bandwidth this amplifier can be used in different data converters like Delta-Sigma ADC. Because the performance of this ADC is depending upon the higher Gain Bandwidth.

Design of High Performance Operational Transconductance Amplifier

Designing high-performance analog circuits is becoming increasingly challenging with the persistent trend toward reduced supply voltages. The main bottleneck in an analog circuit is the operational amplifier. At large supply voltages, there is a trade off among speed, power, and gain, amongs to ther performance parameters. Often these parameters present contradictory choices for the op-amp architecture. At reduced supply voltages, output swing becomes yet another performance metric to be considered when designing the opamp. Of the several architecture folded cascode OTA is used in which all the transistors are in saturation regime. Furthermore, in an effort to reduce costs and integrate analog and digital circuits onto a single chip, the analog designer must often face the challenges using CMOS processes. This paper covers the design and implementation of a novel CMOS folded cascode OTA designed in 1m technology. Covered topic include current source and sinks, differential amplifier, compensation techniques, two stage compensated OTA and cascode OTA. Our design emphasis is on practical design where power consumption and speed are critical. The OTA has very low settling time and can be used for high speed applications, such Analog-to–Digital converters, high speed Sigma-delta ADC.

Design and modelling of operational amplifier for energy systems

In the present study the single channel operational amplifier IS-OU1 with 15 V supply voltage (open loop gain ~100-110 dB) design is based on n-p-n type bipolar transistors has been developed. It is shown that the proposed macromodel sufficiently describes behaviour of operational amplifier. It is established that obtained electrical parameters characteristics of operational amplifier macromodel have good agreement with design requirements. Consequently the proposed design operational amplifier can be applied in industry production for further use in electrical integrated analogue circuits and energy systems.

Design of chopper operational amplifier for leakage current protector chip

Due to the low frequency and small amplitude of the input signal of the leakage current protection chip, an operational amplifier with low offset and low power consumption is designed by using the chopper stabilization technique and the dynamic element matching technique. Based on the TSMC 0.18um process, the spectre environment in cadence is used for design and simulation. The power supply voltage is 1.8V. The post simulation results show that under the TT corner, the average current of the operational amplifier is 139uA, the loop gain is 85.9dB, the phase margin is 68.01°, and the power supply rejection ratio(PSRR) is 101.62dB@50Hz, the common mode rejection ration(CMRR) is 104.52dB@50Hz, the equivalent input noise is 129.86nv/sqrt(Hz)@50Hz, and the value of equivalent input offset voltage is 8.2uV(mean).

Design methodology for general enhancement of a single-stage self-compensated folded-cascode operational transconductance amplifiers in 65 nm CMOS process

The problems resulting from the use of nano-MOSFETs in the design of operational trans-conductance amplifiers (OTAs) lead to an urgent need for new design techniques to produce high-performance metrics OTAs suitable for very high-frequency applications. In this paper, the enhancement techniques and design equations for the proposed single-stage folded-cascode operational trans-conductance amplifiers (FCOTA) are presented for the enhancement of its various performance metrics. The proposed single-stage FCOTA adopts the folded-cascode (FC) current sources with cascode current mirrors (CCMs) load. Using 65 nm complementary metal-oxide semiconductor (CMOS) process from predictive technology model (PTM), the HSPICE2019-based simulation results show that the designed single-stage FCOTA can achieve a high open-loop differential-mode DC voltage gain of 65.64 dB, very high unity-gain bandwidth of 263 MHz, very high stability with phase-margin of 73°, low power dissipation of 0.97 mW, very low DC input-offset voltage of 0.14 uV, high swing-output voltages from −0.97 to 0.91 V, very low equivalent input-referred noise of 15.8 nV/Hz, very high common-mode rejection ratio of 190.64 dB, very high positive/negative slew-rates of 157.5/58.3 V⁄us, very fast settling-time of 5.1 ns, high extension input common-mode range voltages from −0.44to 1 V, and high positive/negative power-supply rejection ratios of 75.5/68.8 dB. The values of the small/large-signal figures-of-merits (𝐹𝑜𝑀s) are the highest when compared to other reported FCOTAs in the literature.

Low-voltage Low-power Bulk-driven CMOS Op-Amp Using Negative Miller Compensation for ECG

Two bulk-driven CMOS (Complementary Metal Oxide Semiconductor) operational amplifier (op-amp) designs for electrocardiogram (ECG) application are presented and compared in this paper. Both op-amps are based on two-stage amplification, where bulk-driven differential input is the first stage, while additional DC gain is the second stage. Different compensation techniques were integrated in each op-amp design. Standard Miller compensation was used for the first op-amp parallel with the second stage. The novelty of the second op-amp is that it utilizes negative Miller compensation between the bulk-driven input node and the output node of the first stag, while standard Miller compensation was used in the second stage. The purpose of this work was to compare DC gain, phase margin (PM) and unit gain frequency (UGF) obtained through different simulated compensation strategies and test results. The op-amps were simulated using 0.25 μm CMOS technology. The simulation results are presented using the standard model libraries from Tanner EDA tools, operating on a single rail +0.8V power supply.

Low-voltage bulk-driven flipped voltage follower-based transconductance amplifier

A low voltage high performance design of operational transconductance amplifier is proposed in this paper. The proposed architecture is based on bulk driven quasi-floating gate metal oxide semiconductor field effect transistor (MOSFET) which supports low voltage operation and improves the gain of the amplifier. Besides to this the tail current source requirement of operational transconductance amplifier (OTA) is removed by using the flipped voltage follower structure at the input pair along with bulk driven quasi-floating gate MOSFET. The proposed operational transconductance amplifier shows a five-fold increase in direct current (DC) gain and 3-fold increase in unity gain bandwidth when compared with its conventional bulk driven architecture. The metal oxide semiconductor (MOS) model used for amplifier design is of 0.18 um complementary metal oxide semiconductor (CMOS) technology at supply of 0.5 V.

Implementation of Modified folded Cascode OTA in Different Biasings Voltages

This paper presents an optimized methodology to modified folded Cascode operational trans conductance amplifier (OTA) design. The design is done in different regions of operation, weak inversion, strong inversion and moderate inversion using the gm/ID methodology in order to optimize MOS transistor sizing. This new family of OTA designs is suitable for biomedical and healthcare circuits and systems, due to the high energy-efficiency, improved gain and low level of noise contribution, when compared to the stateof- the-art in this field. In this paper, two fully-differential implementations are presented, a first one with a double CMOS branch biased by two pairs of voltage-combiners structures in both NMOS and PMOS configurations, and a second one with folded voltagecombiners specifically targeting low voltage applications. The folded voltage-combiners biased OTA is able to operate correctly under a voltage supply down to 0.7 V with proper DC biasing. The simulation is performed in HSPICE Synopsys Tool and compared with existing designs.

A low-noise and fast transient response LDO design for high-speed SerDes

In order to deal with the special needs of high-speed digital-analog hybrid circuits for power supplies, this article has designed a LDO circuit specifically applied to high-speed SerDes. In the design process, a cross-coupled charge pump was used to increase the swing and reduce power supply noise, and to increase the gain and reduce the area overhead, the design of an asymmetric operational amplifier was introduced. At the same time, the use of the cascode structure is also conducive to the frequency stability of the loop and provides sufficient phase margin for the circuit. Through simulation verification, the low-frequency maximum internal noise of this LDO is only 0.96uV/sqrt(Hz), the transient response time when the load changes from low to high is 38ns, the transient response time from high to low is 84ns, the phase margin is 87.3deg, and the PSRR is 56.8dB.

Design of operational transconductance amplifier with Gate-All-Around Nanosheet MOSFET using experimental data from room temperature to 200 °C

In this work, a Gate-All-Around Nanosheet transistor (GAA-NSH) is used to design an operational transconductance amplifier (OTA) operating from room temperature to 200 °C. A simulation model for the transistor was created using Verilog A language including a lookup table (LUT) with current response and capacitance data obtained from measurement of fabricated devices. Two OTA designs were made, for supply voltages (VDD) of 2.1 V and 1.5 V. The first design was analyzed at room temperature (25 °C) with different bias points that defined the transistors efficiency (gm/ID) of the first stage input differential pair and current mirror load. A comparison with other OTA projects using FinFET and Tunnel FET (TFET) devices was performed considering similar gm/ID for all designs. The GAA-NSH design presents a larger voltage gain than the FinFET design (71.8 dB vs. 67.6 dB), while consuming less power (544.5uW vs. 1.41mW) and utilizing smaller devices and an overall smaller area footprint. Improvements are a consequence of the superior gate electrostatic coupling of the GAA-NSH transistors that can be seen through the improved transconductance and output conductance values. Compared with the TFET device, the GAA-NSH presents a tradeoff between Bandwidth and power consumption. Finally, the second OTA designed is analyzed from room temperature to 200 °C, and a decrease of the voltage gain and GBW was observed due to the mobility degradation at high temperature.