Design Of Finite Impulse Response Research Articles

Design and Implementation of FIR Filters for Biomedical Applications

Abstract: Digital signal processing (DSP) greatly facilitates the continuous capture, monitoring, processing, and analysis of signals in real-world applications, particularly in biomedical or wearable devices. Within DSP systems, the design of Finite Impulse Response (FIR) filters is pivotal. In scenarios demanding intricate calculations and high precision, higher-order filters are employed. Multipliers are crucial components in filter design, consuming significant chip space and introducing extra computation overhead. Designers strive to optimize multipliers to enhance performance. In this project we are going to design pipelined based FIR filter by applying pipelining concept to the FIR filter and following the previous implementations such as the FIR filter with high accuracy compared to existing method. The proposed system architectures are known to be efficient for real signal processing, offering advantages over conventional based designs. The proposed design is anticipated to yield benefits in terms of area, power consumption, and timing performance. The synthesis and simulation of the existing and proposed designs are implemented using Cadence Virtuoso.

On the minimization of multiplier-adders for powers-of-two filter using a novel right to left (R2L) algorithm

The field of digital signal processing has been receiving increasing attention over the years because of its widespread applications in various fields of science, engineering and technology. In connection to this, design of finite impulse response (FIR) filter has drawn enough attention of researchers throughout the globe. A number of promising developments has been carried out over the last few decades which emphasize on the design of hardware efficient filter structure. In this work, one novel Right to Left (R2L) algorithm is proposed which can minimize the number of multiplier-adders for the powers-of-two FIR filter. The requirement of such adders essentially depends upon the number of such non-zero entries and the word-length of the input signal. Comparative study has been performed amongst few such hardware efficient realizations of digital filters. Finally, the proposed approach has been implemented using Xilinx Plan Ahead 14.7 so as to have a clear understanding about the requirement of different hardware blocks on a field programmable device.

The optimal design of repetitive controllers based on inverse frequency response

AbstractThis article presents a complete design of non‐causal finite impulse response (FIR) and infinite impulse response (IIR) compensators for repetitive control. The concept of repetitive controllers involves imitating the inverse frequency response of the feedback control system by minimizing the amplitude of error propagation from one period to the next in the frequency domain. The FIR compensator design has already been presented in our previous work. However, it was not complete since some parameters, such as the number of causal gains and total number of gains were still left open for the designers to select. This work provides a reasonable suggestion on how to choose parameters based on the steepest descent method. In addition, an IIR compensator is further developed based on the designed FIR design. The gains of the IIR compensator are adjusted by aiming to minimize the cost function using the steepest descent. As can be observed from the results, the IIR compensator developed from the FIR compensator cannot overcome the original FIR compensator since its learning performance is relatively slow and the extra gains added to the denominator increase memory usage when executing.

FIR Filter Design using Raised Semi-ellipse Window Function

In this paper, a new two-parameter window function - Raised semi-ellipse (RSE) is proposed. The window is obtained from a fixed elliptical window known as Semi-ellipse window by raising the radius of the minor axis by the parameter (β), and applied for the design of finite impulse response (FIR) digital filters. The spectral parameters of the proposed window are determined first and compared with the Kaiser window – a 2-parameter adjustable window. Subsequently, in its application in filter design with an established design algorithm, the newly proposed adjustable window is compared to the Semi-ellipse window to examine its improvement and also the Kaiser window to compare its performance with a commonly used adjustable window. The filter simulation results show that the filters designed with the proposed window can provide more reduced ripples than the Kaiser window for prescribed spectral characteristics.

Low power residue number system using lookup table decomposition and finite state machine based post computation

In this paper, memory optimization and architectural level modifications are introduced for realizing the low power <span lang="EN-US">residue number system (RNS) with improved flexibility for electroencephalograph (EEG) signal classification. The proposed RNS framework is intended to maximize the reconfigurability of RNS for high-performance finite impulse response (FIR) filter design. By replacing the existing power-hungry RAM-based reverse conversion model with a highly decomposed lookup table (LUT) model which can produce the results without using any post accumulation process. The reverse conversion block is modified with an appropriate functional unit to accommodate FIR convolution results. The proposed approach is established to develop and execute pre-calculated inverters for various module sets. Therefore, the proposed LUT-decomposition with RNS multiplication-based post-accumulation technology provides a high-performance FIR filter architecture that allows different frequency response configuration elements. Experimental results shows the superior performance of decomposing LUT-based direct reverse conversion over other existing reverse conversion techniques adopted for energy-efficient RNS FIR implementations. When compared with the conventional RNS FIR design with the proposed FSM based decomposed RNS FIR, the logic elements (LEs) were reduced by 4.57%, the frequency component is increased by 31.79%, number of LUTs is reduced by 42.85%, and the power dissipation was reduced by 13.83%.</span>

Design and implementation of pervasive DA based FIR filter and feeder register based multiplier for software definedradio networks

PurposeDigital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization.Design/methodology/approachThe distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324.FindingsThe MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively.Originality/valueThe MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.

Design of FIR filter ISOTA with the aid of genetic algorithm

The field of digital signal processing has been receiving justified attention over the years because of a number of reasons including sophisticated algorithms, high computational speed and wider area of applications. In connection to this, design of finite impulse response (FIR) filter has drawn the attention of researchers throughout the globe. A number of promising developments has been carried out over the last few decades which emphasize on the design of hardware efficient filter structure. In this paper, a new technique of FIR filter design has been addressed by virtue of genetic algorithm. Filter coefficients have been searched over the discrete space in such a way that the architecture consists of shifts and only two adders. As a matter of fact, the proposed FIR filter involving shift and only two additions (ISOTA) results in minimal hardware cost during its implementation. This has been illustrated by means of a few example filters in this work. Some of the recently proposed FIR ISOTA filters have also been taken for the purpose of comparison. Finally, the proposed filter has been implemented on Altera Cyclone IV FPGA board.

Windowing Techniques, the Welch Method for Improvement of Power Spectrum Estimation

This paper revisits the characteristics of windowing techniques with various window functions involved, and successively investigates spectral leakage mitigation utilizing the Welch method. The discrete Fourier transform (DFT) is ubiquitous in digital signal processing (DSP) for the spectrum analysis and can be efficiently realized by the fast Fourier transform (FFT). The sampling signal will result in distortion and thus may cause unpredictable spectral leakage in discrete spectrum when the DFT is employed. Windowing is implemented by multiplying the input signal with a window function and windowing amplitude modulates the input signal so that the spectral leakage is evened out. Therefore, windowing processing reduces the amplitude of the samples at the beginning and end of the window. In addition to selecting appropriate window functions, a pretreatment method, such as the Welch method, is effective to mitigate the spectral leakage. Due to the noise caused by imperfect, finite data, the noise reduction from Welch’s method is a desired treatment. The nonparametric Welch method is an improvement on the periodogram spectrum estimation method where the signal-to-noise ratio (SNR) is high and mitigates noise in the estimated power spectra in exchange for frequency resolution reduction. The periodogram technique based on Welch method is capable of providing good resolution if data length samples are appropriately selected. The design of finite impulse response (FIR) digital filter using the window technique is firstly addressed. The influence of various window functions on the Fourier transform spectrum of the signals is discussed. Comparison on spectral resolution based on the traditional power spectrum estimation and various window-function-based Welch power spectrum estimations is presented.

Design and optimisation of regression-type small phase shift FIR filters and FIR-based differentiators with optimal local response in LS-sense

The design of finite impulse response (FIR) filters and FIR-based differentiators is a popular topic in the field of digital signal processing. FIR filters/differentiators are characterised by a filtering architecture that does not include a feedback loop. Therefore, they are stable and have a relatively simple design, and most importantly, they can yield a filter with a linear phase diagram. Nevertheless, the FIR filter design methods reported in the scientific literature lead to a filter architecture that causes a transport delay or a nonlinear phase shift in the implementation environment. This limits the applicability of FIR filters/differentiators, e.g. in closed-loop control or real-time state estimation. In this paper, a method for FIR filter and FIR-based differentiator coefficient design is presented. The coefficients of the FIR filter and FIR-based differentiator are designed such that the FIR architecture results in a convolution leading to a locally optimal response in the least-squares sense. Thus, the FIR architecture response is characterised by an extremely small phase shift for the passband of the designed architecture. This feature results in a higher-order FIR architecture compared with the conventional design methods. In the proposed method, the delay caused by the FIR architecture is minimised by coefficient determination. Therefore, when the method is applied to a known FIR architecture, it causes a shorter delay than all other methods of coefficient determination.

Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy

To solve the area and power problems in Finite Impulse Response (FIR) implementations, a faithfully truncated adder-based FIR design is presented in this paper for significant area and power savings while the predefined output accuracy can still be obtained. As a solution to the accuracy loss caused by truncated adders, a static error analysis on the utilization of truncated adders in FIRs was performed. According to the mathematical analysis, we show that, with a given accuracy constraint, the optimal truncated adder configuration for an area-power efficient FIR design can be effortlessly determined. Evaluation results on various FIR implementations by using the proposed faithfully truncated adder designs showed that up to 35.4% and 27.9% savings in area and power consumption can be achieved with less than 1 ulp accuracy loss for uniformly distributed random inputs. Moreover, as a case study for normally distributed signals, a fixed 6-tap FIR is implemented for electrocardiogram (ECG) signal filtering was implemented, in which even with the increased truncated bits up to 10, the mean absolute error (Ē) can be guaranteed to be less than 1 ulp while up to 29.7% and 25.3% savings in area and power can be obtained.

Least squares linear phase FIR filter design and its VLSI implementation

In this work we present least squares (LS) approach to design linear phase Finite Impulse Response (FIR) filter. Since the design of FIR digital filters is non-analytic, we aim at ideal zero-phase magnitude response and minimize the weighted error in passband and stopbands. The problem of least squares can then be solved non-iteratively by solving system of linear equations. Solution of which yields impulse response that is both real and symmetric. Frequency response of the proposed LS FIR filter shows a flat passband, and higher stop-band attenuation than traditional window based FIR design and comparable attenuation with Parks–McClellan method of the same order. In addition we have implemented LS FIR filter on FPGA based VLSI architectures. Performance evaluation of proposed LS FIR design on VLSI architecture shows comparable throughput, area and power consumption compared to classical filter design approaches.

Feature Extraction for Transient Chemical Sensor Signals in Response to Turbulent Plumes: Application to Chemical Source Distance Prediction

This paper describes the design of a low-pass differentiator filter with linear phase and finite impulse response (FIR) for extracting transient features of gas sensor signals (the so-called “bouts”) which are relevant for accurately estimating the source-receptor distance in a turbulent plume. Our current proposal addresses the shortcomings of previous ‘bout’ estimation methods, namely: (i) they were based in non-causal digital filters precluding real time operation, (ii) they used non-linear phase filters leading to waveform distortions and (iii) the smoothing action was achieved by two filters in cascade, precluding an easy tuning of filter performance. The presented filter preserves the signal waveform in the bandpass region for maximum reliability concerning both bout detection and amplitude estimation. Thanks to its FIR design, the filter can be implemented with nonrecursive structures, thus being inherently stable and allowing an easy algorithmic implementation and optimization. As a case study, we apply the proposed filter to predict the source-receptor distance from recordings obtained with a metal oxide (MOX) gas sensor in a wind tunnel. We demonstrate that proper tuning of the proposed filter can reduce the prediction error to 8 cm (in a distance range of 1.45 m) improving previously reported performances in the same dataset by a factor of 2.5. The performance of bout-based features are also benchmarked against traditional source-receptor distance estimators such as the mean, variance and maximum of the response. We also study how the length of the measurement window affects the performance of different signal features and how to tune the filter parameters to make the predictive models insensitive to wind speed. A MATLAB implementation of the proposed filter and all analysis code used in this study is provided.

An Overview of FIR Filter Design in Future Multicarrier Communication Systems

Future wireless communication systems are facing with many challenges due to their complexity and diversification. Orthogonal frequency division multiplexing (OFDM) in 4G cannot meet the requirements in future scenarios, thus alternative multicarrier modulation (MCM) candidates for future physical layer have been extensively studied in the academic field, for example, filter bank multicarrier (FBMC), generalized frequency division multiplexing (GFDM), universal filtered multicarrier (UFMC), filtered OFDM (F-OFDM), and so forth, wherein the prototype filter design is an essential component based on which the synthesis and analysis filters are derived. This paper presents a comprehensive survey on the recent advances of finite impulse response (FIR) filter design methods in MCM based communication systems. Firstly, the fundamental aspects are examined, including the introduction of existing waveform candidates and the principle of FIR filter design. Then the methods of FIR filter design are summarized in details and we focus on the following three categories—frequency sampling methods, windowing based methods and optimization based methods. Finally, the performances of various FIR design methods are evaluated and quantified by power spectral density (PSD) and bit error rate (BER), and different MCM schemes as well as their potential prototype filters are discussed.

VLSI Implementation of Digital Filter using Novel RTSD Adder and Booth Multiplier

Finite Impulse Response (FIR) filters are most important element in signal processing and communication. Area and speed optimization are the essential necessities of FIR filter design. This work looks at the design of Finite Impulse Response (FIR) filters from an arithmetic perspective. Since the fundamental arithmetic operations in the convolution equations are addition and multiplication, they are the objectives of the design analysis. For multiplication, Booth encoding is utilized in order to lessen the quantity of partial products. Consequently, considering carry-propagation free addition strategies should improve the addition operation of the filter. The redundant ternary signed-digit (RTSD) number framework is utilized to speedup addition in the filter. The redundant ternary representation utilizes more bits than required to denote the single binary digit because of which most numbers have several representations. This special behavior of RTSD allows the addition along with the absence of typical carry propagation. Xilinx ISE design suite 14.5 is used for the design and validation of proposed method. From the implementation result, the proposed design of FIR filter is compared with other conventional techniques to show the better performance by means of power, area and delay.

An efficient design of finite impulse response — Fractional-order differentiator using shuffled frog leaping algorithm heuristic

A fractional-order digital differentiator is employed for the calculation of a time-derivative of the applied signal. In the recent few decades, this particular concept of a fractional derivative has been gaining a lot of attention in various applications concerning engineering, technology and science that includes image processing along with automatic control. Once there has been an effective use for this continuous-time Fractional-Order Differentiator (FOD), the trend in its research is primarily toward using a discrete-time fractional differentiator. All these conventional techniques tend to make use of a unimodal function for approximating an ideal FOD. For these techniques, there is a minimization of the fitness function that is accomplished by the algorithms which are based on the gradient. The fractional-order circuits along with their systems include an emerging area that has a high level of potential in aspects such as the biomedical instrumentation, control or signal processing. A digital differentiator is a tool that is extremely helpful in the determination and estimation of time derivatives of any given signal. Irrespective of the actual type of filter chosen (the Finite Impulse Response (FIR) or the Infinite-Length Impulse Response (IIR)), it is critical to bring down the complexity of computation needed for the implementation of the filter for a certain bandwidth and error of approximation. A metaheuristic algorithm normally has some advantages in the solving of problems which are Non-Deterministic Polynomial (NP)-hard. The Shuffled Frog Leaping Algorithm (SFLA) has been a new heuristic algorithm proposed in this work for the determination of optimal coefficients of the problem of FIR-FOD. A design for fractional-order-based digital differentiator is not a very important topic in research and signal processing.

A Novel Design of Sparse FIR Multiple Notch Filters with Tunable Notch Frequencies

We focus on the design of finite impulse response (FIR) multiple notch filters. To reduce the computational complexity and hardware implementation complexity, a novel algorithm is developed based on the mixture of the tuning of notch frequencies and the sparsity of filter coefficients. The proposed design procedure can be carried out as follow: first, since sparse FIR filters have lower implementation complexity than full filters, a sparse linear phase FIR single notch filter with the given rejection bandwidth and passband attenuation is designed. Second, a tuning procedure is applied to the computed sparse filter to produce the desired sparse linear phase FIR multiple notch filter. When the notch frequencies are varied, the same tuning procedure can be employed to render the new multiple notch filter instead of designing the filter from scratch. The effectiveness of the proposed algorithm is demonstrated through three design examples.

Design of Linear Phase High Pass FIR Filter using Weight Improved Particle Swarm Optimization

The design of Finite Impulse Response (FIR) digital filter involves multi-parameter optimization, while the traditional gradient-based methods are not effective enough for precise design. The aim of this paper is to present a method of designing 24th order high pass FIR filter using an evolutionary heuristic search technique called Weight Improved Particle Swarm Optimization (WIPSO). A new function of the weight parameters is constructed for obtaining a better optimal solution with faster computation. The performance of the proposed algorithm is compared with two other search optimization algorithms namely standard Genetic Algorithm (GA) and conventional Particle Swarm Optimization (PSO). The simulation results show that the proposed WIPSO algorithm is better than GA and PSO in terms of the magnitude response accuracy and the convergence speed for the design of 24th order high pass FIR filter.

Modified artificial bee colony optimisation based FIR filter design with experimental validation using field‐programmable gate array

Optimisation based design of finite impulse response (FIR) filters has been an active area of research for quite some time. The various algorithms proposed for FIR filter design aim at meeting a set of desired specifications in the frequency domain. Evolutionary algorithms have been found to be very effective for FIR filter design because of the non-linear, non-differentiable and non-convex nature of the associated optimisation problem. The present work proposes two modified versions of a recently developed evolutionary technique i.e. artificial bee colony (ABC) algorithm for design of FIR filters. The applicability of the proposed approach has been evaluated by comparing its response with conventional reported filter design techniques. The proposed variants of ABC are found to outperform other non-convex algorithms in achieving the desired specifications. In addition to the simulation results, the designed filters have been implemented in hardware using Xilinx-xc7vx330t-3ffg1157 (Virtex-7) field programmable gate array. The hardware implementation allows validation of the proposed techniques for practical filtering applications by considering real time operation parameters.

Design of fir filters using exponential--Hamming window family

In this paper, a new two-parameter window obtained by the combination of two windows, known as exponential and Hamming, is proposed and applied for the design of finite impulse response (FIR) digital filters. First of all, the quality of the proposed window is analyzed in terms of window spectral parameters and then compared with other two-parameter windows, namely Kaiser, cosh, and exponential. The window simulation results show that the proposed window can provide better ripple ratio than other windows for fixed window length and mainlobe width. Secondly, the performance of the proposed window is analyzed in digital filter design. The filter numerical comparison with Saramaki, Kaiser, Dolph–Chebyshev, cosh, and exponential windows confirms that the filter designed by the proposed window can exhibit a better filtering performance compared to well-known two-parameter windows in the literature because it can provide better minimum stopband attenuation for fixed filter length and transition width.

A Standard-Cell-Design-Flow Compatible Energy-Recycling Logic With 70% Energy Saving

This paper presents an energy-recycling micro-architecture and the associated adiabatic logic for ultra-low energy applications, such as implantable bioelectronics. The proposed design achieves low power by transferring and recycling energy between digital logic blocks along with the signal propagation. The CMOS-like layout methodology allows the adiabatic logic core to be synthesized and auto-placed-and-routed with current EDA tools for complex digital systems. A 50% energy saving can be achieved for up to 100 MHz compared to conventional static CMOS logic. As a proof of concept, a 14-tap 8-bit finite impulse response (FIR) filter has been implemented in 90-nm CMOS for implantable neural signal processing. With only 16% area overhead compared to the static CMOS counterpart, the proposed design achieves 70% to 53% of energy reduction for 87 kHz to 410 kHz from a 1 V supply. The FIR filter realized with the proposed energy-recycling logic achieves an FoM of 5.33 nW/MHz/Tap/In-bit/Coeff-bit, yielding a 1.9 $\times$ to 42 $\times$ higher energy efficiency than the state-of-the-art custom energy-efficient FIR designs.