Digital Signal Processing Design Research Articles

ASIP Performance Enhancement by Hazard Control through Scoreboard

The application-specific instruction set processor (ASIP) has been gradually accepted in AI, communication, media, game and industry control. The digital signal processor (DSP) is a typical ASIP, whose benefits include high performance in specific domains, low power consumption, high flexibility and low silicon consumption. One of the challenges for DSP design is to handle problems induced by datapath acceleration. The datapath acceleration (instruction fusion, black box instructions) induces control complexities. To most efficiently utilize hardware, control challenges can be summarized as RAW (Read-After-Write) handling, hardware hazard handling, and WAW (Write-After-Write) handling. Both an advanced compiler and hardware hazard handler can be used as solutions. In this paper, we introduced both solutions and exposed the benefits from the hardware solution. The benefits include utilizing low silicon to achieve higher performance and program memory reduction on chip. In summary, our solution only uses 0.91% extra silicon area yet achieves 32.75% performance improvement. So, the overall performance-to-cost ratio could be evaluated as 32%.

Learnable digital signal processing: a new benchmark of linearity compensation for optical fiber communications

The surge in interest regarding the next generation of optical fiber transmission has stimulated the development of digital signal processing (DSP) schemes that are highly cost-effective with both high performance and low complexity. As benchmarks for nonlinear compensation methods, however, traditional DSP designed with block-by-block modules for linear compensations, could exhibit residual linear effects after compensation, limiting the nonlinear compensation performance. Here we propose a high-efficient design thought for DSP based on the learnable perspectivity, called learnable DSP (LDSP). LDSP reuses the traditional DSP modules, regarding the whole DSP as a deep learning framework and optimizing the DSP parameters adaptively based on backpropagation algorithm from a global scale. This method not only establishes new standards in linear DSP performance but also serves as a critical benchmark for nonlinear DSP designs. In comparison to traditional DSP with hyperparameter optimization, a notable enhancement of approximately 1.21 dB in the Q factor for 400 Gb/s signal after 1600 km fiber transmission is experimentally demonstrated by combining LDSP and perturbation-based nonlinear compensation algorithm. Benefiting from the learnable model, LDSP can learn the best configuration adaptively with low complexity, reducing dependence on initial parameters. The proposed approach implements a symbol-rate DSP with a small bit error rate (BER) cost in exchange for a 48% complexity reduction compared to the conventional 2 samples/symbol processing. We believe that LDSP represents a new and highly efficient paradigm for DSP design, which is poised to attract considerable attention across various domains of optical communications.

Development of a high-performance arithmetic and logic unit for efficient digital signal processing based on reversible logic and quantum dots

Digital Signal Processing (DSP) finds a wide range of applications in various fields, including telecommunications, audio and video processing, biomedical engineering, radar systems, and image processing. Previous DSP designs faced limitations in available processing power and computational resources. Insufficient processing power could result in slower execution times, an inability to handle complex algorithms, or limited capacity to process high-speed or large-scale signals. As the demand for minimal power consumption in DSP circuits continues to grow, reversible logic and quantum-dot cellular automata (QCA) have emerged as promising technologies due to their inherent ability to reduce energy loss. Within this landscape, the arithmetic and logic unit (ALU) plays a vital role in complex circuitry, serving as a key component in digital signal processing applications. However, challenges persist, including high quantum cost and the need to limit the number of cells in the ALU design. To address these challenges, our research aims to develop an efficient ALU by integrating reversible logic and QCA technology. Our focus will be on generating essential components, such as Feynman gates, Fredkin gates, and full adder circuits, which serve as foundational building blocks for reversible logic and QCA designs. These components will be combined to construct a comprehensive ALU capable of performing 20 different operations. Our implementation efforts will be centered around QCADesigner, with a specific emphasis on digital signal processing systems that prioritize energy efficiency and optimal utilization of occupied areas.

Power-aware high-capacity elastic optical networks

The power consumption of telecommunication equipment has been identified as a relevant contributor to global energy consumption. In fact, new-generation optical transponders employ power-intensive electronic application-specific integrated circuits (ASICs) for digital signal processing (DSP). DSP design has traditionally prioritized meeting transmission requirements over power consumption optimization. In general, the evolutions of transmission techniques and network design have always been mainly driven by traffic increase; in this context, in order to operate network resources more efficiently, margin reduction has been investigated in the past few years. Indeed, traditionally, high physical layer margins are used to ensure reliability over an extended period, resulting in overprovisioning the optical connections for both physical layer conditions and capacity. On the other hand, super-channels have emerged as a suitable solution for accommodating the continuous traffic growth. However, power consumption has not been deeply considered in the optimization of super-channel transmission. This paper first investigates the power efficiency of super-channels operated with designed and reduced margins. Low-margin operation is enabled by adapting sub-carrier spacing and filter bandwidth. Power-aware super-channel optimization is then experimentally demonstrated leveraging a 600 Gbit/s transponder in the SDN-controlled elastic optical network (EON). The results have identified a trade-off between power consumption and spectrum efficiency. Furthermore, the ongoing bandwidth demand has motivated the investigation of multi-band (MB) transmission for scaling the capacity of the existing infrastructures. However, novel networking devices (e.g., optical amplifiers operating beyond the C- and L-bands) will affect the overall power consumption. In this context, experimental power analysis of a thulium doped fiber amplifier (TDFA) is performed based on the traffic load and corresponding configuration. The results show that TDFA power consumption varies with configuration and increases with output power.

Exploring unified biometrics with encoded dictionary for hardware security of fault secured IP core designs

This paper presents a novel methodology to explore unified biometrics with encoded dictionary for hardware security of fault secured digital signal processing (DSP) intellectual property (IP) core designs against piracy. The proposed security approach exploits scheduled and allocated DSP design using behavioral synthesis process to generate a fault secured DSP IP core. Since the fault secured IP designs are susceptible to threats of piracy, therefore the proposed technique embeds encoded unified biometric based hardware security constraints into the design to provide detective control against IP piracy. This result into generation of protected fault secured DSP designs against IP piracy thereby ensuring the safety of end consumers against pirated and non-reliable designs. The offered security strength and design cost of the proposed approach exhibits significantly higher strength of digital evidence ensuring assured piracy detection and higher strength against regenerating unified biometric driven hardware security constraints than recent approaches.

Analysis of International Trade Competitiveness of Small Commodities Based on Numerical Simulation Algorithm

In order to improve the analysis effect of the international trade competitiveness of small commodities, this study combines the digital simulation algorithm to analyze the competitiveness of international trade of small commodities and builds a competitiveness analysis model. Furthermore, this study summarizes several main factors that affect energy resolution, presents methods to provide energy resolution, and discusses methods for reducing noise from both analog and digital perspectives. In addition, this study gives the design principle and implementation method of the FIR digital filter, which provides theoretical support for digital signal processing design. Through the data analysis, it can be seen that the analysis model of the international trade competitiveness of small commodities based on the numerical simulation algorithm proposed in this study has a good performance in the analysis of the competitiveness of international trade of small commodities.

A High-Performance On-Chip Memory Module for Image Processing Applications

Abstract: To actualize numerous image processing applications, today's technology revolution in portable electronic devices necessitates significant amounts of data processing power, area, and time. Approximate data computing has been demonstrated to be a viable solution for picture processing. In real-time digital data computing applications, achieving high precision or fulfilling a variable accuracy requirement of up to 100 percent has become a crucial design goal. As a result, very large-scale integration (VLSI) architectures with excellent performance are critical in the design of digital signal processors. The use of high-performance adders and on-chip memory structures has also been a focus of recent breakthroughs in processor design Stability and dependability are crucial design factors that contribute to a reduction in worst-case error and the use of a hybrid application in real time. High precision, high speed, low power, and area efficiency are achieved by balancing the restrictions of high performance. The processor core's performance is determined by the configuration, design parameters, and efficient use of the data channel and on-chip memory structures. As a result, high-performance adders and on-chip memory architecture were used in this study. To provide superior quantitative computation for human perception, the suggested design is included into image processing applications such as image approximation, canny edge detection, and noise reduction approaches. Berkeley, medical, and satellite image samples were used..

Undergraduate Curriculum to Teach and Provide Research Skills on Hardware Design for SDR Applications in FPGA Technology

Software Defined Radio (SDR) technologies play today an important role in modern wireless networks due to their flexibility to implement re-configurable hardware designs. In light of the importance to operate and develop such technologies, academic programs in the communications engineering field demand an introduction to Digital Signal Processing (DSP) and SDR communication schemes accordingly. Typically, the teaching of this subject is afforded through projects and hands-on activities in classrooms. However, provided their relevance in the current state-of-the-art, this topic also provides a framework to teach soft skills concerning research abilities in students. This paper introduces an academic program to the development of SDR functionality as well as research skills based on exposure to state-of-the-art research. Through projects, hands-on activities are conducted to teach digital signal processing designs using Field Programmable Gate Array (FPGA) technology. The course aims to develop technical skills to implement communication system blocks. Besides, workshops and seminars are prepared to support the development of research and communication skills. The proposed course is flexible to incorporate on a given academic program as an elective subject to further support topics related to communication theory and discrete-time signals. Learning outcomes are designed to develop enhanced technical skills in SDR design and simultaneously a critical discussion of the devised solutions in light of the state-of-the-art. Also, skills related to identifying, formulating, and discussing engineering problems are further reinforced. Results from supported projects developed in the classroom exhibit completed assignments superior to 90% of participant students. Learning objectives concerning the technical skills were successfully covered (90%) in comparison to research and communicating skills (80%). Additionally, research skills and the ability to disseminate knowledge gradually improved in seminars. Finally, results of the current course exhibit improvements of 25% regarding the acquired skills in digital signal processing in comparison to previous courses.

Design of digital signal processor based adaptive beamformer using hybrid residual least mean square algorithm for improved performance

This paper proposes a novel hybrid residual least mean square (HRLMS) algorithm for adaptive filtering followed by an antenna beamformer using 16-element linear array. The hybridization process involves a switching between the residual-LMS (RLMS) and the conventional-LMS (CLMS) algorithms after the eighth iteration, if the square errors for four consecutive iterations are less than a threshold. The novelty of HRLMS lies in estimating best step size factor through residuals for speedy convergence followed by the CLMS switching for minimum steady state error (SSE). The novelty also includes in realizing a real-time antenna beamformer with significant sidelobe level (SLL) reduction and improved interference nulling by integration of HRLMS and space selective digital filter (SSDF). The adaptive filter and smart beamformer, based on HRLMS and HRLMS-SSDF have been implemented on TMS320VC5416 digital signal processor. The comparative performance evaluation of HRLMS has been done for convergence speed, SSE, interference nulling and SLL reduction with the existing variable step size LMS (VSSLMS) algorithms. The iteration count for convergence has been reduced by about 50% with paltry additional computational burden over the other VSSLMS algorithms. The HRLMS-SSDF provide attenuations of about 76, 33, and >50 dB, respectively for interfering signals, first SLL and higher order SLLs of beamformer.

High‐performance DSP platform for digital hearing aid SoC with flexible noise estimation

Flexibility and programmability of hearing aids are important because the algorithms applied to hearing aids should be changeable based on different types of hearing impairment and the ambient environment of the user. This paper proposes a high-performance digital signal processing (DSP) platform for a digital hearing aid system on a chip (SoC) with flexible noise estimation. The proposed DSP platform comprises several dedicated accelerators and an application-specific instruction-set processor (ASIP) to achieve flexibility. To handle complex hearing aid algorithms in real time, the main algorithms of hearing aids are executed by hardware accelerators and only environment-sensitive parts of the applied algorithms are implemented as the ASIP. Simulation results show that the proposed DSP platform can handle complex and high-performance algorithms in real time, and that it provides better quality in terms of noise handling by adapting the noise estimation algorithms suitable for the noise environment. The chip area of authors’ DSP design is 2.71 mm2, and it consumes 1.3 mW at 1 V operation, 8 MHz clock frequency with a 65 nm high threshold voltage (HVT) standard cell library.

Low‐cost robust anti‐removal logic for protecting functionally obfuscated DSP core against removal attack

Digital signal processing (DSP) cores (kernels) are key components of modern consumer electronics devices. However, protection of DSP kernels is very crucial considering its vulnerability to hardware threats such as reverse engineering (RE). Functional obfuscation is one of the security mechanisms which provide protection against RE. However, functional obfuscation logic is in itself vulnerable to removal attack. This Letter presents a novel anti-removal logic (ARL) unit which ensures protection against the removal attack on functional obfuscation logic. Further, the ARL unit is itself safeguarded against removal attack by incorporating design architecture customisation and camouflaging. Designer can customise and camouflage the internal gate structure network of the ARL blocks post-synthesis (post-mapping and fitting). The proposed ARL unit integrated with functionally obfuscated DSP design, yielded lightweight and highly secured solution against removal attack when compared to an existing approach. The proposed approach reported on an average 42.57% reduction in gate count and on an average 66.67% enhancement in security compared to a recent existing approach.

Protecting DSP Kernels Using Robust Hologram-Based Obfuscation

Digital signal processing (DSP) kernels-based intellectual property cores are important components of modern consumer electronics. However, hardware threats such as reverse engineering and Trojan insertion have raised serious concerns about the protection of DSP kernels. Structural obfuscation is one of the protection mechanisms that make DSP design architecture un-obvious to interpret, thereby making it harder to reverse engineer. A novel methodology is presented in this paper called “hologram-based structural obfuscation” for protection of DSP kernels. The proposed hologram-based obfuscation integrates two DSP kernel architectures in a camouflaged fashion without change of functionality of each DSP kernel, such that it becomes complex and un-interpretable to an adversary. This approach of simultaneous protection of two DSP kernels via hologram obfuscation is presented first time in the literature. We propose multiple robust obfuscation algorithms in this paper to design hologram-based obfuscated designs and demonstrate using popular DSP kernels. Proposed approach is compared with a recent work on protecting DSP kernels and experimental results indicate that proposed approach yields significantly lesser area and stronger obfuscation. Results of proposed obfuscation on DSP kernels achieve approximately 33.5% reduction in gate count and ~14 times stronger obfuscation than recent work.

Security of Functionally Obfuscated DSP Core Against Removal Attack Using SHA-512 Based Key Encryption Hardware

Digital signal processing (DSP) kernel-based intellectual property (IP) core forms an integral ingredient of consumer electronics devices. Thus, protection of these IP cores against reverse engineering attack is crucial. Functional obfuscation serves as a powerful mechanism to counter this hardware threat. However, functional obfuscation methodologies for DSP cores use security logics that are not lightweight and are prone to removal attack by an adversary. This paper presents a novel security mechanism for protecting functionally obfuscated DSP core against removal attack using low-cost, low-power key encryption hardware. The proposed methodology using lightweight secure hashing algorithm (SHA-512)-based key encryption custom hardware reconfigures the key-bits (resulting into structural reconfiguration) of the locking logic in a functionally obfuscated DSP design augmented with the complete logic synthesis of the design. This hinders the detection of the locking logic in the obfuscated design due to camouflaging. The proposed mechanism integrated with the functional obfuscation framework yielded lower power, lower gate count, and enhanced security compared with an existing approach. An average reduction of 25.86 % in gate count and power as well as the average enhancement of 43.75 % in security against removal attack was obtained in the proposed approach compared with a recent existing approach.

Analytical Solution of Stage-Dependent Bit Resolution of Full Parallel Variable Point FFTs for Real-Time DSP Implementation

Digital signal processing (DSP) is a major driving force for cost-effectively realizing “software-defined anything” required by future converged networks. The fast Fourier transform (FFT) is a fundamental building block of an overwhelming majority of those DSP algorithms. For practical real-time implementation, the logic resource usage reduction of FFT operations is critical for considerably decreasing the hardware cost and power consumption. In this paper, a simple and effective solution of stage-dependent minimum bit resolution of full parallel variable-point FFTs is analytically derived, for the first time, whose validity and robustness are rigorously verified, both numerically and experimentally, over intensity modulation and direct detection optical orthogonal frequency-division multiplexing transmission systems. The developed solution has unique advantages including great simplicity, excellent accuracy and robustness, and significant saving in logic resource usage. The solution can ease the practical real-time FFT DSP design, decrease the DSP complexity, and maximize the overall system performance by making full use of available transceiver/system design parameters.

Multi-Phase Obfuscation of Fault Secured DSP Designs With Enhanced Security Feature

Digital signal processing (DSP) cores are an integral part of consumer electronics devices. This paper presents a novel methodology for obfuscation of transient fault secured circuits. The approach presented obfuscates fault secured DSP circuits such that the functions of the resulting hardware become non-obvious to an adversary (hindering reverse engineer process). The proposed methodology employs hybrid transformations in succession such as redundant operation removal, resource transformation, and connectivity change using tree height transformation, logic transformation, etc. These are achieved without affecting the functionality of the underlying DSP circuits or requiring significant increase in silicon footprint. The proposed methodology integrates an enhanced fault security feature using multi-cuts that ensures maximum detection capability against transient faults in the DSP circuit. Results of proposed approach indicate stronger obfuscation and enhanced fault security at lower design cost (avg. reduction ~14%), compared to prior art.

Design and Analysis of Hybrid Tree Multipliers for Reduction of Partial Products

This paper confers one of the three phases of tree multipliers, i.e. the Partial Product reduction phase. In this paper four types of hybrid tree multipliers are studied and proposed using parallel counters (full adders and half adders) for reduction of Partial Products in multiplication operation.After ANDing the bits of multiplier and multiplicand, the Partial Products are arranged into two groups for reduction, each group uses a different technique for reduction of Partial Products, resulting in a fewer gates than the parent tree reduction techniques. The results of the proposed tree reduction techniques are then tabulated and compared with the parent tree multipliers. The performance comparison is done in terms of number of gate counts of half adder and full adders used in the Partial Product reduction phase. Four types of hybrid tree multipliers are presented using CSA (Carry Save Adder) Array multiplier, Wallace Tree multiplier, Modified Wallace Tree multiplier and Dadda Tree Multiplier. The results show significant reduction in number of full adders and half adders with the slight overhead of increased final addition stage of the hybrid multiplier. The proposed multipliers can prove to be the better choice for digital signal processing designs, image processing designs and processor architecture.

DSP design protection in CE through algorithmic transformation based structural obfuscation

Structural obfuscation offers a means to effectively secure through obfuscation the contents of an intellectual property (IP) cores used in an electronic system-on-chip (SoC). In this work a novel structural obfuscation methodology for protecting a digital signal processor (DSP) IP core at the architectural synthesis design stage. The proposed approach specifically targets protection of IP cores that involve complex loops. Five different algorithmic level transformation techniques are employed: loop unrolling, loop invariant code motion, tree height reduction/increment, logic transformation and redundant operation removal. Each of these can yield camouflaged functionally equivalent designs. In addition, low cost obfuscated design is generated through proposed approach through the use of multi-stage algorithmic transformation and particle swarm optimization (PSO)-drive design space exploration (DSE). Results of proposed approach yielded an enhancement obfuscation of 22 % and reduction in obfuscated design cost of 55 % compared to similar prior art.

An approach to build cycle accurate full system VLIW simulation platform

Very long instruction word (VLIW) architecture is widely used in the design of digital signal processors (DSPs) and application-specific processors because of its hardware simplicity and high efficiency. Some heterogeneous systems also use VLIW style accelerators to achieve high computing performance and power efficiency. However, there are few widely accepted simulators that can cycle-accurately model a VLIW architecture or simulate the entire heterogeneous system with VLIW accelerators. In this paper we present an approach to build cycle accurate full system VLIW simulation platform. The basic idea is to analyze Petri Nets modeling used in the traditional cycle accurate simulation and adjust it to match VLIW architecture. The adjustments reconstruct and optimize the colored token, the place and the arc in Petri Nets in order to adapt it with VLIW characteristics. According to our approach and based on the InOrder simulator in the open source simulator framework Gem5, we build a heterogeneous multicore full system simulator for the MaPU (Mathematical Processor Unit) chip, which is composed by a functional accurate ARM simulator and a cycle accurate accelerator simulator. To evaluate the performance and accuracy of our simulator ‘Gem5-MaPU’, we compare the results of a set of DSP benchmarks executed by both the simulator and the RTL model. The result shows our simulator is about 1000 times faster than the RTL model while the cycle error is reduced to less than 5%. With high accuracy rate and good accelerating ratio over RTL simulation, the cycle accurate simulator turns out to be an efficient and flexible tool for VLIW related architectures’ study and development, such as the hardware-software co-design and performance evaluation, etc.

Exploiting Serial Access and Asymmetric Read/Write of Domain Wall Memory for Area and Energy-Efficient Digital Signal Processor Design

In many digital signal processing (DSP) applications, static random access memory (SRAM) based embedded memory and flip-flop based shift registers consume a significant portion of area and power. These DSP units are dominated by sequential memory access where SRAM-based memory or flip-flop based shift registers are inefficient in terms of area and power. We propose spintronic domain wall memory (DWM) based embedded memories for DSP building blocks such as survivor-path memories and last-in first-out (LIFO) in Viterbi decoder, first-in-first-out (FIFO) register files in FFT processor and bitonic sorter, and input register of distributed arithmetic (DA) based FIR filter that exploit the unique serial access mechanism, non-volatility and small footprint of the memory for area and power saving. Simulations using 65 nm technology show that the DWM based design achieves significant area and power savings over the conventional SRAM and spin-transfer-torque RAM (STTRAM) based design approach. For 8 k-point FFT processor and Viterbi decoder, the DWM-based design shows 60.6% (8.4%) and 66.4% ( $-$ 1.7%) area and 60.3% (44.3%) and 60.0% (37.8%) power savings over the conventional SRAM (STTRAM) based design, respectively. For DA-based FIR filter, it achieves 15.7% area and 15.5% power savings over shift register based design.

Digital Signal Processing for Training-Aided Coherent Optical Single-Carrier Frequency-Domain Equalization Systems

In this paper, we present the design of digital signal processing (DSP) algorithms for training-aided coherent optical single-carrier frequency-domain equalization (SC-FDE) systems. Based on two training-aided channel estimation (TA-CE) schemes, the requirements for training sequence to achieve the minimum mean square error performance of channel estimation (CE) are outlined. Moreover, the practical implementation issues of constant-amplitude zero-autocorrelation sequence and Golay sequences are discussed. We propose to perform time-domain windowing to the CE taps for further noise suppression to improve the CE and achieve large overhead saving with the optimized CE. Furthermore, frame timing synchronization and frequency offset compensation algorithms based on Golay sequences are developed, which provide bandwidth-efficient solution with robust performance for long-haul transmission. Finally, a low-complexity fractionally spaced frequency-domain equalizer is reported to effectively reduce the computational complexity of the whole system. A total of 28-Gbaud coherent polarization division multiplexing (PDM) system simulations and 10-Gbaud coherent PDM system experiments are conducted to verify that the proposed DSP solutions provide robust performance and are suitable for implementation in high-speed long-haul digital coherent receivers.