Design Methodology For Logic Circuits Research Articles

Real parallel and constant delay logic circuit design methodology based on the DNA model-of-computation

DNA is known as the building block of live organisms for storing the life codes and transferring the genetic features through the generations. However, it is found that DNA strands can be used for a new kind of computation. DNA computation proposes a new level of impressive degree of parallelism that is not feasible with conventional electronic computers. However, available computational models cannot be used for massive parallelism in DNA computing and new computation models and techniques should be developed.In this paper, a new computational model and methodology is proposed to use the massive parallelism of DNA-based circuits. In the proposed model, billions of DNA strands are utilized to compute the elements of the Boolean function concurrently to reach a high level of parallelism. Simulation and analytical results prove the feasibility and efficiency of the proposed method. Moreover, analyses and results show that delay of a circuit in this method is independent from the complexity of the function and each Boolean function can be computed with O(1) time complexity.

A Novel Reconfigurable Sub-0.25-V Digital Logic Family Using the Electron-Hole Bilayer TFET

We propose and validate a novel design methodology for logic circuits that exploits the conduction mechanism and the presence of two independently biased gates (“n-gate” and “p-gate”) of the electron-hole bilayer tunnel field-effect transistor (EHBTFET). If the device is designed to conduct only under certain conditions, e.g., when $V_{\mathrm {n-gate}} = V_{\mathrm {DD}}$ and $V_{\mathrm {p-gate}} = 0$ , it then shows an “XOR-like” behavior that allows the implementation of certain logic gates with a smaller number of transistors compared to conventional CMOS static logic. This simplifies the design and possibly results in faster operation due to lower node capacitances. We demonstrate the feasibility of the proposed EHBTFET logic for low supply voltage operation using mixed device/circuit simulations including quantum corrections.

1 /spl mu/m MOSFET VLSI technology. III. Logic circuit design methodology and applications

For pt. II see ibid., vol.SC14, no.2, p.247 (1979). Logic circuits were designed and fabricated in a 1 /spl mu/m silicon-gate MOSFET technology. First, conventional random logic chip images using the largely one-dimensional `Weinberger' layout are examined. The image is able to provide chips with an average circuit delay of 3 ns at the 8000 circuit level of integration. Second, two forms of PLA and PLA-based macros are discussed. A dynamic PLA, used in a microprocessor cross section and including 105 product terms, which achieves a 56 ns cycle time is described. A static PLA, designed for 21-ns delay and achieving measured delays from 13 to 21 ns, is also described. Extensions, particularly into low-temperature operation, are discussed.

1 µm MOSFET VLSI technology: Part III—Logic circuit design methodology and applications

Logic circuits were designed and fabricated in a 1 µm silicon-gate MOSFET technology. First, conventional random logic chip images using the largely one-dimensional "Weinberger" layout are examined. The image is able to provide chips with an average circuit delay of 3 ns at the 8000 circuit level of integration. Second, two forms of PLA and PLA-based macros are discussed. A dynamic PLA, used in a microprocessor cross section and including 105 product terms, which achieves a 56 ns cycle time is described. A static PLA, designed for 21- ns delay and achieving measured delays from 13 to 21 ns, is also described. Extensions, particularly into low-temperature operation, are discussed.