DES Implementation Research Articles

A study and comparison of the various cryptography technique standards within fifteen factors

This paper focuses on analyzing the performance of various encryption algorithms, namely RSA, ECC, and DSA, in terms of encrypting and decrypting sensitive data. Encryption is crucial for ensuring the security of data, and there are two types of encryption algorithms: Symmetric key and Asymmetric-key encryption. RSA is highly secure but has high computation time, whereas ECC provides equivalent security with lower computing power and battery usage. The study compares the implementation and analysis of DES, 3DES, AES, RSA, ECC, and DSA, highlighting their strengths and weaknesses. The paper aims to provide a comprehensive comparison of these cryptographic techniques, including their performances, to assist in selecting the most appropriate algorithm for specific applications.

Hybrid Code Lifting on Space-Hard Block Ciphers

There is a high demand for whitebox cryptography from the practical use of encryption in untrusted environments. It has been actively discussed for two decades since Chow et al. presented the whitebox implementation of DES and AES. The goal is to resist the key extraction from the encryption program and mitigate the code lifting of the program. At CCS2015, Bogdanov and Isobe proposed space-hard block ciphers as a dedicated design of whitebox block ciphers. It ensures that the key extraction is as difficult as the key recovery in the standard blackbox model. Moreover, to mitigate code lifting, they introduce space hardness, a kind of leakage-resilient security with the incompressibility of a huge program. For space-hard ciphers, code lifting (a partial leakage of the entire program) is useless to copy the functionality.In this paper, we consider a new attack model of space-hard block ciphers called hybrid code lifting. Space-hard block ciphers are intended to ensure security under a size-bounded leakage. However, they do not consider attackers (in the standard blackbox model) receiving the leakage by code lifting. If such attackers can recover the encryption program of a space-hard block cipher, such a cipher does not always satisfy the intention. We analyze Yoroi proposed in TCHES 2021. We introduce the canonical representation of Yoroi. Using the representation enables the recovery of the programs of Yoroi-16 and Yoroi-32 with 233 and 265.6 complexities, respectively, in spite of slight leakage. The canonical representation causes another attack against Yoroi. It breaks an authors’ security claim about the “longevity”. We additionally analyzed SPNbox proposed in Asiacrypt 2016. As a result, considering security on the hybrid code lifting, the original number of rounds is insufficient to achieve 128-bit security under quarter-size leakage.

Template Attack Assisted Linear Cryptanalysis on Outer Rounds Protected DES Implementations

Abstract In practice, when the security of a block cipher implementation is considered, the leakages related to the outer rounds encryptions can be used by side channel attacks (SCA) to recover the secret key. Therefore, the outer rounds of block cipher implementations should be protected. However, in order to lower the implementation price, the inner rounds of block cipher implementations may be unprotected. In light of this, the security of an outer rounds protected DES implementation is considered. In detail, template attack (TA), which is information theoretically the strongest SCA style, can be used to obtain the inner round output. Then, linear cryptanalysis (LC) can be used to recover the secret key. Finally, the optimal key enumeration algorithm can be used to optimize the efficiency of TA assisted LC. We evaluate the efficiency of TA assisted LC in simulated scenarios where a three outer rounds protected DES implementation is targeted. The evaluation results show that when 800 correct samples are available and the number of key enumeration is $2^{10}$, the efficiency of TA assisted LC can reach 83% of success rate. Overall, an efficient combination attack style that can be used to accurately evaluate the security of an outer rounds protected DES implementation is proposed.

A White-box Implementation of SEED

White-box cryptography is an implementation technique in order to protect secret keys of cryptographic algorithms in the white-box attack model, which is the setting that an adversary has full access to the implementation of the cryptographic algorithm and full control over their execution. This concept was introduced in 2002 by Chow et al., and since then, there have been many proposals for secure implementations. While there have been many approaches to construct a secure white-box implementation for the ciphers with SPN structures, there was no notable result about the white-box implementation for the block ciphers with Feistel structure after white-box DES implementation was broken. In this paper, we propose a secure white-box implementation for a block cipher SEED with Feistel structure, which can prevent the previous known attacks for white-box implementations. Our proposal is simple and practical: it is performed by only 3,376 table lookups during each execution and the total size of tables is 762.5 KB.

A high-performance and energy-efficient exhaustive key search approach via GPU on DES-like cryptosystems

Recently, graphical processing units (GPUs) have found a prominent role in general-purpose applications. Specifically, in parallel processing applications where a considerable number of tasks should be processed while meeting specific design constraints. One of the most interesting subjects in this area is cipher breaking via brute-force attacks, which attracts the attention of many researchers to the field. In this paper, we introduce a novel exhaustive key search approach for block cipher cryptosystems. The key point is how to utilize the single instruction multiple thread architecture to improve the speed of the DES-like hardware-based cryptosystems. At first, the standard DES core is implemented while all operations like bit permutation, swapping, and general hardware data stream follow the original algorithm. Then, in order to maximize the usage of the memory bandwidth and to eliminate the bit access penalty in GPU architecture, we exploit the register permutation and swapping (instead of the conventional bit swapping) in our implementation. In this approach, each thread examines a set of 32 keys per each iteration and hence a considerable throughput is achieved. The experimental results demonstrate 24K $$\times $$ , 800 $$\times $$ , and 400 $$\times $$ speed up over the traditional DES implementation on single-core CPU, the best previous work on multi-core CPU, and the conventional implementation on GPU, respectively. Furthermore, we measure the power and energy consumption of the best GPU and CPU approaches, where the GPU implementation proves to be more power efficient.

Implementation of DES and AES Cryptographic Algorithms in Accordance with Cloud Computing

Implementation of DES and AES Cryptographic Algorithms in Accordance with Cloud Computing

Pipelining Concept for Low Power DES Implementation

Pipelining Concept for Low Power DES Implementation

Реалізація криптографічних алгоритмів на основі ПЛІС для цифрових розподілених систем

This paper presents a single chip efficient FPGA implementation of RSA and DES for Digital Envelope Scheme that targets the Altera Apex 20KE EP20k200EBC356. Implementation of cryptographic algorithms on programmable devices like FPGAs run much faster than on software while preserving physical security of hardware solutions. The high throughput in the implementation of cryptographic algorithms for digital envelope scheme is achieved by means of exploiting the parallelism present in the DES and RSA operations as well as the features of Altera Apex 20KE device family which best suit for system-on-a-programmable-chip (SOPC) applications. The parallelized single chip implementation of DES and RSA for performing the Encryption/Decryption for the Digital envelope scheme offers a throughput of 3.5 Gbits/sec at a system clock rate of 54.7 MHz. This implementation even provides a means for using the DES and RSA separately.

Second Generation DES: Better Option in Treatment ISR

The development of an effective strategy for treatment of in-stent restenosis after BMS placement has been found to be extremely complicated. The therapeutic purpose for many patients is achieved with the implantation of DES – an option which is still not investigated and studied enough. 152 patients with implanted drug-eluting stents (different generations) for severe in-stent restenosis were followed up for a period of 9 years in the department of cardiology of University Hospital “St. Ekaterina”. Patients were divided into two groups – 131 patients with implanted first generation DES, and 21 patients – with second generation DES. Patients were followed up clinically (reversed angina, MI, emergency CABG, death), EchoCG and/or ECG stress test. Patients with angina pectoris and/or decreased LV function were assessed by conventional or CT angiography. Serious complications were not observed. 9 patients were with significant in-stent proliferation, and the others were with patent stents. Implementation of DES for treatment of in-stent restenosis is an established method, because of its reliability and safety with low percentage of complications.

Advanced Analysis of Faults Injected Through Conducted Intentional Electromagnetic Interferences

Experimental setups used in electromagnetic compatibility (EMC) tests can be used as platforms for fault injections. Injecting faults into equipment is a means for a malevolent attacker to extract secret information. In this paper, we first present an advanced setup, i.e., a setup with characteristics beyond the main international EMC standards. It performs more accurate measurements of the disturbance power, reducing the measurement error by 20.33 dB. Second, we propose an advanced analysis methodology allowing an attacker or a countermeasure designer to identify the disturbance frequency leading to the most powerful attack. As an illustration, the method is applied on an ASIC implementation of DES, providing a thorough characterization and classification of the generated faults. In this case, the most powerful attacks are performed when the disturbance has a frequency below 1 MHz. The threat has thus to be considered really serious, as generating such disturbance does not require a high budget.

Discussion of New Padding Method in DES Encryption

DES is a kind of block cipher and before DES encryption the plain text be divided into the same-size blocks. But sometimes the plain text can’t be divided into the exactly size. So padding step is needed to pad the space of the block. The discussion of the block padding is the emphasis of this paper. A new padding method is given and at the last part of the paper the implementation of DES using new padding method is given.

Algorithm‐level evaluation of DPA resistance to cryptosystems

AbstractPaul Kocher has proposed a cryptanalysis technique called differential power analysis (DPA), in which attackers derive secret information such as private keys from a statistical analysis of the power consumption by the target device. There is now a demand to evaluate the DPA resistivity of a cryptographic device before the device is actually created. In this paper, we focus on simulating DPA with high speed at algorithm level in upstream of the design process. Messerges used a power leakage model to obtain power consumption from Hamming weight for proof of high‐order DPA. However, the correctness of the model has not been verified. In this paper, we verify that difference of power consumption in DPA can be obtained from the power leakage model by investigating the cause of power consumption of CMOS circuits and transition probability of logic gates. The verification is performed by means of a circuit simulator. Next we describe a method of performing algorithm‐level simulation which calculates power consumption using the power leakage model. We illustrate the effectiveness of the method by applying it to DPA resistivity evaluation of DES implementation. © 2008 Wiley Periodicals, Inc. Electr Eng Jpn, 165(3): 37– 45, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/eej.20611

On two DES implementations secure against differential power analysis in smart-cards

Masking is one of the efficient and easily implemented countermeasures to protect cryptographic algorithms in such resource limited environments as smart-cards from differential power analysis as well as simple power analysis that were first introduced by Kocher et al. in 1999. To defend differential power analysis attacks, Akkar and Giraud presented a Transformed Masking Method and applied it to DES implementation in 2001. Unfortunately, in 2003, Akkar and Goubin showed a superposition attack that actually is a high-order differential power analysis attack on Akkar and Giraud’s DES implementation using Transformed Masking Method, and finally they presented a DES implementation using their proposed Unique Masking Method to defend any order differential power analysis attacks, which was later improved by Akkar, Bévan and Goubin in 2004. In this paper, by exploiting a new artifice to classify the electric consumption curves, we show that Akkar, Bévan and Goubin’s improved DES implementation using Unique Masking Method is still vulnerable to a high-order differential power analysis attack. Besides, we find it is also vulnerable to a superposition attack. We also present four new differential power analysis attacks on Akkar and Giraud’s DES implementation using Transformed Masking Method.

Algorithm Level Evaluation of DPA Resistivity against Cryptosystems

Paul Kocher has proposed a cryptanalysis technique called Differential Power Analysis (DPA), in which attackers derive secret information such as private keys from a statistical analysis of the power consumption by the target device. There is now a demand to evaluate the DPA resistivity of cryptographic device before the device is actually created. In this paper, we focus on simulating DPA with high speed at algorithm level in upstream of the design process. Messerges used Power Leakage Model to obtain power consumption from Hamming Weight for proof of high-order DPA. However, the correctness of the model has not been verified. In this paper, we verify that difference of power consumption in DPA can be obtained from Power Leakage Model by investigating the cause of power consumption of CMOS circuits and transition probability of logic gates. The verification is performed by means of a circuit simulator. Next we describe a method of performing algorithm level simulation which calculates power consumption using Power Leakage Model. We illustrate the effectiveness of the method by applying it to DPA resistivity evaluation of DES implementation.

Programming by sketching for bit-streaming programs

This paper introduces the concept of programming with sketches , an approach for the rapid development of high-performance applications. This approach allows a programmer to write clean and portable reference code, and then obtain a high-quality implementation by simply sketching the outlines of the desired implementation. Subsequently, a compiler automatically fills in the missing details while also ensuring that a completed sketch is faithful to the input reference code. In this paper, we develop StreamBit as a sketching methodology for the important class of bit-streaming programs (e.g., coding and cryptography).A sketch is a partial specification of the implementation, and as such, it affords several benefits to programmer in terms of productivity and code robustness. First, a sketch is easier to write compared to a complete implementation. Second, sketching allows the programmer to focus on exploiting algorithmic properties rather than on orchestrating low-level details. Third, a sketch-aware compiler rejects "buggy" sketches, thus improving reliability while allowing the programmer to quickly evaluate sophisticated implementation ideas.We evaluated the productivity and performance benefits of our programming methodology in a user-study, where a group of novice StreamBit programmers competed with a group of experienced C programmers on implementing a cipher. We learned that, given the same time budget, the ciphers developed in StreamBit ran 2.5x faster than ciphers coded in C. We also produced implementations of DES and Serpent that were competitive with hand optimized implementations available in the public domain.

The tissue microarray data exchange specification: A document type definition to validate and enhance XML data

BackgroundThe Association for Pathology Informatics (API) Extensible Mark-up Language (XML) TMA Data Exchange Specification (TMA DES) proposed in April 2003 provides a community-based, open source tool for sharing tissue microarray (TMA) data in a common format. Each tissue core within an array has separate data including digital images; therefore an organized, common approach to produce, navigate and publish such data facilitates viewing, sharing and merging TMA data from different laboratories. The AIDS and Cancer Specimen Resource (ACSR) is a HIV/AIDS tissue bank consortium sponsored by the National Cancer Institute (NCI) Division of Cancer Treatment and Diagnosis (DCTD). The ACSR offers HIV-related malignancies and uninfected control tissues in microarrays (TMA) accompanied by de-identified clinical data to approved researchers. Exporting our TMA data into the proposed API specified format offers an opportunity to evaluate the API specification in an applied setting and to explore its usefulness.ResultsA document type definition (DTD) that governs the allowed common data elements (CDE) in TMA DES export XML files was written, tested and evolved and is in routine use by the ACSR. This DTD defines TMA DES CDEs which are implemented in an external file that can be supplemented by internal DTD extensions for locally defined TMA data elements (LDE).ConclusionACSR implementation of the TMA DES demonstrated the utility of the specification and allowed application of a DTD to validate the language of the API specified XML elements and to identify possible enhancements within our TMA data management application. Improvements to the specification have additionally been suggested by our experience in importing other institution's exported TMA data. Enhancements to TMA DES to remove ambiguous situations and clarify the data should be considered. Better specified identifiers and hierarchical relationships will make automatic use of the data possible. Our tool can be used to reorder data and add identifiers; upgrading data for changes in the specification can be automatically accomplished. Using a DTD (optionally reflecting our proposed enhancements) can provide stronger validation of exported TMA data.

The stent.

The stent.

Efficient uses of FPGAs for implementations of DES and its experimental linear cryptanalysis

In its basic version, linear cryptanalysis is a known-plaintext attack that uses a linear relation between input-bits, output-bits, and key-bits of an encryption algorithm that holds with a certain probability. If enough plaintext-ciphertext pairs are provided, this approximation can be used to assign probabilities to the possible keys and to locate the most probable one. Matsui (1993) applied it to DES, becoming the best known attack against DES. Knudsen (2000) proposed three chosen-plaintext linear attacks, the third one becoming the best chosen-plaintext attack. This paper presents two original FPGA implementations of a DES encryption/decryption core that work at data rates up to 21.3 Gbps (333 MHz). We believe that our implementations are the fastest ones known nowadays. In our design, the plaintext, the key, and the mode (encryption/decryption) can be changed with no dead cycles. Based on one of our fast DES implementations, we present an FPGA implementation of the known-plaintext linear cryptanalysis of DES. The resulting design is deployed on eight FPGAs and allows us to find 12+1 key bits in about 2.3 hours. As a comparison, the fastest software implementation known so far (in 2000) used the idle time of 18 Intel Pentium III MMX and broke a DES key in 4.32 days. Our fast linear cryptanalysis implementation made the performing of practical tests possible, allowing a comparison with Matsui's theoretical estimations.

High speed implementation of DES

AmZ8068 is the fastest encryption/decryption device in one LSI available in the market. This device, which is manufactured by Advanced Micro Devices, Sunnyvale, California, complies with the National Bureau of Standards' Data Encryption Standard. it has three key registers to improve security and can handle encrypted keys. There are three separate input/output ports for maximum flexibility in system design. Throughput rate is fast enough for disk controllers and communication channels. Maximum data throughput is 1.7 M bytes/sec.