Demand-based Flash Translation Layer Research Articles

TCFTL: Improved Real-Time Flash Memory Two Cache Flash Translation Layer Algorithm

The traditional flash translation layer (FTL) algorithm is mainly aimed at optimizing the average response time of flash reading and writing. Since it cannot be updated in place, for the traditional FTL algorithm, it is necessary to find a free page for writing each time. When a block is full, it will redistribute a free block. Therefore, when the flash memory is almost full, a written request will lead to a garbage collection, which will have many write copies, which will lead to a substantial decline in response time. This paper proposes an algorithm that makes full use of spatial locality and temporal locality to optimize the address cache in Demand-based Flash Translation Layer (DFTL) algorithm. In the experiment, this algorithm experiment and good results are obtained.

An Adaptive Read-Write Partitioning Flash Translation Layer Algorithm

The classic demand-based flash translation layer (DFTL) algorithm is well-known since it can solve the contradiction between mapping flexibility and the size of mapping cache by dynamically loading mapping entries. However, DFTL failed to utilize the spatial locality and hot-cold characteristics of the request and had an inefficient mapping entry eviction scheme. This paper proposes an adaptive read-write partitioning flash translation layer algorithm (ARWFTL). First, the cache mapping table (CMT) is divided into the read CMT and the write CMT. The size of the two can be adaptively adjusted by sensing the characteristics of the upper workload and the read-write latency of the underlying flash page. Second, a priority eviction window is set at the tail of the write CMT to evict the clean mapping entry firstly. When there is no clean mapping entry in the priority eviction window, the tail mapping entry and other mapping entries that belong to the same translation page are clustered to write back into the translation page. Then, other written back mapping entries are set to be clean and the tail mapping entry is evicted. Third, a hot data window is set at the head of the write CMT to recognize the hot and cold data of write requests. Then, the hot and cold data are stored in different data blocks of flash to avoid hot and cold data entanglement and reduce valid page migrations in garbage collection. Experimental results show that, compared with DFTL, ARWFTL can reduce the translation page write counts, the valid page migration counts, the block erase counts, and the average response time by 92.8%, 47.7%, 31.7%, and 31.4%, respectively. In addition, ARWFTL is also superior to the other recent DFTL-based improved algorithms, and even exceeds the pure page-level FTL in some indicators.

Exploiting Internal Parallelism for Address Translation in Solid-State Drives

Solid-state Drives (SSDs) have changed the landscape of storage systems and present a promising storage solution for data-intensive applications due to their low latency, high bandwidth, and low power consumption compared to traditional hard disk drives. SSDs achieve these desirable characteristics using internal parallelism —parallel access to multiple internal flash memory chips—and a Flash Translation Layer (FTL) that determines where data are stored on those chips so that they do not wear out prematurely. However, current state-of-the-art cache-based FTLs like the Demand-based Flash Translation Layer (DFTL) do not allow IO schedulers to take full advantage of internal parallelism, because they impose a tight coupling between the logical-to-physical address translation and the data access. To address this limitation, we introduce a new FTL design called Parallel-DFTL that works with the DFTL to decouple address translation operations from data accesses. Parallel-DFTL separates address translation and data access operations into different queues, allowing the SSD to use concurrent flash accesses for both types of operations. We also present a Parallel-LRU cache replacement algorithm to improve the concurrency of address translation operations. To compare Parallel-DFTL against existing FTL approaches, we present a Parallel-DFTL performance model and compare its predictions against those for DFTL and an ideal page-mapping approach. We also implemented the Parallel-DFTL approach in an SSD simulator using real device parameters, and used trace-driven simulation to evaluate Parallel-DFTL’s efficacy. Our evaluation results show that Parallel-DFTL improved the overall performance by up to 32% for the real IO workloads we tested, and by up to two orders of magnitude with synthetic test workloads. We also found that Parallel-DFTL is able to achieve reasonable performance with a very small cache size and that it provides the best benefit for those workloads with large request size or with high write ratio.

RFTL: improving performance of selective caching-based page-level FTL through replication

The internal nature of flash memory technology, makes its performance highly dependent on workload characteristics causing poor performance on random writes. To solve this, Demand-based Flash Translation Layer (DFTL) which selectively caches page-level address mappings, was proposed. DFTL exploits temporal locality in workloads and when low, high cache miss rates are experienced. In this paper, we propose a replication based DFTL, called RFTL, which aims at minimizing the overhead caused by miss penalty from the cached mapping table in SRAM. We developed an analytical model for studying the range of performance for RFTL. We extended EagleTree simulator to implement RFTL. Our experimental evaluation with synthetic workloads endorses the utility of RFTL showing improved performance over DFTL especially for read-dominant workloads. With 80% read dominant workload, RFTL’s cumulative distribution function shows a 20% improvement and under 80% write dominant workload, it outperforms DFTL by 10% on I/O throughput.

An Adaptive Demand-Based Caching Mechanism for NAND Flash Memory Storage Systems

During past decades, the capacity of NAND flash memory has been increasing dramatically, leading to the use of nonvolatile flash in the system’s memory hierarchy. The increasing capacity of NAND flash memory introduces a large RAM footprint to store the logical to physical address mapping. The demand-based approach can effectively reduce and well control the RAM footprint. However, extra address translation overhead is also introduced which may degrade the system performance. In this article, we present CDFTL, an adaptive Caching mechanism for Demand-based Flash Translation Layer, for NAND flash memory storage systems. CDFTL adopts both the fine-grained entry-based caching mechanism to exploit temporal locality and the coarse-grained translation-page-based caching mechanism to exploit spatial locality of workloads. By selectively caching the on-demand address mappings and adaptively changing the space configurations of two granularities, CDFTL can effectively utilize the RAM space and improve the cache hit ratio. We evaluate CDFTL under a real hardware embedded platform using a variety of I/O traces. Experimental results show that our technique can achieve an 11.13% reduction in average system response time and a 35.21% reduction in translation block erase counts compared with the previous work.

Exploiting Sequential and Temporal Localities to Improve Performance of NAND Flash-Based SSDs

NAND flash-based Solid-State Drives (SSDs) are becoming a viable alternative as a secondary storage solution for many computing systems. Since the physical characteristics of NAND flash memory are different from conventional Hard-Disk Drives (HDDs), flash-based SSDs usually employ an intermediate software layer, called a Flash Translation Layer (FTL). The FTL runs several firmware algorithms for logical-to-physical mapping, I/O interleaving, garbage collection, wear-leveling, and so on. These FTL algorithms not only have a great effect on storage performance and lifetime, but also determine hardware cost and data integrity. In general, a hybrid FTL scheme has been widely used in mobile devices because it exhibits high performance and high data integrity at a low hardware cost. Recently, a demand-based FTL based on page-level mapping has been rapidly adopted in high-performance SSDs. The demand-based FTL more effectively exploits the device-level parallelism than the hybrid FTL and requires a small amount of memory by keeping only popular mapping entries in DRAM. Because of this caching mechanism, however, the demand-based FTL is not robust enough for power failures and requires extra reads to fetch missing mapping entries from NAND flash. In this article, we propose a new flash translation layer called LAST++. The proposed LAST++ scheme is based on the hybrid FTL, thus it has the inherent benefits of the hybrid FTL, including low resource requirements, strong robustness for power failures, and high read performance. By effectively exploiting the locality of I/O references, LAST++ increases device-level parallelism and reduces garbage collection overheads. This leads to a great improvement of I/O performance and makes it possible to overcome the limitations of the hybrid FTL. Our experimental results show that LAST++ outperforms the demand-based FTL by 27% for writes and 7% for reads, on average, while offering higher robustness against sudden power failures. LAST++ also improves write performance by 39%, on average, over the existing hybrid FTL.

A Temporal Locality-Aware Page-Mapped Flash Translation Layer

The poor performance of random writes has been a cause of major concern which needs to be addressed to better utilize the potential of flash in enterprise-scale environments. We examine one of the important causes of this poor performance: the design of the flash translation layer (FTL) which performs the virtual-to-physical address translations and hides the erase-before-write characteristics of flash. We propose a complete paradigm shift in the design of the core FTL engine from the existing techniques with our Demand-Based Flash Translation Layer (DFTL) which selectively caches page- level address mappings. Our experimental evaluation using FlashSim with realistic enterprise-scale workloads endorses the utility of DFTL in enterprise-scale storage systems by demonstrating: 1) improved performance, 2) reduced garbage collection overhead and 3) better overload behavior compared with hybrid FTL schemes which are the most popular implementation methods. For example, a predominantly random-write dominant I/O trace from an OLTP application running at a large financial institution shows a 78% improvement in average response time (due to a 3-fold reduction in operations of the garbage collector), compared with the hybrid FTL scheme. Even for the well-known read-dominant TPC-H benchmark, for which DFTL introduces additional overheads, we improve system response time by 56%. Moreover, interestingly, when write-back cache on DFTL-based SSD is enabled, DFTL even outperforms the page-based FTL scheme, improving their response time by 72% in Financial trace.

DFTL

Recent technological advances in the development of flash-memory based devices have consolidated their leadership position as the preferred storage media in the embedded systems market and opened new vistas for deployment in enterprise-scale storage systems. Unlike hard disks, flash devices are free from any mechanical moving parts, have no seek or rotational delays and consume lower power. However, the internal idiosyncrasies of flash technology make its performance highly dependent on workload characteristics. The poor performance of random writes has been a cause of major concern, which needs to be addressed to better utilize the potential of flash in enterprise-scale environments. We examine one of the important causes of this poor performance: the design of the Flash Translation Layer (FTL), which performs the virtual-to-physical address translations and hides the erase-before-write characteristics of flash. We propose a complete paradigm shift in the design of the core FTL engine from the existing techniques with our Demand-based Flash Translation Layer (DFTL), which selectively caches page-level address mappings. We develop a flash simulation framework called FlashSim. Our experimental evaluation with realistic enterprise-scale workloads endorses the utility of DFTL in enterprise-scale storage systems by demonstrating: (i) improved performance, (ii) reduced garbage collection overhead and (iii) better overload behavior compared to state-of-the-art FTL schemes. For example, a predominantly random-write dominant I/O trace from an OLTP application running at a large financial institution shows a 78% improvement in average response time (due to a 3-fold reduction in operations of the garbage collector), compared to a state-of-the-art FTL scheme. Even for the well-known read-dominant TPC-H benchmark, for which DFTL introduces additional overheads, we improve system response time by 56%.