Delta Modulation Research Articles

Circularly polarized beam-scanning leaky wave antenna based on a slow-wave substrate integrated waveguide

A circularly polarized (CP) beam-scanning leaky wave antenna (LWA) based on a slow-wave substrate integrated waveguide (SW-SIW) is presented in this paper. The SW effect is realized by introducing a spoof surface plasmon polariton (SSPP), excited by periodic etched 45° tilted slots on the top metallic layer of an SIW. With extra delta modulation, the electromagnetic waves radiate through the etched slots and scan continuously from a backward to forward direction as the frequency changes. Taking advantage of the tilted slots and relative displacement between the upper and lower slots, the direction of the electric field of the radiated waves and phase difference between them are adjustable, making a CP characteristic available. Both the simulated and measured results show the proposed LWA exhibits good performance. The total scanning angle reaches 70°, and the average gain is 8.9 dBi from 9.5 GHz to 11.7 GHz. The CP characteristic is verified through the axial ratio of less than 3 during the operating frequency range. A simple structure, compact size, and good performance make the proposed design promising for a compact wireless communication system.

Digitalized Radio over Fiber Network-Based Sigma Delta Modulation

ABSTRACT Digital Radio over Fiber (DRoF) technologies end up being the most often used option for the backbone of Wide Area Networks (WAN). The main goal of this paper is to evaluate a DRoF scheme called Sigma Delta Radio over Fiber (SDRoF). Studies have been done on the suggested system performance metrics, such as Error Vector Magnitude (EVM). According to the simulation findings, the suggested model can handle 6.144 Gbps data transfer up to 300 km with zero BER and an EVM of about 4.153%. The proposed system model was found to be superior to the most recent peer-reviewed papers.

New 1H-pyrazolo[3,4-d]pyrimidin-1-yl)ethyl)-2-phenylisoquinoline-1(2H)-ones as Phosphoinositide 3-kinase Inhibitors for Treating Cancer and Other Diseases.

The patent describes novel useful compounds, such as PI3K protein kinase inhibitors, in particular as PI3K delta (δ) and/or gamma (γ) protein kinase modulators. The present disclosure also provides methods for preparing PI3K protein kinase inhibitors, pharmaceutical compositions containing them, and methods of treatment, prevention, and amelioration of PI3K kinase-mediated diseases, and disorders.

Convolutional spiking neural networks for intent detection based on anticipatory brain potentials using electroencephalogram

Spiking neural networks (SNNs) are receiving increased attention because they mimic synaptic connections in biological systems and produce spike trains, which can be approximated by binary values for computational efficiency. Recently, the addition of convolutional layers to combine the feature extraction power of convolutional networks with the computational efficiency of SNNs has been introduced. This paper studies the feasibility of using a convolutional spiking neural network (CSNN) to detect anticipatory slow cortical potentials (SCPs) related to braking intention in human participants using an electroencephalogram (EEG). Data was collected during an experiment wherein participants operated a remote-controlled vehicle on a testbed designed to simulate an urban environment. Participants were alerted to an incoming braking event via an audio countdown to elicit anticipatory potentials that were measured using an EEG. The CSNN’s performance was compared to a standard CNN, EEGNet and three graph neural networks via 10-fold cross-validation. The CSNN outperformed all the other neural networks, and had a predictive accuracy of 99.06% with a true positive rate of 98.50%, a true negative rate of 99.20% and an F1-score of 0.98. Performance of the CSNN was comparable to the CNN in an ablation study using a subset of EEG channels that localized SCPs. Classification performance of the CSNN degraded only slightly when the floating-point EEG data were converted into spike trains via delta modulation to mimic synaptic connections.

A novel approach toward optimized image processing using sigma delta modulation

Image processing has widespread uses practically in every branch of science and arts. Processing images is more difficult than processing sound or data as there are more bits in the high pixel quality image. It requires more space to store the image, more bandwidth to transmit it, and more time and resources to process. An image's complexity may decrease if its bit size is decreased. Sigma-delta modulation, or SDM for short, is an alternative method of minimizing data-word length to compression. Digital signal processing (DSP) systems can be made simpler by using the SDM approach, which was first created for analog to digital conversion (ADC). This paper suggests a novel way to use SDM in MATLAB for improved image processing. Consequently, the suggested single-bit SDM-based image arithmetic architecture is tested and compared with the traditional image arithmetic techniques. Additionally, to see the noisy channel influence on the traditional and proposed systems, some statistical metrics are also studied at different noise variance values, such as signal to noise ratio (SNR), mean square error (MSE), and Peak SNR value. The suggested architecture for the SDM-based image arithmetic precisely matches the addition and subtraction results of the conventional design, even yielding a higher SNR and the same Peak SNR as the traditional methods. In contrast, the outcomes of division and multiplication fall within an acceptable range. For better results the over-sampling ratio (OSR), an inherent characteristic of SDM must be increased at the cost of more processing cycles. Therefore, the trade-off between fewer resources, limited transmission bandwidth, and comparatively more cycles is provided by the SDM-based technique.

A Single Op-Amp Resonator-Based Continuous-Time Sigma–Delta Modulator With Time-Division Switching for Excess Loop Delay Compensation

A Single Op-Amp Resonator-Based Continuous-Time Sigma–Delta Modulator With Time-Division Switching for Excess Loop Delay Compensation

A Novel Three-Dimensional Sigma–Delta Modulation for High-Switching-Frequency Three-Phase Four-Wire Active Power Filters

This article presents a new modulation technique called three-dimensional sigma–delta (3D-ΣΔ) modulation for high-frequency three-leg four-wire voltage source converters (VSCs) that use wide-bandgap (WBG) semiconductors. These WBG devices allow for the use of high switching frequencies with a greater efficiency than silicon devices. The proposed 3D-ΣΔ technique enables operation at a variable switching frequency, resulting in a significant reduction in switching losses compared to classical pulse-width modulation (PWM) techniques. Moreover, the 3D-ΣΔ technique uses a fast-processing 3D quantiser that simplifies implementation and considerably reduces computational costs. The behaviour of the 3D-ΣΔ modulation is analysed using MATLAB/Simulink and PLECS. The experimental results performed on an active power filter that uses silicon carbide (SiC) MOSFETs demonstrate an improvement in converter efficiency compared to the conventional SPWM technique. Additionally, the experimental results show how 3D-ΣΔ allows for the compensation of harmonics and homopolar currents, thereby balancing the electrical grid currents. The experiments also show that the proposed 3D-ΣΔ modulation outperforms an SPWM technique in terms of power quality, since the former achieves a larger reduction in the harmonic content of the power grid. In conclusion, the proposed modulation technique is an attractive option for improving the performance of four-wire converters in active power filter applications.

A Review on Higher Order Continuous-Time Sigma-Delta Modulators for ADC Design

Abstract—In this paper, the concept of adaptive filtering has been proposed. It has been shown that signals often undergo variation in the noise environment encountered. Hence it becomes mandatory to design filters based on noise shaping and adaptive noise cancellation. Such filters are called adaptive filters and are used for applications requiring real time noise cancellation such as speech processing, live video broadcasting etc. The paper presents the structure of Sigma Delta or MASH ADCs which employ recursive encoding. SDM ADCs are also used to convert high bit-count, low- frequency digital signals into lower bit-count, higher-frequency digital signals as part of the process to convert digital signals into analog as part of a digital-to-analog converter (DAC). The paper focuses on the various approaches used thus far for the purpose, citing the pros and cons of each approach. Keywords— Adaptive Filter Design, Noise Filtering, Sigma Delta Modulator (SDM), MASH, Signal to Noise Ratio.

Adaptive Delta Modulation Simulation and Analysis Using MatLab


 
 
 
 The system for converting analog signals to digital signals has become a necessity, considering that the tools currently used are digital computers. One of the analog-to-digital conversion systems is the delta modulation system. In delta modulation, only one bit is used to encode each change in the input signal, where a rising signal is encoded into a one bit and a falling signal is encoded into a zero bit. This can save the bit rate which, when transmitted over the transmission channel, can save the transmission bandwidth, and when stored in computer storage media, can save storage space. However, if the slope of the signal rises and falls sharply, the delta modulation system cannot follow these signal changes, which is called slope overload. To overcome this problem, an adaptive delta modulation system was developed that has variable or adaptive pulse height for both one and zero bits. In this paper, a comparison between the delta modulation system and the adaptive delta modulation system using MatLab application will be simulated and analyzed. From the simulation results, it can be seen that the adaptive delta modulation system is able to overcome slope overload compared to the delta modulation system.
 
 
 

Reduction of Spurious Switching in Direct Vector Quantized Space Vector Pulse Density Modulation Scheme for Multilevel Inverters

A generalized online switching scheme for multi-level inverter based on Direct Vector Quantized Space Vector Pulse Density Modulation (DVQSVPDM) suitable for adjustable speed drive is proposed in this article. The existing DVQSVPDM schemes have spurious switching as the voronoi region is determined from integrated error vector of Sigma Delta Modulator (SDM). This results in high Total Harmonic Distortion (THD) of Common Mode Voltage (CMV) at lower modulation index. In the proposed DVQSVPDM the nearest three space vectors to the reference vector forms the triangular voronoi region. The integrated error vector of SDM is quantized to its nearest space vector in the voronoi region to generate the switching vectors. This reduces spurious switching associated with DVQSVPDM schemes and improves the performance at lower modulation index by reducing THD of CMV. The proposed scheme works for all n-level inverter topologies and the computations required remain same irrespective of level of inverter. Redundant states of switching vectors are not considered for switching which results in the discontinuous nature of proposed scheme. The performance of proposed DVQSVPDM is compared with space vector based modulation schemes and third harmonic injected sine PWM scheme and the results are presented. The proposed scheme is experimentally validated for a 3hp open end winding induction motor fed with three-level inverters on both sides.

Experiments on Digital Filtering of Analog Signals: Pulse Amplitude Modulation and Delta Modulation

To boost students' active learning and understanding of abstract scientific concepts, hands-on learning experiences such as experiments are necessary. Computer simulations also allow students to carry out experiments virtually. Analog signals are processed using digital signal processing because of the advantages of digital signal processing over analog signal processing. Numerical experiments, results, and observations on digital band pass filtering of analog signals are presented. Two types of digital modulation are employed: Pulse Amplitude Modulation (PAM) and Delta Modulation (DM). Results demonstrated higher suppression of frequencies in the stopband compared with the transition band. Frequencies in the passband suffer minimum or no attenuation. The phase difference between input and output signals, transient response, and steady state response are observed vividly. PAM is found to add less noise to the system compared with DM. These experiments are recommended as virtual laboratory exercises for undergraduate and postgraduate studies for active learning purposes.

Efficacious Zero Sequence Voltage Elimination in Space Vector Modulation by Sigma Delta Modulation

The growing popularity of electric motor driven systems emphasize the need for proper motor maintenance and necessitates zero sequence voltage (ZSV) elimination in electrical machines and drives. A spread spectrum modulation scheme for eliminating zero sequence voltage, utilizing space vector pulse density modulation (SVPDM) approach is proposed in this article. In the presented five-level inverter scheme, when vectors that do not contribute zero sequence voltage are considered, a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$30^{0}$</tex-math></inline-formula> tilted three-level space vector diagram with inner and outer layer is formed. Reference vector residing in outer layer is mapped to inner layer and is vector quantized in a space vector quantizer to generate inner layer switching vectors. Outer layer switching vectors are then realized by the process of reverse mapping. The article investigates two-level SVPDM scheme and ZSV eliminated two-level SVPDM scheme, to prove that effectiveness of ZSV elimination can be determined from the shape of demodulated waveform. Better the ZSV elimination, better will be the resemblance of demodulated waveform to sinusoidal signal. The scheme is experimentally validated with 2.2 kW five-level dual inverter fed induction motor drive and is compared with space vector pulse width modulation (SVPWM) scheme. Results of comparison confirms the effectiveness of proposed scheme.

Artificial TMAP Signal Generator Based on One-Bit Sigma Delta Modulator for MEC Test

The current study proposes three electrode-channels with time delay of artificial nerve signals generator utilized with only a active low pass filter and a Field Programmable Gate Array (FPGA). The XC3S100E FPGA board adopted to design a novel and real-time artificial transmembrane action potential (TMAP). The implementation of one bit Sigma Delta Modulation (SDM) method with linearized technique could be very expensive and complicated products with other technologies option currently available such as a microcontroller due to the fabrication requirements. This technique could employ in many biomedical applications and testing efficiently, especially, in evaluating the multi-electrode cuff system without requiring use of real nerves spike from animal models and saving time and effort, and cost. Moreover, this approach is adopted for further improvement to the signal performances such as resolution, accuracy, differential linearity monotonic DAC, and settling time of the signal waveform without extra hardware or cost required. In addition, the design included three channels of white Gaussian noise uncorrelated for each TMAP signal to simulate the real nerve noise environment, which surrounds the electrode cuff in experimental cases. A noise channels with adjustment level is added to the nerve spike using three sets of taps are employed to provide three channels of noise sources. The Xilinx ISE platform and Mentor Graphics ModelSim tool are used to simulate and implement this, and the results produced are compared. The power consumption of conventional technology is 31 mW, which is significantly higher than the power consumed (21mW) in modern technology. Furthermore, as compared to the usual way, the proposed solution conserved around 10% of the FPGA resources. This technique offers reuse in other applications where delay time, low amplitude voltage signals, and multichannel generator is needed. Moreover, this system offers adjustable waveform signal, noise level, conduction velocity and time delay easily to adequate different applications and tests.

An Integrated 50 V Boost Controller With Digitally-Assisted MPPT for Submodule PV Applications

This work introduces an integrated maximum power point tracking boost controller for photovoltaic submodule applications. The IC offers a wide input voltage range from 7 V to 24 V, whereas the output voltage is actively limited to 50 V. The presented design utilizes discrete, low-ohmic MOSFETs for the output stage and thus supports input power levels up to 144 W. The converter operates with peak-current-mode control at 300 kHz switching frequency in continuous conduction mode. During light load operation, the control transitions to direct input voltage sensing pulse-frequency-modulation (PFM) with input and output voltage dependent peak inductor current. Moreover, the low-side resistive current sense is explained in detail together with an inductor current replication circuit for precise high-side turn-off. The maximum power point tracker (MPPT) is based on an adjustable resistive sense element and a delta modulator and achieves 99.9 % tracking efficiency, omitting any need for a high resolution analog-to-digital converter (ADC). In addition, the series connection of multiple DC/DC converters is examined. The peak system efficiency measures 98.4 %. The application-specific integrated circuit (ASIC) is manufactured in an 0.18 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula> m HV-BCD process and occupies 6.25 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of silicon area.

Novel Common Mode Voltage Elimination Methods in Three-Phase Four-Wire Grid-Connected Inverters

This paper presents two current control methods to attenuate the common mode (CM) conducted emissions in three-phase four-wire four-pole inverters connected to an AC distribution bus and operating in grid-following mode. Delta modulation and model predictive control both achieve elimination of the common mode voltage at the output of the three-phase four-pole inverter and meet the requirements of the military standard 461G without a full-size CM choke. The differential mode performance is comparable to that achieved with the benchmark three-dimensional space vector modulation, which does not cancel the CM voltage. A physics-based model of the system was developed to simulate the conducted emissions and DM performance of the two proposed methods. As the CM voltage cancellation methods result in increased switching frequency, wide bandgap devices were used to build a laboratory prototype, on which the simulated results were successfully validated.

All-Standard-Cell-Based Analog-to-Digital Architectures Well-Suited for Internet of Things Applications

In this paper, the most suited analog-to-digital (A/D) converters (ADCs) for Internet of Things (IoT) applications are compared in terms of complexity, dynamic performance, and energy efficiency. Among them, an innovative hybrid topology, a digital–delta (Δ) modulator (ΔM) ADC employing noise shaping (NS), is proposed. To implement the active building blocks, several standard-cell-based synthesizable comparators and amplifiers are examined and compared in terms of their key performance parameters. The simulation results of a fully synthesizable Digital-ΔM with NS using passive and standard-cell-based circuitry show a peak of 72.5 dB in the signal-to-noise and distortion ratio (SNDR) for a 113 kHz input signal and 1 MHz bandwidth (BW). The estimated FoMWalden is close to 16.2 fJ/conv.-step.

Macro Model for Discrete-Time Sigma‒Delta Modulators

This work presents a macro model for discrete-time sigma‒delta modulators, which can significantly reduce the simulation time compared to transistor level circuits. The proposed macro model is realized by effectively combining active and passive ideal circuit components with Verilog-A modules. As such, since the macro model is a true representation of the actual transistor level circuit, a moderately good accuracy can be obtained. In addition, the proposed macro model includes the major amplifier, comparator, and switch‒capacitor non-idealities of the sigma‒delta modulator such as amplifier DC gain, GBW, slewrate, comparator bandwidth, hysteresis, parasitic capacitance, and switch-on resistance. The results show the simulation time of the proposed macro model sigma‒delta modulator is only 6.43% of the transistor level circuit with comparable accuracy. As a result, the proposed macro model can facilitate the circuit design and leverage non-ideality analysis of discrete-time sigma‒delta modulators. As a practical design example, a second order discrete-time sigma‒delta modulator with a five-level quantizer is realized using the propose macro model for GSM and WCDMA applications.

1-ADM-CNN: A Lightweight In-field Compression Method for Seismic Data

Large-scale seismic acquisition, versatility, flexibility, automation, and scalability are the objectives of future oil and gas exploration technology. An example of emerging technology for seismic monitoring is distributed acoustic sensing (DAS). The significant amount of data produced by DAS is a challenge that necessitates the development of new technologies for its efficient handling and processing. A typical seismic survey, on the one hand, can generate hundreds of terabytes of raw seismic data per day. The demand for wireless seismic data transmission, on the other hand, remains enormous. The massive amount of data transmission from geophones to the on-site data collection center and its storage poses significant challenges. A lightweight compression procedure is required in order to reduce the data traffic and the storage size at the data center without putting an extra burden on a geophone. In this brief, an efficient implementation of a 1D convolutional neural network (CNN) together with 1-bit adaptive delta modulation is presented for in-field seismic data compression. It is worth mentioning here that the training of CNN is done offline on synthetic data set and hence, the proposed approach has potential for real-time implementation. Furthermore, no assumption on the underlying statistics of noise or the seismic signal is imposed and consequently, the proposed method is suitable for a wide range of seismic data. Furthermore, the proposed method works in the time-domain, unlike existing transform-domain methods, making it suitable for quick diagnosis of bad traces at the data center. Simulation results with real data set reveal that the proposed approach achieves a signal-to-noise ratio (SNR) of approximately 30 dB with a compression gain of 35: 1. Finally, significant superiority in terms of compression gain and reconstruction quality is demonstrated when compared to the existing methods.

A New Space Vector Pulse Density Modulation Scheme for Two-Level Five Phase Induction Motor Drive

Variable speed drives incorporating multiphase motors have started gaining attention in recent years due to their benefits over three-phase counter parts. In this article, we propose a digital control scheme based on space vector pulse density modulation for two-level five phase induction motor drive. The scheme combines principles of digital signal processing techniques, such as sigma delta modulation and vector quantization, along with space vector modulation to form computationally efficient motor drives. In this article, vector space is divided into ten nonoverlapping regions, with each region partitioned into three voronoi regions. The reference vector is vector quantized to the nearest switching vector. Absence of dwell time calculations, less memory requirements, and reduced computational complexity of the scheme along with reduced acoustic noise and electromagnetic interference in the drive are the core advantages of the scheme. The work has been experimentally implemented with 2 HP five-phase induction motor drive and the results are compared with space vector pulsewidth modulation scheme for validation purpose.

4th Order LC-Based Sigma Delta Modulators.

Due to the characteristic of narrow band conversion around a central radio frequency, the Sigma Delta Modulator (ΣΔM) based on LC resonators is a suitable option for use in Software-Defined Radio (SDR). However, some aspects of the topologies described in the state-of-the-art, such as noise and nonlinear sources, affect the performance of ΣΔM. This paper presents the design methodology of three high-order LC-Based single-block Sigma Delta Modulators. The method is based on the equivalence between continuous time and discrete time loop gain using a Finite Impulse Response Digital-to-Analog Converter (FIRDAC) through a numerical approach to defining the coefficients. The continuous bandpass LC ΣΔM simulations are performed at a center frequency of 432 MHz and a sampling frequency of 1.72 GHz. To the proposed modulators a maximum Signal-to-Noise Ratio (SNR) of 51.39 dB, 48.48 dB, and 46.50 dB in a 4 MHz bandwidth was achieved to respectively 4th Order Gm-LC ΣΔM, 4th Order Magnetically Coupled ΣΔM and 4th Order Capacitively Coupled ΣΔM.