Interconnect Delay Research Articles

Stability and stabilization of fractional-order singular interconnected delay systems

An analytical approach based on fractional calculus and singular value theory to finite-time stability and stabilization of fractional-order singular interconnected delay systems is proposed. Particularly, we study fractional singular equations with interval time-varying delays. We first give new sufficient conditions for finite-time stability of such equations. Then, the feedback stabilizing controllers are designed via solving a tractable linear matrix inequality (LMI) and Mittag-Leffler function. Finally, numerical examples with simulations are given to illustrate the feasibility and effectiveness of the proposed results.

Noise coupling reduction using temperature enhanced device for future integrated circuit integration applications

<p>Information technology-to-internet of things may have succeeded because of fast silicon chip capability expansion. Moore's law, which reduces device size, boosted integrated circuit (IC) performance. Delay rises with highdensity connection parasitic capacitance. Interconnect delays have surpassed transistor delays and slowed progress. An alternative is required now to reduce connection latency. The third dimension is used in popular 3D IC technology IC technology requires through silicon via (TSV) for signal integrity and heat mitigation. Noise coupling hinders electrical communication between signal-carrying TSVs (aggressive TSVs) and ground TSVs (victim TSVs), a 3D IC bottleneck. TSVs must be dielectrically insulated from Si substrates to avoid electrical signal interference. Additionally, first-order modelling will confirm the suggestions. This article proposes using the nanosheet field effect transistor (NSFET) to overcome 3D IC noise coupling and complementary metal oxide semiconductor (CMOS) technology nodes. After discussing the electronic industry and sub nm, several basic metrics and criteria for developing electronic components are presented. The first technique uses Perylene-N's exceptional noise-cancelling characteristics. Second technique uses electrical TSV (ETSV), thermal TSV (TTSV), and heat source models to measure noise coupling on numerous ICs. The third proposes many noise-reducing materials. The suggested structures outperform traditional approaches.</p>

Consensus of Euler–Lagrange Agents With Internal Model Disturbance Rejection and Interconnection Delays

Consensus of Euler–Lagrange Agents With Internal Model Disturbance Rejection and Interconnection Delays

Microcellular long-chain branched polyphenylene oxide (PPO) with excellent comprehensive properties and comprehensive analysis of its dielectric properties

High-frequency and high-speed communications impose stringent requirements on low-dielectric materials with exceptional comprehensive properties. The development of dielectric materials with low dielectric constants and low dielectric dissipation factors holds significant value in reducing interconnect delay, power consumption, and crosstalk in high-frequency communication. In this study, polyphenylene oxide (PPO), known for its excellent properties, was chosen as the base material. Modified PPO with a long-chain branched structure was prepared using the multi-epoxy modifier ADR-4468. The increase in molecular weight and the formation of a long-chain branched structure improved the thermal stability, flexural properties, and foamability of PPO. Introduction of low-dielectric air into the material was achieved through supercritical CO2 foaming, resulting in a series of microcellular PPO foams exhibiting low dielectric properties (with a dielectric constant as low as 1.12 and a dielectric dissipation factor as low as 0.000636). Concurrently, the dielectric properties of microcellular PPO foams were examined at 10 GHz, revealing that the foam’s dielectric properties were minimally impacted by the properties of the raw materials. Based on water absorption analysis, an improved equation for calculating the dielectric dissipation factor was proposed, comprehensively analyzing the influencing factors on the foam’s dielectric dissipation factor. The study unveiled that water absorption significantly affects the foam’s dielectric dissipation factor, and under high expansion ratios, water absorption’s impact on the dielectric dissipation factor exceeds that of air introduction. These microcellular PPO foams, possessing excellent comprehensive properties and low dielectric characteristics, hold promise for applications in the realm of high-frequency and high-speed communications.

Decentralized Output-Feedback Adaptive Event-Triggered Control for Interconnected Nonlinear Delay Systems with Actuator Failures

This paper investigates decentralized adaptive event-triggered fault-tolerant control for interconnected nonlinear delay systems with actuator failures. The actuator failures suffered include loss of effectiveness and bias faults. A control scheme based on the K-filter is proposed, which effectively compensates for the effects of unknown actuator failures. A hyperbolic tangent function and neural network are introduced to approximate the unknown interconnection function and nonlinear delay function. By introducing the dynamic surface control method, the “explosion of complexity” issue is addressed. Furthermore, our proposed controller can ensure that all states of the corresponding closed-loop system are semi-globally uniformly ultimately bounded and that the tracking error can converge to a small neighborhood of zero. Meanwhile, Zeno behavior can be effectively avoided. Finally, the validity of the proposed control scheme is verified using a simulation example.

Novel Architecture of Fir Lattice Filter with Reduced Interconnect Delay Impacts Towards Reduced Power-delay Product using Pipelining and Parallel Processing for Medical Applications

Three important parameters area, speed and power are important. In VLSI design, the speed is determined by the critical path delay. Delay is depending on the data path taken for processing in the VLSI design. By minimizing data-path delay using efficient architecture the speed of the design of system can be improved in turn to result in better performance. In this new era, data-path delay is the dominating one compared to logic delay. So, it is very essential to concentrate more towards path delay in any architecture design. Even though the speed is important it is having in trade of with power. This data-path delay can be reduced by different technique like pipelining, parallel processing, register retiming. Also, by constructing this architecture in an innovative way the power is having trade of with delay. So the power-delay product can be taken as the reduced one. In this paper, various architecture of delay-product optimized FIR filter and Lattice filter architecture is being surveyed and implemented in order to get minimum delay-power product

Performance metrics of doped graphene nanoribbons based nanoscale interconnects: DFT and NEGF analysis

Due to the scaling of devices, the interconnects delay is the most important concern of the current technology, becomes more significant than the IC delay, and leads to overall impact on the performance of the chip. In the present work, doped Zigzag Graphene Nano ribbons (GNR) have been analyzed for the possible nanoscale interconnect applications. The investigation has been performed using the density-functional theory-based ab-initio approach, discussed in terms of structural stability of ribbons, their electronic and transport properties, and the dynamical parameters. Zigzag GNR has been decorated with itssix possible sites along the width, through P and N type impurities, to select the most favorable site for the further analysis. The stability of the systems has been analyzed in terms of formation energy, the electronic properties in terms of band structure and density of states profiles, whereas, the transport properties in terms of transmission spectrum and I–V characteristics. The magnetic inductance, kinetic inductance, electrostatic capacitance, and quantum capacitance have also been calculated as interconnect parameters. The formation energy calculations suggest that the doping at the edge sites of NRs are more favorable. Further, it has been observed that the metallicity of the doped ZGNR enhances with doping, whereas, the I–V characteristics confirms that the N doped ZGNRs have linear current with constant slope. The performance metrics of ZGNRs have also been analyzed using HSPICE, discussed in terms of delay and power delay product, shows that the N doped ZGNRs have lower delay than the other considered counterparts, defends its application as interconnects in the electronic industry.

Hashing for secure optical information compression in a heterogeneous convolutional neural network

In recent years, heterogeneous machine learning accelerators have become of significant interest to science, engineering, and industry. At the same time, the looming post-quantum encryption era instigates the demand for increased data security. From a hardware processing point of view, electronic computing hardware is challenged by electronic capacitive interconnect delay and associated energy consumption. In heterogeneous systems, such as electronic–photonic accelerators, parasitic domain crossings limit throughput and speed. With analog optical accelerators exhibiting a strong potential for high throughput (up to petaoperations per second) and operation efficiency, their ability to perform machine learning classification tasks on encrypted data has not been broadly recognized. This work is a significant step in that direction. Here, we present an optical hashing and compression scheme that is inspired by SWIFFT, a post-quantum hashing family of algorithms. High degree optical hardware-to-algorithm homomorphism allows one to optimally harvest the potential of free-space data processing: innate parallelism, low latency tensor by-element multiplication, and zero-energy Fourier transformation operations. The algorithm can provide several orders of magnitude increase in processing speed as compared to optical machine learning accelerators with non-compressed input. This is achieved by replacing slow, high-resolution CMOS cameras with ultra-fast and signal-triggered CMOS detector arrays. Additionally, information acquired in this way will require much lower transmission throughput, less in silico processing power, storage, and will be pre-hashed, facilitating optical information security. This concept has the potential to allow heterogeneous convolutional Fourier classifiers to approach the performance of their fully electronic counterparts and enables data classification on hashed data.

Distributed Robust Partial State Consensus Control for Chain Interconnected Delay Systems

Partial state consensus (PSC) is investigated for chain interconnected systems with time-varying delays and parameter uncertainties. A novel design philosophy of PSC control is proposed and a sequential calculation method is presented to guarantee the robustness of the controller. A sufficient condition based on linear matrix inequalities (LMIs) is derived and the stability is proven by the Lyapunov method. The proposed approach can ensure that the states which are subject to a consensus constraint achieve consensus, while those without a consensus constraint track their own set points. Finally, numerical simulations and a solution proportioning experiment are developed to validate the effectiveness of the proposed method.

PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs

Hundreds of processor cores or modules are integrated into a single chip. The traditional bus or crossbar is challenged by bandwidth, scalability, and silicon area, and cannot meet the requirements of high end applications. Network-on-chip (NoC) has become a very promising interconnection structure because of its good scalability, predictable interconnect length and delay, high bandwidth, and reusability. However, the most available packet routing NoC may not be the perfect solution for high-end heterogeneous multi-core real-time systems-on-chip (SoC) because of the excessive latency and cache cost overhead. Moreover, circuit switching is limited by the scale, connectivity flexibility, and excessive overhead of fully connected systems. To solve the above problems and to meet the need for low latency, high throughput, and flexibility, this paper proposes PCCNoC (Packet Connected Circuit NoC), a low-latency and low-overhead NoC based on both packet switching (setting-up circuit) and circuit switching (data transmission on circuit), which offers flexible routing and zero overhead of data transmission latency, making it suitable for high-end heterogeneous multi-core real-time SoC at various system scales. Compared with typically available packet switched NoC, our PCCoC sees 242% improved performance and 97% latency reduction while keeping the silicon cost relatively low.

Distributed control for spatially interconnected time-varying delay systems under input saturation

This paper presents the distributed control design for a class of spatially interconnected continuous-time time-varying delay (SICTD) systems under input saturation. A distributed controller and distributed anti-windup compensator (AWC) are proposed based on the distributed structure of the SICTD system. Then, a sufficient condition is derived to guarantee the asymptotic stability and H∞ performance of the closed-loop system under the saturation constraints. We have also provided an algorithm for obtaining the AWC parameters by employing the elimination lemma and the cone complementary linearization approach. The proposed anti-windup compensation methodology can also be employed to compensate for the actuator saturation of the spatially interconnected delay-free systems. Finally, two practical examples are presented to verify the effectiveness of the proposed AWC design method.

Output feedback stabilization of an ODE-Reaction–Diffusion PDE cascade with a long interconnection delay

This paper addresses the output feedback stabilization of an ODE–PDE cascade. The PDE takes the form of a 1-D reaction–diffusion equation. The output of the ODE enters into the PDE via a Dirichlet/Neumann/Robin boundary condition. It is assumed that both the output of the ODE and the output of the PDE, selected as a boundary Dirichlet trace, are available for feedback control. The proposed control strategy takes the form of a finite-dimensional observer-based controller. Under a suitable structural controllability property, we show that the reported control strategy achieves the exponential stabilization of the plant when the order of the observer is selected large enough. We then demonstrate how such a control strategy can be adapted and augmented with a predictor component in order to achieve the stabilization of the above mentioned PDE–ODE cascade when the output of the ODE enters into the PDE with an arbitrarily long delay.

Design Space Exploration of Interconnect Materials for Cryogenic Operation: Electrical and Thermal Analyses

With Copper (Cu) Interconnects causing performance bottleneck at single nanometer nodes due to increase in resistivity size effects viz., grain boundary scattering and surface scattering, there has always been scavenging for alternate interconnect materials. Although the Cu resistivity value decreases at cryogenic temperature, the problems continue to persist. In this work, we study three alternate interconnect materials specifically for 77K High Performance Compute applications. We select the materials based on their resistivity value at 77K for 7nm node computed using Fuchs-Sondheimer-Mayadas-Shatzkes (FS-MS) models. We analyze the delay of the interconnects, understand repeater insertion as a function of wire length, evaluate repeater count and energy at system level and perform IR drop analysis by showing through detailed analytical models that Ru, Rh and Al can provide appreciable improvements over Cu at 77K. The delay of interconnects reduces by 1-3.75% for Ru, 1.5-7.25% for Rh and 4.4-17.8% for Al across the BEOL stack while repeater counts decrease by 10%, 15% and 37% for Ru, Rh and Al respectively at 77K. We investigate thermal and reliability aspects of interconnect design including electromigration, Joule Heating and maximum allowed current densities again proving that Ru (9%), Rh (18%) and Al (63%) outperform Cu at 77K. Finally, we study the effects of various Low-k dielectric materials on the interconnect capacitance and thermal behavior for Cu as well as three alternate materials noting that, even though thermal conductivity of dielectrics decrease at 77K, the Joule Heating will not be as worse as one might expect.

Minimization of crosstalk noise and delay using reduced graphene nano ribbon (GNR) interconnect

In this paper, we proposed a side-contact reduced graphene nano-ribbon (SC-RGNR) interconnect model to reduce crosstalk noise and delay for next generation high performance integrated circuit (IC) design. The SC-RGNR interconnect structure is designed with latest 11 nm ITRS (International Technological Road Map for Semiconductor) technology node. A comparative crosstalk noise, delay and power consumption analysis has been performed with side-contact graphene nano-ribbon (SC-GNR) interconnect model. The SC-RGNR and SC-GNR interconnect both model parameters are applied in standard (STD) bus and staggered (STAGG) bus model with different interconnect lengths (10 μm–500 μm) and four standard mean free paths (MFP) (i.e., 300 nm, 419 nm, 1000 nm and 1200 nm) values. Five different switching conditions (i.e., SP1 to SP5) are applied on tri-interconnect driver-load circuit to check the performance of SC-RGNR and SC-GNR interconnect in-terms of crosstalk noise and delay. In our analysis, it is shown that, the higher MFP based SC-RGNR interconnect shows less dynamic delay compared with SC-GNR interconnect for both STD and STAGG interconnect model with worst-case switching condition (SP5) and best-case switching condition (SP2). For STD interconnect model with worst-case switching condition (SP5) the dynamic delay of SC-RGNR interconnect is ∼1.33–2.62 × lesser than SC-GNR interconnect. Similarly, for STAGG model with worst-case switching condition (SP5) the dynamic delay of SC-RGNR interconnect is ∼1.26–2.16 × lesser than SC-GNR interconnect. Although, the STAGG interconnect model performs ∼1.5–2 × faster than STD interconnect model in terms of delay. In our analysis, it is also observed that, the output noise peak is ∼2.91–17.5 × less in SC-RGNR compared with SC-GNR at 500 μm interconnect length and higher MFP. Our analysis also shows that, the switching power consumption in SC-RGNR is ∼1.66–2.2 × less than SC-GNR for both STD and STAGG model for both best and worst-case switching condition (SP2 and SP5).

Timing-Aware Layer Assignment for Advanced Process Technologies Considering via Pillars

Interconnect delay is a key factor that affects the chip performance in layer assignment. Particularly in the advanced process technologies of 5 nm and beyond, interconnect delay has grown significantly due to the increase of circuit scale. Moreover, coupling effect existed in wires reduces the accuracy of delay evaluation. On the other hand, the size of vias is often ignored in layer assignment, which enlarges the mismatch between global routing and detailed routing. To solve these problems, we propose <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VPT</i> , a timing-aware layer assignment algorithm considering via pillars, which includes the following five key techniques: 1) via pillar structure combined with nondefault-rule (NDR) wires is adopted to form a net delay optimization system for advanced process technologies; 2) a synthetical model that can adapt to varying types and sizes of both vias and wires is designed to evaluate overflow effectively; 3) a sorting strategy is devised to reduce uncertainty of layer assignment flow and improve stability of the proposed algorithm; 4) an awareness strategy based on multiaspect congestion assessment is designed to reduce overflow significantly; and 5) a net scalpel algorithm is devised to minimize the maximum delay of nets, so that the timing behaviors can be improved systematically. The experimental results on multiple benchmarks confirm that the proposed algorithm leads to lower delay and less overflow, while achieving the best solution quality among the existing algorithms with the shortest runtime.

Decentralized Constrained Tracking Control for Interconnected Nonlinear Systems with Interconnection and Input Delays

Decentralized Constrained Tracking Control for Interconnected Nonlinear Systems with Interconnection and Input Delays

Analysis of the Impact of Electrical and Timing Masking on Soft Error Rate Estimation in VLSI Circuits

Due to continuous CMOS technology downscaling, Integrated Circuits (ICs) have become more susceptible to radiation-induced hazards such as soft errors. Thus, to design radiation-hardened and reliable ICs, the Soft Error Rate (SER) estimation constitutes an essential procedure. An accurate SER evaluation is provided based on a SPICE-oriented electrical masking analysis, combined with a TCAD characterization process. Furthermore, the proposed work analyzes the effect of a Static Timing Analysis (STA) methodology and the actual interconnection delay on SER evaluation. An analysis of the generated Single Event Multiple Transients (SEMTs) and the circuit operating frequency that are related to the SER estimation is also discussed. Various benchmarks, synthesized utilizing a 45 nm and 15 nm technology, are employed, and the experimental results demonstrate the SER variation as the device node scales down.

Writing-only in-MRAM computing paradigm for ultra-low power applications

In-memory computing (IMC) is demonstrated as a breakthrough in terms of few interconnection delay and high density. Computing in nonvolatile memory, e.g., spin-transfer-torque (STT)-MRAM, is expected to realize near-zero leakage power consumption and unlimited endurance. Based on circuit-level reconfiguration, we propose a in-MRAM computing scheme to perform data storage and Boolean arithmetic simultaneously. This proposed scheme is implemented with a 28-nm CMOS process and a 40-nm Magnetic tunnel junction (MTJ) compact model. The self-write-termination method achieves 84.7% writing energy saving within 20-ns write access duration. A high-level simulation is performed with 28×28 pixels image similarity analysis. It demonstrates 24% dynamic energy reduction comparing to the previous method. The proposed in-MRAM computing scheme is also applicable to other resistive memories with the identical bit-cell structure.

An Efficient Delay Estimation Model for High Speed VLSI Interconnects

In this paper a closed-form matrix rational model for the computation of step and finite ramp responses of Resistance Inductance Capacitance (RLC) interconnects in VLSI circuits is presented. This model allows the numerical estimation of delay and overshoot in lossy VLSI interconnects. The proposed method is based on the U-transform, which provides rational function approximation for obtaining passive interconnect model. With the reduced order lossy interconnect transfer function, step and finite ramp responses are obtained and line delay and signal overshoot are estimated. The estimated delay and overshoot values are compared with the Euder method, Pade method and HSPICE W- element model. The 50% delay results are in good agreement with those of HSPICE within 0.5% error while the overshoot error is within 1% for a 2 mm long interconnect. For global lines of length more than 5 mm in SOC (system on chip) applications, the proposed method is found to be nearly four times more accurate than existing methods.

An improved exponential stability criterion and distributed H ∞ filter design for spatially interconnected discrete-time systems with time-varying delay

This paper proposes an improved exponential stability analysis criterion and designs a distributed filter for a spatially interconnected discrete-time time-varying delay (SIDTD) system. Firstly, combining the Wirtinger-based inequality with reciprocally convex combination inequality, a new and less conservative exponential stability criterion, which guarantees the well-posedness, exponential stability, and performance of the SIDTD system, is reduced to standard linear matrix inequalities. Moreover, we design a distributed structure-preserving filter based on the new stability result. The structure-preserving filter and the delay-free filter can be obtained by employing the Finsler lemma. Finally, the validity and advantages of the derived results are shown by a numerical example and a practical example.