Degradation Of Gate Oxide Integrity Research Articles

Degradation of Gate Oxide Integrity by Formation of Tiny Holes by Metal Contamination of Raw Wafer

Heavy metal atoms (such as Cu) spontaneously undergo a dissolution reaction when they come into contact with silicon. Most investigations in this extensively studied area begin with a clean, bare wafer and focus on metal contamination during the IC manufacturing stage. In this work, the effect of Fe and Cu contamination on raw wafers was elucidated. When two batches of raw wafers are scheduled, one uncontaminated and one with various degrees of contamination ranging from 0.1 to 10 ppb undergo the typical steps of the 90 nm LOGIC complementary metal–oxide–semiconductor (CMOS) semiconductor manufacturing process. The main contribution of this work is the discovery of a previously unidentified cause of gate oxide leakage: the formation of tiny holes by metal contamination during the wafer manufacturing stage. Because tiny holes are formed, a spontaneous reaction can occur even with at very low metal concentration (0.2 ppb), revealing that the wafer manufacturing stage is more vulnerable to metal contamination than the IC manufacturing stage and therefore requires stricter contamination control.

Stability Enhancement of Polysilicon Thin-Film Transistors Using Stacked Plasma-Enhanced Chemical Vapor Deposited SiO2/SiNx Gate Dielectric

The use of a double-layer, plasma-enhanced chemical vapor deposited SiO2/SiNx film as a gate dielectric material for polysilicon thin-film transistors was investigated in order to reduce mobile ion contamination and to improve gate oxide integrity degradation. We observed that the interposed silicon nitride film between the gate electrode and the SiO2 gate insulator prevents the incorporation of mobile ions into the SiO2 film, and also increases the breakdown voltage of the gate-insulating film. The mobile ion densities for the double SiO2/SiNx and single SiO2 gate dielectrics (no interposed SiNx layer between the gate electrode and SiO2 gate insulator) were 1.3 ×1011 and 1.7 ×1012/cm2, respectively. The breakdown fields at the 50% failure points in the Weibull plots for the double and single dielectric cases were 8 and 5 MV/cm, respectively. We conclude that the silicon nitride layer of the double gate insulator film minimizes ion contamination, leading to the enhancement of breakdown characteristics.

Mechanisms and solutions to gate oxide degradation in flash memory by tunnel-oxide nitridation engineering

Increasing attention has been paid to the peripheral gate-oxide integrity degradation of Flash memory devices that is induced by the tunnel-oxide nitridation. In this letter, the mechanisms of tunnel-oxide nitridation-induced degradation are characterized. We report that both a local oxide thinning effect and nitrogen residue will impact the integrity of gate-oxide. Minimizing the local thinning effect with an in situ steam generation (ISSG) oxidation process and removing the nitrogen residues from the silicon wafer surface by either an additional sacrificial oxide process or over-dip are proven to be useful in recovering the gate-oxide integrity. An optimum approach with the tunnel-oxide nitridation is proposed in this work that results in comparable or even better gate-oxide property than other approaches that have no tunnel-oxide nitridation process.

Hafnium or Zirconium High-k Fab Cross-Contamination Issues

Hf and Zr contamination during immersion in process solutions is most likely to occur in neutral and caustic solutions. Both Hf and Zr contamination are introduced onto the wafer surface if they are present in an ammonium hydroxide peroxide mixture solution (which is caustic), but such contamination is removed using existing acid cleans. Large amounts of wafer-to-wafer cross contamination occurs in plasma etch tools. Particles can cause cross contamination in a thermal reactor during high-temperature anneals of high-k dielectric layers. Residual surface cross contamination does not diffuse into the wafers during thermal processing. If contamination remains on a wafer, gate oxide integrity degradation is only observed at high concentrations. Near surface minority carrier lifetime is also affected, but bulk lifetime is not.

The Copper Contamination Effect of Al2 O 3 Gate Dielectric on Si

We have studied the Cu contamination effect on 4.2 nm thick metal-oxide semiconductor (MOS) capacitors with an equivalent-oxide thickness (EOT) of 1.9 nm. In contrast to the large degradation of gate oxide integrity of control 3.0 nm MOS capacitors contaminated by Cu, the 1.9 nm EOT MOS devices have good Cu contamination resistance with only small degradation of gate dielectric leakage current, charge-to-breakdown, and stress-induced leakage current. This strong Cu contamination resistance is similar to oxynitride (with high nitrogen content), but the gate dielectric has the advantage of higher κ value and lower gate dielectric leakage current. © 2004 The Electrochemical Society. All rights reserved.

The impact of post-polysilicon gate process on ultra-thin gate oxide integrity

The impact of rapid-thermal spike anneal after source/drain extension (SDE) implant on the integrity of ultra-thin gate oxide is studied. It is found that SDE anneal can cause increasingly severe gate oxide integrity (GOI) degradation as the gate oxide becomes thinner. The GOI degradation can be suppressed by growing a thin oxide on the polysilicon gate or inserting an offset spacer prior to the SDE implant step. Additionally, a close correspondence between GOI degradation, gate to source/drain leakage current, and the bridging of dense polysilicon lines is observed, indicating a common origin for these phenomena.

The abnormality in gate oxide failure induced by stress-enhanced diffusion of polycrystalline silicon

An abnormal gate oxide failure was found in DRAM using deep submicron technology. Contrary to the general dielectric extrinsic breakdown, the degradation of gate oxide integrity was shown only in the gate lines of a small dimension, not in those of a large dimension. This abnormal oxide breakdown is due to the voids in the polycrystalline silicon, which are at the center of gate line with a small dimension. These voids are formed by both chemical potential difference and stress enhanced diffusion of polycrystalline silicon. The suppression method of these voids using sufficient source of polycrystalline silicon is proposed.

Degradation of ultrathin oxides by iron contamination

Iron-contaminated oxides of metal-oxide-semiconductor devices were investigated to study gate oxide integrity (GOI) degradation dependence on oxide thickness for oxide thicknesses from 3 to 5 nm and iron densities from 4×1010 to 1.4×1012 cm−3. In contrast to other publications, we show that oxides as thin as 3 nm show gate oxide integrity degradation, especially for the higher iron densities. But even for the low iron density we observe GOI degradation for all oxides.

Study of forming a p+ poly-Si gate by inductively coupled nitrogen plasma nitridation of the stacked poly-Si layers

Formation of a p+ poly-Si gate by using the stacked poly-Si layers that are nitridized by using inductively coupled nitrogen plasma (ICNP) has been studied. The stacked poly-Si gate structure consists of three poly-Si layers with thickness of 50, 50, and 100 nm, respectively. As for the control samples that do not receive nitrogen plasma nitridation, when they are annealed at 900 °C, the gate oxide integrity is significantly degraded and the flat-band voltage (Vfb) shift is large, attributable to considerable boron penetration through gate oxide. If the ICNP treatment is directly done with respect to the gate oxide layer, the Vfb shift can be considerably reduced, but the resultant gate oxide integrity is even much worse than that for the control samples. However, for the specimens that sustain ICNP treatment immediately after the deposition of the first poly-Si layer, the degradation of gate oxide integrity and the Vfb shift are significantly alleviated even at 900 °C. Hence, the process scheme that employs the stacked poly-Si gate nitridized by the ICNP treatment is highly available for forming a p+ poly-Si gate.

Effects of CoSi2 on p+ Polysilicon Gates Fabricated by BF 2 + Implantation into CoSi/Amorphous Si Bilayers

The integrity of thin gate oxide structures fabricated by implanting ions into bilayered CoSi/amorphous silicon films and subsequent annealing has been studied as a function of cobalt silicide thickness and implantation energy. Significant degradation of gate oxide integrity and flatband voltage shifts were found with increasing cobalt silicide thickness and annealing temperature. It is shown that although thinner cobalt silicide can result in excellent gate dielectric integrity it also leads to worse thermal stability at a high annealing temperature. Moreover, shallower implantation depth and lower annealing temperature can reduce the boron penetration, but depletion effects in polycrystalline silicon gates are caused accordingly. Hence, appropriate process conditions, involving trade‐offs among thickness, implantation energy and annealing temperature, must be used to optimize the device performance while retaining the thin dielectric reliability.

Impact of Iron Contamination and Roughness Generated in Ammonia Hydrogen Peroxide Mixtures (SC1) on 5 nm Gate Oxides

Immersion of hydrophobic (HF‐last) silicon wafers into iron‐contaminated ammonia peroxide mixtures (SC1 solution) results in the formation of so‐called clustered light point defects. At these sites, increased surface microroughness and local higher iron concentrations are observed. Also, device yield is strongly affected by the presence of iron contamination into SC1 solutions. It is demonstrated that only dHF/dHCl cleans are capable of completely eliminating any yield loss resulting from iron‐contaminated SC1 treatments. The experimental observations can be understood based on the following model. Hydrogen peroxide decomposition is catalyzed by iron. Iron contamination (present in SC1 solution as insoluble hydroxide aggregates) deposits on the silicon wafer surface upon immersion of the latter. While doing so, the adsorbed iron cluster continues to catalyze further hydrogen peroxide decomposition. Local hydrogen peroxide depletion exposes the bare silicon surface to the etching activity of the ammonia. Local etching of the silicon creates microroughness. Additionally, iron becomes inhomogeneously incorporated into the bulk of the chemical oxide formed. Gate oxide integrity degradation can be observed to correlate with these sites. A subsequent acid clean is only efficient in eliminating the induced yield loss, if the oxide layer (with built‐in iron) is completely removed.

Influence of silicon-wafer loading ambients in an oxidation furnace on the gate oxide degradation due to organic contamination

Organic contaminants adsorbed on the surface of silicon wafers do not always cause the degradation of gate-oxide integrity (GOI) degradation but very little information is available on the ambient atmosphere when wafers are loaded in an oxidation furnace. It has been found in this work that GOI is degraded when wafers having organic contamination are loaded in a nitrogen atmosphere, but that GOI degradation does not occur when the wafers are loaded in an oxygen-containing ambient. In a high-temperature nitrogen atmosphere, carbon remains in silicon dioxides, while in an oxygen-containing ambient, the organic contaminants will be oxidatively degraded and evaporated, so carbon does not remain on the surface.