PSNR Degradation Research Articles

On the Performance of Self‐Concatenated Coding for Wireless Mobile Video Transmission Using DSTS‐SP‐Assisted Smart Antenna System

In the current age of advanced technologies, there is an escalating demand for reliable wireless systems, catering to the high data rates of mobile multimedia applications. This article presents a novel approach to the concept of Self‐Concatenated Convolutional Coding (SECCC) with Sphere Packing (SP) modulation via Differential Space‐Time Spreading‐ (DSTS‐) based smart antennas. The two transmitters provide transmit diversity which is capable of recuperating the signal from the effects of fading, even with a single receiving antenna. The proposed DSTS‐SP SECCC scheme is probed for the Rayleigh fading channel. The SECCC structure is developed using the Recursive Systematic Convolutional (RSC) code with the aid of an interleaver. Interleaving generates randomness in exchange for extrinsic information between the constituent decoders. Iterative decoding is invoked at the receiving side to enhance the output performance by attaining fruitful convergence. The convergence behaviour of the proposed system is investigated using EXtrinsic Information Transfer (EXIT) curves. The performance of the proposed system is ascertained with the H.264 standard video codec. The perceived video quality of DSTS‐SP SECCC is found to be significantly better than that of the DSTS‐SP RSC. To be more precise, the proposed DSTS‐SP SECCC system exhibits an Eb/N0 gain of 8 dB at the PSNR degradation point of 1 dB, relative to the equivalent rate DSTS‐SP RSC. Similarly, an Eb/N0 gain of 10 dB exists for the DSTS‐SP SECCC system at 1 dB degradation point when compared with the SECCC scheme dispensing with the DSTS‐SP approach.

On the Performance of Wireless Video Communication Using Iterative Joint Source Channel Decoding and Transmitter Diversity Gain Technique

In this research work, we have presented an iterative joint source channel decoding- (IJSCD-) based wireless video communication system. The anticipated transmission system is using the sphere packing (SP) modulation assisted differential space-time spreading (DSTS) multiple input-multiple output (MIMO) scheme. SP modulation-aided DSTS transmission mechanism results in achieving high diversity gain by keeping the maximum possible Euclidean distance between the modulated symbols. Furthermore, the proposed DSTS scheme results in a low-complexity MIMO scheme, due to nonemployment of any channel estimation mechanism. Various combinations of source bit coding- (SBC-) aided IJSCD error protection scheme has been used, while considering their identical overall bit rate budget. Artificial redundancy is incorporated in the source-coded stream for the proposed SBC scheme. The motive of adding artificial redundancy is to increase the iterative decoding performance. The performance of diverse SBC schemes is investigated for identical overall code rate. SBC schemes are employed with different combinations of inner recursive systematic convolutional (RSC) codes and outer SBC codes. Furthermore, the convergence behaviour of the employed error protection schemes is investigated using extrinsic information transfer (EXIT) charts. The results of experiments show that our proposed R a t e − 2 / 3 SBC-assisted error protection scheme with high redundancy incorporation and convergence capability gives better performance. The proposed R a t e − 2 / 3 SBC gives about 1.5 dB E b / N 0 gain at the PSNR degradation point of 1 dB as compared to R a t e − 6 / 7 SBC-assisted error protection scheme, while sustaining the overall bit rate budget. Furthermore, it is also concluded that the proposed R a t e − 2 / 3 SBC-assisted scheme results in E b / N 0 gain of 24 dB at the PSNR degradation point of 1 dB with reference to R a t e − 1 SBC benchmarker scheme.

Low Power Motion Estimation Algorithm and Architecture of HEVC/H.265 for Consumer Applications

High-quality videos like high-definition (HD) and ultra HD became an essential requirement in recent applications such as security surveillance, television system, etc. However, due to increase in resolution of the videos, the volume of visual information data increases significantly, which became a challenge for storage, transmission and processing the HD video data. The new video compression standard, high efficient video coding (HEVC), achieved two-fold video efficiency improvements as compared to H.264/AVC using efficient compression techniques. Motion estimation (ME) is one of the computationally intensive blocks in video CODEC. In HEVC, the complexity of ME further increases due to a large processing unit and flexible partitioning of the prediction unit (PU). In this paper, we proposed a low power ME algorithm and architecture of the HEVC for consumer applications. The proposed algorithm and architecture utilizes sub-sampling, data reuse, pixel truncation and adaptive search range techniques for reducing the computational power. Simulations result shows that the proposed ME algorithm requires an average of 53.82% fewer search points as compared to the reference software HM with a small degradation in PSNR and little increment in bit-rate. The proposed architecture is simulated and synthesized using standard 90 nm technology. The proposed ME architecture can process $3840\times2160$ @ 30 fps video sequences with only 4.5193 mm2 of the area and 8.192 KB of SRAM. The operating frequency of the proposed architecture is 250 MHz with 151.7619 mW of power.

Multi-level complexity reduction for HEVC multiview coding

Standardized in 2014, multiview extension of high efficiency video coding (MV-HEVC) offers significantly better compression performance of up to 50% for multiview and 3D videos compared to multiple independent single view HEVC coding. However, the extreme high computational complexity of MV-HEVC demands significant optimization of the encoder. In this work, we propose a series of optimization techniques at various levels of abstraction: non-aggregation massively parallel motion estimation (ME) and disparity estimation (DE) for prediction units, fractional and bidirectional ME/DE, quantization parameter-based early termination of coding tree unit (CTU), and optimized resource-scheduled wave front parallel processing for CTU. When evaluated over three views for all available official multiview video coding test sequences, proposed optimization outperforms the anchor encoder by average factor of 5.4 at the cost of 4.4% bitrate (DBR) increase at no loss in PSNR, or alternatively a PSNR degradation of 0.12 dB at no change to the DBR.

A Low-Cost Hardware Design of a 1-D SPIHT Algorithm for Video Display Systems

This paper presents low-cost compressors for video display systems, which compress video data to reduce the size of the frame memory in a display panel in a television or a smartphone. The hardware solution exploits the discrete wavelet transform (DWT) and 1-D set partitioning in hierarchical trees (SPIHT) to support the raster-scan processing order in a display system and meet the fixed target compression ratio (CR). However, the compression efficiency and hardware cost often increase in proportion to the block size and thus, designing a compressor with low cost but high fidelity is challenging. This paper proposes a generic partitioned SPIHT algorithm, which achieves a low-cost design for mobile devices by allowing various sizes of partitioned sub-blocks. By taking advantage of DWT decomposition properties, the proposed algorithm partitions a coding block into sub-blocks, each of which can be processed independently. The independent coding operations among multiple sub-blocks allow the size of the hardware buffer to be decreased, by storing the temporary results only for an individual sub-block. However, the proposed sub-block coding slightly decreases the compression efficiency when each sub-block is compressed with the same target CR. To reduce the drop-off in the compression efficiency, the boundary-pixel handling in DWT is exploited and the proposed partitioned SPIHT method adjusts the target CR for each sub-block depending on the potential quality loss. When compared with the previous 1-D design, experimental results show that the hardware gate count and internal memory are reduced by 59.34% and 75%, respectively. Furthermore, the proposed boundary handling and bit-allocation schemes mitigate the PSNR degradation due to the sub-block coding by 1.11 dB.

An adaptive block-based matching algorithm for crowd motion sequences

For crowd analytics and surveillance systems, motion estimation is an essential first step. Lots of crowd motion estimation algorithms have been presented in the last years comprising pedestrian motion. However, algorithms based on optical flow and background subtraction have numerous limitations such as the complexity of the computation in the presence of high dense crowd and sudden motion changes. Therefore, a novel estimation algorithm is proposed to measure the motion of crowd with less computational complexity and satisfy the real time requirements. The proposed algorithm is based on block-based matching, particle advection, and social force model. By the block-based matching, the motion is estimated in each frame, and the corresponding motion field is created. The particle advection process provides more information about the behavior of pedestrians groups, their tracked trajectories and the boundary of each group segment. Relying on the social force model, a predicted direction of the motion vectors (MV) could be measured significantly. Subsequently, the block-based technique is combined with the social force model to obtain the accurate motion vector with the less possible number of search points. The experimental results indicate that the proposed method achieves high performance by reducing the search points, particularly when many collision situations or obstacles exist in the scenes. Considering the reduction in the computational complexity, the quality of degradation is very low. In all cases, average PSNR degradation of the proposed algorithm is only 0.09.

A new approach with enhanced accuracy in zero motion prejudgment for motion estimation in real-time applications

For improving the accuracy and speed of motion estimation, a refined threshold estimation technique for zero motion prejudgment (ZMP) has been proposed in this manuscript. Various fixed or dynamically varying threshold techniques reported in literature treat all the blocks whose sum of absolute differences (SAD) lie below a particular threshold as stationary blocks (SB). However, in reality these blocks have high probability to be SB but not certain. Also SB with abrupt or irregular variations may not be detected with these techniques. The proposed two-level ZMP technique with its dynamic threshold at level 1 attempt to identify SB blocks with much more accuracy and precision. Level 2 of it has very high probability to identify the SB with large and abrupt distortions that are left in level 1. The proposed technique for ZMP can be applied before any fast motion estimation algorithm (FMEA). Adaptive rood pattern search algorithm (ARPS) is used as FMEA for comparing the performance of the proposed ZMP technique with other fixed and dynamic threshold techniques described in the literature. Simulation results clearly indicate that the proposed technique shows very promising results—significantly reduces the decision errors, improves the video quality in terms of PSNR and SSIM and reduces memory requirement for residual frames in comparison to fixed and dynamic threshold techniques for ZMP. Real-time applications contain sequences with higher frame rates as 30 and 60 fps. The proposed technique gives promising results on sequences with higher as well as lower frame rates. Further, proposed ZMP is able to save computations by 95–99 % in comparison to full search (FS) algorithm with small degradation in PSNR and SSIM. The proposed technique when embedded with fast motion estimation algorithm (ARPS) can reduce the computations up to 70 % depending upon the presence of stationary blocks with negligible degradation in video quality. All this has been achieved by enhancing the accuracy in determination of stationary blocks in comparison to other ZMP techniques.

FITD: Fast Intra Transcoding from H.264/AVC to high efficiency video coding based on DCT coefficients and prediction modes

In the literatures, the designs of H.264 to High Efficiency Video Coding (HEVC) transcoders mostly focus on inter transcoding. In this paper, a fast intra transcoding system from H.264 to HEVC based on discrete cosine transform (DCT) coefficients and intra prediction modes, called FITD, is proposed by using the intra information retrieved from an H.264 decoder for transcoding. To design effective transcoding strategies, FITD not only refers block size of intra prediction and intra prediction modes, but also effectively uses the DCT coefficients to help a transcoder to predict the complexity of the blocks. We successfully use DCT coefficients as well as intra prediction information embedded in H.264 bitstreams to predict the coding depth map for depth limitation and early termination to simplify HEVC re-encoding process. After a HEVC encoder gets the prediction of a certain CU size from depth map, if it reaches the predicted depth, the HEVC encoder will stop the next CU branch. As a result, the numbers of CU branches and predictions in HEVC re-encoder will be substantially reduced to achieve fast and precise intra transcoding. The experimental results show that the FITD is 1.7–2.5 times faster than the original HEVC in encoding intra frames, while the bitrate is only increased to 3% or less and the PSNR degradation is also controlled within 0.1dB. Compared to the previous H.264 to HEVC transcoding approaches, FITD clearly maintains the better trade-off between re-encoding speed and video quality.

An H.264 High-Profile Intra-Prediction with Adaptive Selection Between the Parallel and Pipelined Executions of Prediction Modes

A high-profile H.264 intra-frame encoder is suitable for low-cost and low-power applications and capable of providing enhanced compression efficiency. The high-profile is targeting the high-resolution videos. Thus, the encoding speed should be faster than or comparable to the baseline-profile. In previous work related to a hardware-based baseline-profile intra-frame encoder, a speed-up is achieved by the early termination of the intra modes and by an increase in the rate of hardware utilization only under one of the serialized and parallel schedules. This paper proposes a novel pipeline schedule for a hardware-based high-profile intra-prediction scheme in which the $8 \times 8$ prediction is performed in Stage 1 and $4 \times 4$ , $16 \times 16$ and chroma predictions are executed during Stage 2. The processing time of Stage 2 is efficiently accelerated based on the result of the $8 \times 8$ prediction in Stage 1. According to the distribution of each mode, the schedule is adaptively selected between parallel and pipeline schedules. To increase the hardware utilization of the $8 \times 8$ prediction, the order of prediction modes and the inverse vertical transform is adaptively adjusted. In addition, early termination of the prediction modes is employed for a fast $8 \times 8$ prediction. The proposed $8 \times 8$ intra-prediction is implemented and verified as an entire intra-frame encoder. Experimental results show that the average number of cycles necessary to process one MB for videos with resolutions of $1920 \times 1080$ and $3840 \times 2160$ are only 269 and 253 cycles, respectively. Compared to JM13.2, the bitrate is increased by 1.13% on average with a small PSNR degradation of 0.06 dB. The difference in the rate-distortion performance between the proposed high-profile intra-prediction scheme and JM 13.2 is not significant, whereas the achieved speed-up due to the proposed schemes is considerable compared to the conventional hardware-based intra-prediction encoders.

Tampering Detection in Compressed Digital Video Using Watermarking

This paper presents a method to detect video tampering and distinguish it from common video processing operations, such as recompression, noise, and brightness increase, using a practical watermarking scheme for real-time authentication of digital video. In our method, the watermark signals represent the macroblock's and frame's indices, and are embedded into the nonzero quantized discrete cosine transform value of blocks, mostly the last nonzero values, enabling our method to detect spatial, temporal, and spatiotemporal tampering. Our method can be easily configured to adjust transparency, robustness, and capacity of the system according to the specific application at hand. In addition, our method takes advantage of content-based cryptography and increases the security of the system. While our method can be applied to any modern video codec, including the recently released high-efficiency video coding standard, we have implemented and evaluated it using the H.264/AVC codec, and we have shown that compared with the existing similar methods, which also embed extra bits inside video frames, our method causes significantly smaller video distortion, leading to a PSNR degradation of about 0.88 dB and structural similarity index decrease of 0.0090 with only 0.05% increase in bitrate, and with the bit correct rate of 0.71 to 0.88 after H.264/AVC recompression.

Pixel-Wise Unified Rate-Quantization Model for Multi-Level Rate Control

In this paper, we present a pixel-wise unified rate quantization (R-Q) model for a low-complexity rate control on configurable coding units of high efficiency video coding (HEVC). In the case of HEVC, which employs hierarchical coding block structure, multiple R-Q models can be employed for the various block sizes. However, we found that the ratios of distortions over bits for all the blocks are a nearly constant because of employment of the rate distortion optimization technique. Hence, one relationship model between rate and quantization can be derived from the characteristic of similar ratios of distortions over bits regardless of block sizes. Thus, we propose the pixel-wise unified R-Q model for HEVC rate control working on the multi-level for all block sizes. We employ a simple leaky bucket model for bit control. The rate control based on the proposed pixel-wise unified R-Q model is implemented on HEVC test model 6.1 (HM6.1). According to the evaluation for the proposed rate control, the average matching percentage to target bitrates is 99.47% and the average PSNR degradation is 0.76 dB. Based on the comparative study, we found that the proposed rate control shows low bit fluctuation and good RD performance, compared to R-lambda rate control for long sequences.

Multi-view Rate Control based on HEVC for 3D Video Services

In this paper, we propose two rate control algorithms for multi-view extension of HEVC with two rate control algorithms adopted in HEVC and analyze the multi-view rate control performance. The proposed multi-view rate controls are designed on HEVC-based multi-view video coding (MV-HEVC) platform with consideration of high-level syntax, inter-view prediction, etc. not only for the base view but also for the extended views using the rate control algorithms based on URQ (Unified Rate-Quantization) and R-lambda model adopted in HEVC. The proposed multi-view rate controls also contain view-wise target bit allocation for providing the compatibility to the base view. By allocating the target bitrates for each view, the proposed multi-view rate control based on URQ model achieved about 1.83% of average bitrate accuracy and 1.73dB of average PSNR degradation. In addition, about 2.97% of average bitrate accuracy and 0.31dB of average PSNR degradation are achieved with the proposed multi-view rate control based on R-lambda model.

Enhanced Motion Estimation Algorithm based on Block Mean Deviation and Sorting Approaches

Technologies such as TV, HDTV, 3D TV, Video telephony, Video surveillance, and Wireless multimedia communication have put a great demand for development of efficient and fast video compression algorithms. Motion Estimation (ME) is being used to achieve and increase the effectiveness of video compression. Traditional ME algorithms are not suited to current market demands. This paper proposes a Motion Estimation algorithm which is based on Partial Distortion Search and Sorting schemes. It tries to minimize the calculations by rejecting those partial distortion calculations early which would yield bad motion vectors. It is based on the concept that if deviation of sub-block is higher, then its contribution to total SAD (Sum of Absolute difference) is also higher. It uses this approach along with sorting of sub-blocks on the basis of their deviation. The results show that this algorithm can save 60 to 70 % of computation costs as incurred by traditional algorithms as well as performs well than other Partial Distortion Algorithms. Also PSNR degradation is very less and is 0.017 on average.

경성 실시간 동작을 보장하는 움직임 추정 알고리즘

본 논문에서는 움직임 추정기의 하드웨어 자원이 유한하게 주어졌을 때, 동작 중에 적응적으로 작업량을 제어함으로서 주어진 경성 실시간 동작 조건 내에서 최적의 성능을 얻는 움직임 추정 기법을 제안한다. 제안하는 움직임 추정 기법은 작업량과 탐색 단계를 적응적으로 결정함으로서 경성 실시간 동작을 보장하는 범위 내에서 최대한의 탐색을 수행할 수 있다. 이 기법은 하드웨어 크기를 기존 기법의 1/4~1/400까지 줄이면서도 PSNR 저하는 0.02~0.44 dB에 불과하며, 하드웨어의 사용 효율도 기존 기법의 3.7~21.5배에 달하였다. 이 기법은 기존의 고속 탐색 기법에 쉽게 적용이 가능하므로 실시간 처리가 가능한 인코더 칩을 설계하는데 유용하다. This paper proposes a motion estimation algorithm with run-time adaptive workload control. It has optimized performance within limited hardware resources while guaranteeing hard realtime operation. It performs maximum searches within hard realtime constraints, since it determines search steps and workload adaptively. It reduces the hardware size to 1/4~1/400 of conventional algorithms, while its PSNR degradation is only 0.02~0.44 dB. It can be easily applied to most conventional fast algorithms, so it is useful to design realtime encoder chips.

Buffer structure optimized VLSI architecture for efficient hierarchical integer pixel motion estimation implementation

Integer pixel motion estimation (IME) is one crucial module with high complexity in high-definition video encoder. Efficient algorithm and architecture joint design is supposed to tradeoff multiple target parameters including throughput capacity, logic gate, on-chip SRAM size, memory bandwidth, and rate distortion performance. Data organization and on-chip buffer structure are crucial factors for IME architecture design, accounting for multiple target performance tradeoff. In this work, we combine global hierarchical search and local full search to propose hardware efficient IME algorithm, and then propose hardware VLSI architecture with optimized on-chip buffer structure. The major contribution of this work is characterized by: (1) improved hierarchical IME algorithm with presearch and deliberate data organization, (2) multistage on-chip reference pixel buffer structure with high data reuse between integer and fraction pixel motion estimations, (3) highly reused and reconfigurable processing element structure. The optimized data organization and buffer structure achieves nearly 70 % buffer saving with less than average 0.08, 0.12 dB the worst case, PSNR degradation compared with full search based architecture. At the hardware cost of 336 and 382 K logic gate and 20 kB SRAM, the proposed architecture achieves the throughput of 384 and 272 cycles per macroblock, at system frequency of 95 and 264 MHz for 1080p and QFHD @30fps format video coding.

Efficient Region-of-Interest Scalable Video Coding with Adaptive Bit-Rate Control

This work relates to the regions-of-interest (ROI) coding that is a desirable feature in future applications based on the scalable video coding, which is an extension of the H.264/MPEG-4 AVC standard. Due to the dramatic technological progress, there is a plurality of heterogeneous devices, which can be used for viewing a variety of video content. Devices such as smartphones and tablets are mostly resource-limited devices, which make it difficult to display high-quality content. Usually, the displayed video content contains one or more ROI(s), which should be adaptively selected from the preencoded scalable video bitstream. Thus, an efficient scalable ROI video coding scheme is proposed in this work, thereby enabling the extraction of the desired regions-of-interest and the adaptive setting of the desirable ROI location, size, and resolution. In addition, an adaptive bit-rate control is provided for the region-of-interest scalable video coding. The performance of the presented techniques is demonstrated and compared with the joint scalable video model reference software (JSVM 9.19), thereby showing significant bit-rate savings as a tradeoff for the relatively low PSNR degradation.

Enhanced AMBTC for Image Compression using Block Classification and Interpolation

ABSTRACT Block Truncation Coding (BTC) is a fast moment preserving lossy image compression technique. This paper proposes a original image. Though some data is removed, for Human two-level compression scheme. In the first level of compression, the blocks are categorized into high-detail blocks and low-detail blocks. The high detail blocks are stored or transmitted in the form of a bit plane (16 bits), and two statistical moments; high mean and low mean (16 bits). Only the mean values are stored for low detailed blocks. In second level of compression, the interpolation technique is incorporated as part of the proposed method for further bit rate reduction. The performance of the method is tested with standard images Lena, Cameraman Boats, Bridge, Baboon and Kush. The proposed scheme achieves better coding efficiency with a slight degradation in PSNR when compared to existing methods. General Terms Image Compression Keywords image compression; high-detail block; low-detail block; interpolation; bpp; PSNR;

Mode decision acceleration for scalable video coding through coded block pattern

This paper presents a fast mode decision to accelerate the encoding process of scalable video coding (SVC) through coded block pattern (CBP) analysis. CBP contains residual information of each macroblock (MB) and provide cues for mode prediction in encoding process. The proposed algorithm makes use of the existing mode information in base layer (BL), enhancement layer (EL) and CBP to remove invalid modes for the mode prediction of the current MB in EL coding. Also, the EL’s modes in the highest temporal level of a group of picture are determined by high correlation exists in adjacent frames. Experimental results show that the proposed algorithm saves an average of 68% of EL motion estimation time with minor degradation in PSNR and with few bitrate increase of SVC quality and spatial scalabilities when compared to JSVM 9.19.14. Our algorithm outperforms the best-known method by 17% EL motion estimation time saving in average.

Probability Constrained Search Range Determination for Fast Motion Estimation

In this paper, we propose new adaptive search range motion estimation methods where the search ranges are constrained by the probabilities of motion vector differences and a search point sampling technique is applied to the constrained search ranges. Our new methods are based on our previous work, in which the search ranges were analytically determined by the probabilities. Since the proposed adaptive search range motion estimation methods effectively restrict the search ranges instead of search point sampling patterns, they provide a very flexible and hardware-friendly approach in motion estimation. The proposed methods were evaluated and tested with JM16.2 of the H.264/AVC video coding standard. Experiment results exhibit that with negligible degradation in PSNR, the proposed methods considerably reduce the computational complexity in comparison with the conventional methods. In particular, the combined method provides performance similar to that of the hybrid unsymmetrical-cross multi-hexagon-grid search method and outstanding merits in hardware implementation.

움직임 보상된 웨이블릿 기반의 비디오 코딩 시스템에 적용 가능한 임베디드 압축 코덱 알고리즘

In this paper, a low-complexity embedded compression (EC) Codec algorithm for the wavelet video coder is applied to reduce excessive external memory requirements. The EC algorithm is used to achieve a fixed compression ratio of 50 % under the near-lossless-compression constraint. The EC technique can reduce the 50 % memory requirement for intermediate low-frequency coefficients during multiple discrete wavelet transform stages compared with direct implementation of the wavelet video encoder of this paper. Furthermore, the EC scheme based on a forward adaptive quantization and fixed length coding can save bandwidth and size of buffer between DWT and SPIHT to 50 %. Simulation results show that our EC algorithm present only PSNR degradation of 0.179 and 0.162 dB in average when the target bit-rate of the video coder are 1 and 0.5 bpp, respectively.