Spiking neural networks (SNNs) have the potential to closely mimic the information processing of biological brains, by using massive neurons that are interconnected in a complex network. Recent researches have considered using electronic hardware circuits to SNN implementations to meet real-time processing requirements. Network-on-Chips (NoCs) have been widely used to develop such SNN circuits as their interconnections can offer stable interconnectivity for neuron communications with high throughput and real-time execution. However, its scalability is limited due to expensive and complex NoC routers which leads to high energy consumption and large area utilization. Therefore, a minimally buffered deflection router (MBDR) is proposed in this work to address the scalability challenge of the hardware SNNs. It employs a deflection router technique to remove most of the inter-buffers and other expensive components of the conventional routers. Moreover, a novel flow controller is developed in MBDR to further reduce power consumption. Compared to existing approaches, experimental results show that based on 90-nm CMOS technology the area and power consumption of the proposed router are reduced by ~ 86% and ~ 88%, respectively. In the meantime, system throughput is maintained at a high level.