Defect Review Scanning Electron Microscope Research Articles

An Effective Approach for Associating the Sources of Defect Signatures to Process Zones

A semiconductor wafer undergoes various processing steps before it is transformed from a plain silicon wafer to one populated with thousands of integrated circuits. Each of these processing steps is susceptible to specific types of defects. Some defects may not be captured by in-line inspection tools or may not be sampled during defect review-scanning electron microscope and are carried over multiple processing steps. Such defects can be discovered at the end of the fabrication procedure, which requires process engineers to trace back the manufacturing processes that caused these defects. Despite the success of most current methods that detect defects during wafer fabrication, most of these methods are inable to accurately associate the source of an individual defect type to a specific semiconductor processing step. We believe that this limitation can be overcome by considering the carry-over of defect signatures rather than individual defects. We propose in this paper a system called step-defect contribution analyzer (SDCA) that detects defect signatures on semiconductor wafers and overcomes the limitations outlined above. SDCA allows process engineers to trace back and associate the source of a final defectivity discovered at the end of the fabrication procedure to specific defect signatures carried over multiple process zones. We experimentally evaluated the quality of SDCA by measuring its prediction accuracy. Results revealed marked prediction accuracy.

A Fast QC Method for Testing Contact Hole Roughness by Defect Review SEM Image Analysis

We propose a new and fast method for monitoring contact hole roughness (CHR), which can be a major yield-loss factor for advanced SRAMs. The method, defect-review scanning electron microscopy (SEM) image processing, can monitor CHR 100 times faster than the conventional method by critical dimension (CD)-SEM. The speed can facilitate faster identification of process countermeasures by, for example, making detailed monitoring of CHR variation within a wafer practicable. Results for CHR obtained by both new and conventional methods show similar trends for differences in process conditions. Also, we experimentally confirmed the new method's measuring variation of the rate of deformed contact holes.

Voltage Contrast for Gate-Leak Failures Detected by Electron Beam Inspection

We examine a technique for enhancing the voltage contrast (VC) of a failure analysis (FA) tool, defect review scanning electron microscope (DR-SEM). For an SRAM, we demonstrate a dependence of gate-leak VC on the relative angle (RA) between the direction of beam scanning by the FA tool and the lengthwise direction of the gate electrode. Experimental results show that better VC results are obtained when RA is zero, in other words, a beam's scan-line is parallel with the SRAM gate. We propose a simple qualitative resistor-capacitor model to explain this phenomenon. With the help of this VC enhancement technique of the FA tool, we could tune the electron beam inspection (EBI) recipe to an appropriate condition quicker. The cycle time of EBI recipe tuning was shortened from five to two days. As a result, correct EBI evaluation results of countermeasure experiments led us to a yield enhancement solution within a shorter period of time.