Deep Submicron CMOS Technology Research Articles

Radiation-tolerant all-digital clock generators for HEP applications

The emergence of high-precision timing systems in High Energy Physics motivates new developments in the domain of clock generation and distribution. Particularly, when considering the challenges arising from adopting advanced deep-submicron CMOS technology nodes, all-digital PLL and clock and data recovery (CDR) architectures constitute a promising option for future high energy physics (HEP) experiments. Both LC oscillator and ring oscillator-based all-digital PLL/CDR blocks for front-end ASICs were studied, designed, manufactured and characterized. Their design, the hardening considerations, as well as the performance obtained with these circuits are presented in this article.

Physical Design of VCO with Wide Frequency Tuning Range Using Deep Submicron CMOS Technology

Abstract: This paper presents a new design approach of CMOS voltage controlled oscillator (VCO) with low power and wide frequency tuning range. A novel current starved delay cell has been proposed based on dual delay path architecture. The results have been obtained in 45 nm CMOS technology with supply voltage 1 V. The proposed VCO achieves a controllable frequency range from 1.81 GHz to 10.55 GHz with a wide tuning range. The control voltage (Vctrl) has been varied from 0.3V to 1V for obtaining the different output frequencies. The power dissipation of proposed VCO is 34.932 uW with current consumption as 0.079 mA at a control voltage of 1V and very optimised surface area as 14.8µm2. Keywords: Current starved delay cell, Low Power, Tuning range, VCO, etc.

A Proposed Technique to Improve the Performance of Receiver by Using Linear Gm-C Low-Pass Filter for mmwave Band Applications

Deep submicron CMOS technology proves to be suitable for transceiver design at mmwave band frequencies. At the same time, it has been a challenging task to obtain high performance at mmwave frequencies. In this paper, a 28[Formula: see text]GHz low-IF receiver frontend with improved performance by incorporating a proposed linear Gm-C low-pass filter (LPF) is presented using 40[Formula: see text]nm CMOS technology targeting for 5G wireless system. A mathematical expression for the linearity of the proposed filter is derived and compared with the basic filter model. The improved linearity (IIP3 of [Formula: see text][Formula: see text]dBm) of the proposed filter results in the enhancement of linearity and hence the Figure of Merit (FOM) of the receiver with the proposed filter. The receiver attains a conversion gain of 34.6[Formula: see text]dB, a noise figure of 3.1[Formula: see text]dB and IIP3 of [Formula: see text][Formula: see text]dBm. The total current drawn by the receiver is 27.3[Formula: see text]mA at a 1.2[Formula: see text]V power supply. The overall FOM of the receiver with the proposed filter is improved to 0.30 whereas the FOM of the receiver with the basic filter model is 0.13. The area of the receiver is [Formula: see text] whereas the proposed filter occupies [Formula: see text].

Analytical Modeling of Short-Channel Fully-Depleted Triple Work Function Metal Gate (TWFMG) SOI MESFET

In this paper, a new structure: triple work function metal gate SOI MESFET, intended for integration into the deep-submicron CMOS technology, is proposed. The gate of the device consists of three different materials which are laterally merged into one. The difference in the work function of dissimilar gate materials introduces two step changes in the profile of channel potentials which screens the threshold-defining region of the channel from the impact of drain potential. Therefore, the effects associated with DIBL are significantly alleviated. On the basis of exact solution of the Poisson equation in the channel region, an analytical subthreshold model for the device is developed. Using the analytical data, the device has been characterized and compared with conventional device in terms of potential function, DIBL, threshold voltage roll-off, and subthreshold swing. The TCAD simulator ATLAS from Silvaco has been used to validate the analytical results. The feasibility of device fabrication is also demonstrated.

Memristor: A Unique Discovery for Reducing Power

A Process parameter variation has increasing, which results unpredictable device behaviour, due to occurrence of deep submicron CMOS technology. As the time passage this issue is exasperated by low power requirements which are approaching transistor operation into sub threshold regime. Principally for portable devices efficient, capable and process variation amiable memory is the most demandable in the market. In designing of low power memories, leakage power is observant parameter to design low power devices, because leakage power plays a dominant role in the total power utilization of the devices. In this paper, simple 6T SRAM formed with memristor has compared with the technique based 6T SRAM for the various parameters like total power and leakage power.

A Robust and Efficient Fault-Resilient Rad Hard ADPLL

Typically, classical PLLs adopt analog design methods. However integrating PLL with noise-prone application environment is highly tedious and somewhere confined. As per current knowledge majority of PLLs apply Analog Loop Filters (ALFs) and Voltage Controlled Oscillators which are practically highly complicated to integrate with noisy environment. Even the traditional PLLs can’t be ported to the advanced processors. In last few years, the emergence of deep-submicron CMOS technologies have enabled digitization of major traditional analog circuits, comprising the analog PLLs that as a result could be vital to overcome above mentioned issues and to achieve more efficient solution than classical analog implementation.

Low voltage base current cancellation circuit

ABSTRACT A low voltage base current cancellation circuit is proposed. It is useful in minimising the non-linearity due to base current in Complementary to Absolute Temperature current references and temperature independent current references and in improving the accuracy of bipolar transistor current mirrors. In today’s deep submicron CMOS technologies, parasitic bipolar transistors have a low current gain factor (β) and their base current cannot be neglected which adversely impacts the accuracy of the generated reference currents. By substantially eliminating the base current component, the accuracy of the generated reference current is improved significantly. The proposed base current cancellation circuit has been designed in 16nm FinFet technology for a wide temperature range of −40°C to 150°C and a supply voltage range of 1.8V ± 10%. The simulation results show that the proposed base current cancellation circuit significantly reduces the non-linearity in the Complementary to Absolute Temperature reference current.

Radiation effects on Single-Photon Avalanche Diodes manufactured in deep submicron CMOS technology

CMOS Single-Photon Avalanche Diodes (SPADs) have been introduced recently in many scientific applications. This paper reports on the performance, in terms of Dark Count Rate (DCR), of a photo-sensor based on CMOS SPADs. The device has been subjected to an accurate investigation, in order to evaluate its behaviour in a radiation environment. Several irradiation tests were conducted, and a complete survey of their effects on the DCR behaviour has been performed. An overall increase in the DCR level has been measured, meaning that new defects have been introduced in the space charge region of the SPADs. Furthermore, for a fraction of the SPADs, DCR measurements show a Random Telegraph Signal (RTS) temporal pattern.

Analysis of Total Ionizing Dose effects for highly scaled CMOS devices in Low Earth Orbit

Abstract Total Ionizing Dose (TID) effects are an essential concern for integrated devices that are operating in space environment. We present in this work an extensive study of TID effects in Deep-Submicron and Nanoscale CMOS technologies. Principal aspects are the changes of the transistors I-V characteristics due to TID effects, the variation of the threshold voltage and the impact of radiation on the carrier densities and mobility as well as on the electrical potentials and the leakage currents. Further, we discuss a potential solution that reduces TID effects in CMOS devices. The device level simulations consider a satellite application that orbits in Low Earth Orbit (LEO), leading to dose levels of up to 500 krad(Si). Results clearly indicate the high impact of TID on the transistor parameters, enforcing the designer to consider countermeasures in order to guarantee the circuits reliability.

An accurate behavioral model for single-photon avalanche diode statistical performance simulation

An accurate behavioral model is presented to simulate important statistical performance of single-photon avalanche diodes (SPADs), such as dark count and after-pulsing noise. The derived simulation model takes into account all important generation mechanisms of the two kinds of noise. For the first time, thermal agitation, trap-assisted tunneling and band-to-band tunneling mechanisms are simultaneously incorporated in the simulation model to evaluate dark count behavior of SPADs fabricated in deep sub-micron CMOS technology. Meanwhile, a complete carrier trapping and de-trapping process is considered in afterpulsing model and a simple analytical expression is derived to estimate after-pulsing probability. In particular, the key model parameters of avalanche triggering probability and electric field dependence of excess bias voltage are extracted from Geiger-mode TCAD simulation and this behavioral simulation model doesn't include any empirical parameters. The developed SPAD model is implemented in Verilog-A behavioral hardware description language and successfully operated on commercial Cadence Spectre simulator, showing good universality and compatibility. The model simulation results are in a good accordance with the test data, validating high simulation accuracy.

Fully-Digital Blind Compensation of Non-Linear Distortions in Wideband Receivers

Digital post-distortion is becoming an increasingly attractive solution to compensate for the non-linearities of RF receivers implemented in deep submicron CMOS technologies. A very promising technique which provides flexibility and robustness is the frequency spreading based digital post-distortion. This paper focuses on the analysis of this approach for wideband receivers and its main limitations, such as the anti-alias filter (AAF) impact. As a matter of fact, distortions filtered by the AAF can degrade the correction performance. To overcome this problem, a novel solution based on mimicking the AAF frequency response in the digital domain is proposed. Aspects regarding the estimation and the algorithm convergence are also studied: the noise effect and the choice of the free frequency band. Furthermore, two other techniques are developed to improve the modeling and the correction of the memory effect using, respectively, a bank of filters and two-step architecture. The proposed techniques are demonstrated by simulations and measurements on a multi-channel receiver suited for DVB-T applications. The receiver is based on a 1-GHz bandwidth RF front-end followed by a 2.7-GHz 13-bit analog-to-digital converter.

Aging signature properties and an efficient signature determination tool for online monitoring

Increased reliability problems in deep sub-micron CMOS technologies have led to a dramatic decrease of lifetime of analog integrated circuits. To palliate this problem, several reliability-aware design approaches have been developed. Reconfigurable circuit design is one of those approaches, which is based on reconfiguring the circuit considering degradation in circuit performances. Sense & React (S & R) approach is the well-known reconfigurable design approach, where degradation in circuit performances are sensed and a pre-established recovery operation is applied to heal the circuit. In practice, indirect measurements are preferred during sense operation, in which electrical quantities are measured in order to determine time to recovery. Determination of the time to recover is the most critical part of a S & R system. One or more circuit variables are selected out of all measurable circuit quantities. The selected signature should have some attributes to be used as the aging signature to reduce the measurement cost. However, efficient aging signature properties have not been defined in the literature yet. Moreover, the designer determines the aging signature manually by performing an iterative search and evaluation on aging simulation results, and there is no tool to ease this time consuming process. This paper clearly describes the aging signature properties and proposes an automatic signature selection tool that determines the most efficient signature for sense operation.

Quantitative Optimization of Highly Efficient Dedicated CORDIC Macros for SoCs in Deep-Submicron CMOS Technologies

The CORDIC algorithm is frequently used in many applications and dedicated CORDIC macros are attractive components for SoCs e.g., as hardware accelerators to Application-Specific Instruction-set Processors. Therefore, there is a wide variety of CORDIC specifications. In order to achieve high area and energy efficiency for a given specification, a systematic exploration of the design space is required. Due to the features of today’s deep-submicron CMOS technologies, there are strong interactions between the design levels which makes a quantitative optimization challenging. In this contribution, an attractive approach based on algebraic cost models is described, which allows for exploring the design space with adequate accuracy and in reasonable time. The benefits from this approach are demonstrated by an evaluation for different exemplary CORDIC specifications.

A Novel Paradigm to Eliminate Timing Violations using AHL

Objectives: This Paper presents a novel low power design approach for multipliers to eliminate timing violations. There are two major issues which are concentrated in this paper are positive bias temperature instability and negative bias temperature instability. Both the things affect the speed of transistor and leads to timing violations, which intern leads to the failure of an entire system. Methods: In this work, bypassing multiplier is used with adaptive hold logic. The implementation is done in 180 nm deep submicron CMOS technology. Findings: power consumption and error rate is studied after employing the AHL. Improvements: The experimental result shows that the performance of multipliers with AHL improved 72.8% when compared to existing methods and consumes less power.

Comprehensive understanding of dark count mechanisms of single-photon avalanche diodes fabricated in deep sub-micron CMOS technologies

The dark count noise mechanisms of single-photon avalanche diodes (SPADs) fabricated in deep sub-micron (DSM) CMOS technologies are investigated in depth. An electric field dependence of tunneling model combined with carrier thermal generation is established for dark count rate (DCR) prediction. Applying the crucial parameters provided by Geiger mode TCAD simulation such as avalanche triggering probability and electric field distribution in the SPAD avalanche region, the individual contribution of each noise source to DCR is calculated for several SPADs in DSM CMOS technologies. The model calculation results reveal that the trap-assisted tunneling is the main DCR generation source for these DSM CMOS SPADs. With the increase of doping levels in the device avalanche region, the band-to-band tunneling will be the dominant factor that could lead to the higher DCR in scaled DSM CMOS technologies.

Comparative performance analysis and complementary triode based CMFB circuits for fully differential class AB symmetrical OTAs with low power consumption

SummaryIn this paper we extend the figures of merit for class AB symmetrical OTAs to the fully differential case and compare topologies from the literature. This analysis shows that the power consumption of the CMFB can have a significant role in determining the efficiency of the OTA, but on the other hand a CMFB is needed both to set the desired output common mode voltage and to improve the CMRR. We propose the complementary triode CMFB, i.e. a triode CMFB applied both at the NMOS and PMOS current mirrors, as suitable for class AB symmetrical OTAs, and show some case studies in deep submicron CMOS technology to assess the effectiveness of the proposed solution. Copyright © 2015 John Wiley & Sons, Ltd.

Temperature effect on hetero structure junctionless tunnel FET

For the first time, we investigate the temperature effect on AlGaAs/Si based hetero-structure junctionless double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute device for ultra scaled deep-submicron CMOS technology, having very good device characteristics such as an improved subthreshold slope (< 60 mV/decade at 300 K) and very small static leakage currents. The improved subthreshold slope and static leakage current confirms that it will be helpful for the development of future low power switching circuits. The 2-D computer based simulation results show that OFF-state leakage current is almost temperature independent for the proposed device structure.

The Race for the Extra Decibel: A Brief Review of Current ADC Performance Trajectories

At the turn of this century, there was widespread concern that the performance of analog-to-digital converters (ADCs) might have reached a saturation point and would, in fact, deteriorate as we began to scale into deep submicron CMOS technology. The past 15 years of innovation have clearly refuted such fears. Driven by a combination of application pull, architectural modifications, and relentless optimization, we have seen steady improvements in several key performance metrics.

Impact analysis of deep-submicron CMOS technologies on the voltage and temperature independence of a time-domain sensor interface

This article presents a comparative study of a time-based sensor interface implemented in two standard CMOS technologies, 130 and 40 nm. The interface uses a ring oscillator to generate a pulse-width modulated signal of which the duty cycle is proportional to the sensor value. This results in a highly temperature- and supply voltage-independent output signal. Simulation results of both implementations are compared in terms of temperature and voltage dependence, power consumption and linearity. Also the noise propagation from the oscillator to the PWM output is discussed. Afterwards, the simulation results are compared to measured values of a 40-nm CMOS implementation. It is concluded that the interface topology is a robust solution for deep-submicron wireless sensor nodes in dynamic environments.

Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives

In the past few years, extensive research efforts pursued by both the industry and the academia have lead to major improvements in the performance of Analog to Digital Converters (ADCs) and Time to Digital Converters (TDCs). ADCs achieving 8–10bit resolution, 50–100MHz conversion frequency and less than 1mW power consumption are the today׳s standard, while TDCs have reached sub-picosecond time resolution. These results have been made possible by architectural upgrades combined with the use of ultra deep submicron CMOS technologies with minimum feature size of 130nm or smaller. Front-end ASICs in which a prompt digitization is followed by signal conditioning in the digital domain can now be envisaged also within the tight power budget typically available in high density tracking systems. Furthermore, tracking detectors embedding high resolution timing capabilities are gaining interest. In the paper, ADC׳s and TDC׳s developments which are of particular relevance for the design front-end electronics for semiconductor trackers are discussed along with the benefits and challenges of exploiting such high performance building blocks in implementing the next generation of ASICs for high granularity particle detectors.