Dedicated Hardware Modules Research Articles

Satellite Localization of IoT Devices Using Signal Strength and Doppler Measurements

Determining the location of wireless devices is vital in many applications. However, global navigation satellite system technologies require a dedicated hardware module installed in the device, imposing additional power and cost constraints. This letter presents a framework to passively localize ground wireless devices by a constellation of satellites using only the signal strength and Doppler measurements. We derive the likelihood of the measurements and then compare two methods: first by applying a stochastic optimizer, namely simulated annealing, and second using Markov Chain Monte Carlo (MCMC) algorithm to draw a sample distribution of the estimated location and the device Equivalent Isotropic Radiated Power (EIRP). Simulation results under realistic Internet-of-things scenarios show that reliable IoT device localization can be achieved using several satellites.

Comprehensive machine data acquisition through intelligent parameter identification and assignment

In today’s highly competitive manufacturing environment, process data monitoring continues to be of high priority, but often relies on modern communication interfaces being provided by PLC manufacturers. This paper proposes an alternative approach in which data is acquired automatically from various PLC models through available interfaces. Multiple Machine Learning algorithms are incorporated to identify machine parameters, which are then assigned to appropriate machine information models. All functionalities can be provided by a dedicated hardware module or as software modules on IPCs. The proposed approach can be integrated into existing Industry 4.0 efforts to accelerate digitalization in challenging environments.

IoT Based Voice Controlled Multitasking System for Home

Internet of Things is a rising innovation that makes our world more astute. In recent years, there has been immense development in the realm of insightful gadgets for home mechanization. Such contraptions are planned so as to facilitate communication among individuals and everyday home obligations. This paper exhibits a voice-controlled smart home with multi-functions using ESP32 as the wireless choice. Voice control (using human voice to control any load like light, fan, ac, geyser, motor etc.). The voice-commands are recognized by a dedicated hardware module and the recognized data is sent to database using ESP32. On the accepting unit, raspberry pi peruses the information from the database and deciphers the directions verbally expressed by the client and controls the family unit apparatuses.

An FPGA-based controller design for a five degrees of freedom robot for repairing hydraulic turbine blades

This paper presents the design of a FPGA-based embedded system for controlling and monitoring a 5-D.O.F. spherical topology robot specialized in welding for repairing hydraulic turbine blade surfaces. The embedded controller has been developed using a hardware/software co-design approach in which a Nios II soft-processor is configured on a Terasic DE2-115 development kit, along with several support modules (timer, JTAG, I/O, memory and RS-232). Additionally, other dedicated hardware modules were designed to control the motors, encoders, the welding system and a joystick while daughter boards were designed to provide an opto-coupled connection from the FPGA kit to their respective external peripherals. Furthermore, the control system also provides a RS-232 interface to the pan-tilt, which provides the last two degrees-of-freedom to the manipulator. While the control algorithm runs on the FPGA it receives spatial coordinate points via a USB connection maintained with a PC where higher level software uses image processing techniques to map the turbine surface using a 3D LASER scanner and compute the welding trajectories. Finally, the validity of the system is verified with repeatability and welding tests.

An Embedded System for a High-Speed Manipulator With Single Time Scale Visual Servoing

This study presents the development of an embedded system for controlling a high-speed robotic manipulator. Three different types of controllers including hardware proportional derivative (PD), software PD, and single time scale visual servoing are considered in this study. Novel field programmable gate array (FPGA) technology was used for implementing the embedded system for faster execution speeds and parallelism. It is comprised of dedicated hardware and software modules for obtaining sensor feedback and control signal (CT) estimation, providing the control signal to the servovalves. A NIOS II virtual soft processor system was configured in the FPGA for implementing functions that are computationally expensive and difficult to implement in hardware. Quadrature decoding, serial peripheral interface (SPI) input and output modules, and control signal estimation in some cases was carried out using the dedicated hardware modules. The experiments show that the proposed controller performed satisfactory control of the end effector position. It performed single time scale visual servoing with control signal updates at 330 Hz to control the end effector trajectory at speeds of up to 0.8 ms−1. The FPGA technology also provided a more compact single chip implementation of the controller.

Automated Design Flow for Multi-Functional Dataflow-Based Platforms

The implementation of processing platforms supporting multiple applications by runtime reconfigurations on dedicated hardware modules requires the solution of different problems. These problems are notably not-trivial since both platform and application complexities increase year after year. As a consequence, the design process is both time and resource demanding. System configuration along with resources management and mapping remain one of the most challenging problem, particularly when runtime adaptation is required. In this direction, the ISO/IEC SC29WG11 committee (MPEG) has developed the so called MPEG-RVC standards ISO/IEC 23001-4 and 23002-4. This standard provides specifications of video codecs in the form of dataflow programs. In this paper, an integrated design flow to derive optimized multi-functional platforms directly from disjoined high-level specifications is presented. To the authors' best of knowledge, such an optimization, synthesis and mapping methodology for coarse-grained reconfigurable systems design does not exist within the MPEG-RVC framework. The design flow presented in this paper leverages on an integrated set of independently designed tools, all supporting the RVC standard. Results assessment has been carried out on three different scenarios: an MPEG-RVC decoder, a standard baseline MPEG-RVC JPEG codec and a generalized reconfigurable multi-quality JPEG encoder. For all these scenarios, the proposed design flow has been targeted for a Xilinx Virtex 5 FPGA. Results show how this approach is capable of yielding a reconfigurable design that preserves the original performance of the stand alone non-reconfigurable platform providing, at the same time, considerable area savings featuring a larger set of functionalities. Moreover, platforms programmability, on the basis of the required functionality ID, is automatically handled at runtime without any designer effort.

A Fast Performance Estimation Framework for System-Level Design Space Exploration

This paper presents a fast performance estimation framework and an performance estimation method for design space exploration at system level. As the complexity of embedded systems grows, design space exploration at a system level plays a more important role than before. In the system-level design, system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various Processing Elements (PEs) including processors and dedicated hardware modules. A mapping decision is evaluated by simulation or FPGA-based prototyping. Designers iterate mapping and evaluation until all design requirements are met. In order to shorten the evaluation time, we have developed a fast design space exploration framework which combines our system-level design tool, named SystemBuilder, and a newly developed fast performance estimation tool, named SystemPerfEst. SystemPerfEst is based on trace-based simulation method. The trace is obtained as the result of SystemBuilder, and the trace is fed to SystemPerfEst smoothly. Since the estimation of a design candidate finishes in about one second, design space exploration of a number of design candidates can be performed with SystemPerfEst in a practical time. A case study on design space exploration of a JPEG decoder system demonstrates the effectiveness of our framework.

Efficient Resource Sharing Architecture for Multistandard Communication System

The Fourth Generation (4G) network is expected to serve mobile subscribers under dynamic network conditions and offer any type service: anytime, anywhere, and anyhow. Two such technologies that can respond to the above said services are Wideband Code Division Multiple Access (WCDMA) and Orthogonal Frequency Division Multiplexing (OFDM). The main contribution of this paper is to propose a dedicated hardware module which can reconfigure itself either to the OFDM Wireless LAN or WCDMA standard. In this paper, Fast Fourier Transform (FFT) algorithm is implemented for OFDM standard, and rake receiver is implemented for WCDMA standard. Initially efficient implementations of these two algorithms are tested separately and identified the resources utilized by them. Then the new hardware architecture, which configures to any one of these two standards on demand, is proposed. This architecture efficiently shares the resources needed for these two standards. The proposed architecture is simulated using ModelSimSE v6.5 and mapped onto a virtex 5 FPGA device (xc5v1x30ff324) using the tool Xilinx ISE 9.2i, and the results are compared with the standard approach. These results show that the proposed hardware architecture utilizes less number of resources compared to the conventional Reconfigurable Receiver Architecture System.

Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation

As the complexity of embedded systems grows, design space exploration at a system level plays a more important role than before. In the system-level design, system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various Processing Elements (PEs) including processors and dedicated hardware modules. A mapping decision is evaluated by simulation or FPGA-based prototyping. Designers iterate mapping and evaluation until all design requirements are met. We have developed two profilers, a process profiler and a memory profiler, for FPGA-based performance analysis of design candidates. The process profiler records a trace of process activations, while the memory profiler records a trace of channel accesses. According to mapping of processes to PEs, the profilers are automatically configured and instrumented into FPGA-based system prototypes by a system-level design tool that we have developed. Designers therefore need to manually modify neither the system description nor the profilers upon each change of process mapping. In order to demonstrate the effectiveness of our profilers, two case studies are conducted where the profiles are used for design space exploration of AES encryption and MPEG4 decoding systems.

Vector Processing as a Soft Processor Accelerator

Current FPGA soft processor systems use dedicated hardware modules or accelerators to speed up data-parallel applications. This work explores an alternative approach of using a soft vector processor as a general-purpose accelerator. The approach has the benefits of a purely software-oriented development model, a fixed ISA allowing parallel software and hardware development, a single accelerator that can accelerate multiple applications, and scalable performance from the same source code. With no hardware design experience needed, a software programmer can make area-versus-performance trade-offs by scaling the number of functional units and register file bandwidth with a single parameter. A soft vector processor can be further customized by a number of secondary parameters to add or remove features for a specific application to optimize resource utilization. This article introduces VIPERS, a soft vector processor architecture that maps efficiently into an FPGA and provides a scalable amount of performance for a reasonable amount of area. Compared to a Nios II/s processor, instances of VIPERS with 32 processing lanes achieve up to 44× speedup using up to 26× the area.

A Practical Biosignal-Based Human Interface Applicable to the Assistive Systems for People with Motor Impairment

An alternative human interface enabling the handicapped with severe motor disabilities to control an assistive system is presented. Since this interface relies on the biosignals originating from the contraction of muscles on the face during particular movements, even individuals with a paralyzed limb can use it with ease. For real-world application, a dedicated hardware module employing a general-purpose DSP was implemented and its validity tested on an electrically powered wheelchair. Furthermore, an additional attempt to reduce error rates to a minimum for stable operation was also made based on the entropy information inherent in the signals during the classification phase. In the experiments in which 11 subjects participated, it was found most of them could control the target system at their own will, and thus the proposed interface could be considered a potential alternative for the interaction of the severely handicapped with electronic systems.

A Biosignal-Based Human Interface Controlling a Power-Wheelchair for People with Motor Disabilities

An alternative human interface enabling people with severe motor disabilities to control an assistive system is presented. Since this interface relies on the biosignals originating from the contraction of muscles on the face during particular movements, even individuals with a paralyzed limb can use it with ease. For real-world application, a dedicated hardware module employing a general-purpose digital signal processor was implemented and its validity tested on an electrically powered wheelchair. Furthermore, an additional attempt to reduce error rates to a minimum for stable operation was also made based on the entropy information inherent in the signals during the classification phase. In the experiments, most of the five participating subjects could control the target system at their own will, and thus it is found that the proposed interface can be considered a potential alternative for the interaction of the severely disabled with electronic systems. disabled lead a more improved life have been addressed, and corresponding effort has also been made in the fields related to rehabilitation engineering and user interface (UI) development. One attempt attracting considerable attention in those fields involves the utilization of biosignals such as an electroencephalogram (EEG) or electromyogram (EMG) obtainable from the human body as a means for interaction with the surrounding world. In the field of brain-computer interface (BCI), meaningful information derived directly from a user's brain activity has been used to manipulate systems. However, despite the definite advantage unique to EEG signals that allows a system to be controlled only by one's thoughts, the poor signal-to-noise ratios in the spontaneous EEG signals and the lack of consistency in the signal patterns still make their application impractical. Compared to such drawbacks of EEG signals, EMG signals have more possibility to be applied to a wide range of users due to their easy controllability and insensitiveness to noises (1). In this letter, a special interface based on these EMG signals that runs in a stand-alone mode is proposed, and its usefulness as a communication channel is investigated through a practical test on an electrically powered wheelchair, called a power-wheelchair throughout this letter.

Instruction-level test methodology for CPU core self-testing

TIS is an instruction-level methodology for processor core self-testing that enhances instruction set of a CPU with test instructions. Since the functionality of test instructions is the same as the NOP instruction, NOP instructions can be replaced with test instructions. Online testing can be accomplished without any performance penalty. TIS tests different parts of the processor and detects stuck-at faults. This method can be employed in offline and online testing of single-cycle, multicycle and pipelined processors. But, TIS is more appropriate for online testing of pipelined architectures in which NOP instructions are frequently executed because of data, control and structural hazards. Running test instructions instead of these NOP instructions, TIS utilizes the time that is otherwise wasted by NOPs. In this article, two different implementations of TIS are presented. One implementation employs a dedicated hardware modules for test vector generation, while the other is a software-based approach that reads test vectors from memory. These two approaches are implemented on a pipelined processor core and their area overheads are compared. To demonstrate the appropriateness of the TIS test technique, several programs are executed and fault coverage results are presented.

High Performance Network of PC Cluster Maestro

This paper presents a design, an architecture, and performance evaluation of high-performance network of PC cluster, called i> Maestro. Most networks of recent clusters have been organized based on WAN or LAN technology, due to their market availability. However, communication protocols and functions of such conventional networks are not optimal for parallel computing, which requires low latency and high bandwidth communication. In this paper, we propose two optimizations for high-performance communication: (1) transferring in burst as many packets as the receiving buffer accepts at once, and (2) having each hardware component pass one data unit to another in a pipelined manner. We have developed a network interface and a switch, which are composed of dedicated hardware modules to realize these optimizations. An implementatin of the message passing library developed on Maestro cluster is also described. Performance evaluation shows that the proposed optimizations can extract the potential performance of the physical layer efficiently and improve the performance in communication.

Bus guardians: an effective solution for online detection and correction of faults affecting system-on-chip buses

This paper presents a methodology for designing system-on-chip (SOC) interconnection architectures providing a high level of protection from crosstalk effects. An event driven simulator enriched with fault injection capabilities is exploited to evaluate the dependability level of the system being designed. The simulation environment supports several bus coding protocols and, thus, designers can easily evaluate different design alternatives. To enhance the dependability level of the interconnection architecture, we propose a distributed bus guardian scheme, where dedicated hardware modules monitor the integrity of the information transmitted over the bus and provide error correction mechanisms.

SIERA: a unified framework for rapid-prototyping of system-level hardware and software

Modern electronic systems contain a mix of software running on general-purpose programmable processors, algorithms hardwired into dedicated hardware such as custom boards and chips, electromechanical components, and mechanical interconnect and packaging. Far more time Is spent in designing the boards, writing the software to drive, and integrate the hardware, and other such system level issues, than is spent in designing any application-specific ICs that may be needed. Therefore a systems perspective of the design process is essential, as opposed to the conventional "chip-focused" approach. A design framework, called SIERA, for application-specific systems is described in which higher level aspects of system design, including software, multichip design issues present at the board level, and hardware-software integration are addressed, in addition to the design of individual custom chips. A high-level description of the system as a network of processes is mapped to a system architecture template consisting of multiple boards using dedicated hardware modules and ASIC's as well as software processes running on programmable hardware modules. Application of SIERA's design methodology to a multisensory robot control system is also presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

System level hardware module generation

In complex modern day electronic systems, far more time is spent in designing the boards, writing the software to drive and integrate the hardware, and other such system level issues, than is spent in designing any application-specific ICs that may be needed. Unfortunately, most of the research in computer-aided design has been focussed on the more glamorous ASIC design problem, as a result of which the design methodologies and tools at the system level are much more primitive than at the chip level. We have developed a design framework for application-specific systems, called SIERA, that addresses the higher level aspects of system design, including multichip design issues at the board-level, and hardware-software codesign and integration, in addition to the design of individual ASICs. SIERA allows rapid-prototyping of multiboard systems where the functionality is implemented using a mix of dedicated hardware modules and ASICs, as well as software running on programmable hardware modules. A key step in the design methodology provided by SIERA is that of generating the physical implementation of the system hardware from a description of the system architecture. The analogue of this problem at the chip level is referred to as silicon assembly or silicon compilation. In this paper we address this problem at the system level, and describe how the generation and interfacing of board-level modules, board-level physical design, simulation of custom boards, and the overall management of board design are handled in SIERA. While some of the problems could be solved by adapting or extending techniques from the existing ASIC design tools, others required new approaches. Case-studies of several real-life applications are also presented to demonstrate the effectiveness of the board-level physical design methodology embodied in SIERA compared to the traditional PCB design systems. >

Specialized module for full frame radiological image compression

The full-frame image compression technique was developed at the University of California, Los Angeles, specifically for radiological applications. Because this method is very innovative and unique, no commercially available hardware is able to process the algorithm with any efficiency. We have developed a dedicated hardware module for this purpose based on the latest technology. Specifications were determined from clinical requirements. Various important technical challenges were overcome by customized system designs, including a key concept of using dual-bus architecture for direct memory access transfer. We report on the status of a functional prototype and some image quality evaluations.

The discrete event simulation computer - DESC

Simulation of large models on digital computers is often limited by the high computational expenses. The Discrete Event Simulation Computer (DESC) reported here improves simulation performance through an exploitation of parallelism inherent in simulation, with regard to list processing, random number generation, statistical analysis and program control. The DESC consists of a set of nodes that communicate via FIFO-buffered channels (i.e. do not share memory among nodes). In order to achieve high system throughput dedicated hardware modules were developed; this includes new concepts for a list processor and a hardware random number generator for uniform deviates.The implementation of simulation languages such as SIMULA, SIMSCRIPT or GPSS is conceptually straightforward. We chose SIMULA as the frame language concept. Metrics applicable to simulation throughput and simulation costs are defined and compared with the CD CYBER 175.

A fast and flexible focal-plane detection system for electron scattering experiments

A multiwire drift chamber detection system, with a total of 1800 sense wires, operated in the focal planes of a two-spectrometer set-up for intermediate energy electron scattering experiments, is discussed. Two-dimensional reconstruction of single-arm events with a spatial resolution of 250 μm is performed by dedicated hardware modules with a peak event rate of 5 MHz. The system is rather flexible and expandable in its applications. Special features of the system used for single-arm and coincidence reactions are discussed and test results are presented to illustrate the overall performance of the detection system.