Decrease In Subthreshold Swing Research Articles

Enhanced performance of MoS2/SiO2 field-effect transistors by hexamethyldisilazane (HMDS) encapsulation

Scalable methods for improving the performance and stability of a field-effect transistor (FET) based on two-dimensional materials are crucial for its real applications. A scalable method of encapsulating the exfoliated MoS2 on the SiO2/Si substrate by hexamethyldisilazane (HMDS) is explored here for reducing the influence of interface traps and ambient contaminants. This leads to 25 times reduction in trap density, three times decrease in subthreshold swing, three times increase in the peak field-effect mobility, and a drastic reduction in hysteresis. This performance remains nearly the same after several weeks of ambient exposure of the device. This is attributed to the superhydrophobic nature of HMDS and the SiO2 surface hydrophobization by the formation of covalent bonds between the methyl groups of HMDS and silanol groups of SiO2.

Design and investigation of [formula omitted] based thin film transistors for high-speed AMLCD pixel circuit applications

The present paper reports a detailed comparative study of ZnO TFT with its two materials doped variants i.e., CdxZn1−xO &MgyZn1−yO. Three TFT structures are taken into consideration whose performances are explored in terms of analog, radio-frequency (RF), linearity, energy efficiency and noise analysis using a TCAD simulator. Further successful implementations of these TFT structures are done on an AMLCD pixel circuit. Tremendous improvement was observed in all the devices as well as circuit performance after material doping of Cd and Mg in ZnO. In device analysis, CdxZn1−xO TFT demonstrated superior current drive (ION/IOFF), subthreshold swing (SS) and mobility (μeff&μFE) to other structures, however with minor increase in kickback voltage in pixel circuit and vast decrease in time circuit delay. Percentage improvement in (ION/IOFF) ratio, effective mobility (μeff) and field mobility (μFE) for CdxZn1−xO based TFT are found to be ∼9041%, 196% and 111% with respect to ZnO TFT, whereas for MgyZn1−yO the improvements are ∼8253%, 136% and 105% only. At the same time percentage decrease in subthreshold swing and pixel circuit delay for CdxZn1−xO based TFT are ∼38% and ∼98% as compared to ZnO TFT, and the corresponding decrements for MgyZn1−yO are ∼3% and 92% respectively. With enhanced device and circuit performance, CdxZn1−xO has come up as promising channel material in TFT in view of low power high speed display circuit applications.

2-D Strain FET (2D-SFET) Based SRAMs—Part I: Device-Circuit Interactions

In this article, we analyze the characteristics of a recently conceived steep switching device 2-D Strain FET (2D-SFET) and present its circuit implications in the context of 6T-SRAM. We discuss the dependence of 2D-SFET characteristics on key design parameters, showing up to $2.7\times $ larger ON-current and 35% decrease in subthreshold swing when compared to 2D-FET. We analyze the performance of 2D-SFET (as drop-in replacement for standard 2D-FET) in 6T-SRAM for a range of design parameters and compare those to 2D-FET 6T-SRAM. 2D-SFET 6T-SRAM achieves up to 5.7% lower access time, 63% higher write margin, and comparable hold margin, but at the cost of comparable to 11% lower read stability and 16% increase in write time. In Part II of this article, we mitigate the read stability issues of 2D-SFET SRAMs by proposing ${V}_{{\mathrm {B}}}$ -enabled SRAM designs.

Sub-60 mV/decade switching in 2D negative capacitance field-effect transistors with integrated ferroelectric polymer

There is a rising interest in employing the negative capacitance (NC) effect to achieve sub-60 mV/decade (below the thermal limit) switching in field-effect transistors (FETs). The NC effect, which is an effectual amplification of the applied gate potential, is realized by incorporating a ferroelectric material in series with a dielectric in the gate stack of a FET. One of the leading challenges to such NC-FETs is the variable substrate capacitance exhibited in 3D semiconductor channels (bulk, Fin, or nanowire) that minimizes the extent of sub-60 mV/decade switching. In this work, we demonstrate 2D NC-FETs that combine the NC effect with 2D MoS2 channels to extend the steep switching behavior. Using the ferroelectric polymer, poly(vinylidene difluoride-trifluoroethylene) (P(VDF-TrFE)), these 2D NC-FETs are fabricated by modification of top-gated 2D FETs through the integrated addition of P(VDF-TrFE) into the gate stack. The impact of including an interfacial metal between the ferroelectric and dielectric is studied and shown to be critical. These 2D NC-FETs exhibit a decrease in subthreshold swing from 113 mV/decade down to 11.7 mV/decade at room temperature with sub-60 mV/decade switching occurring over more than 4 decades of current. The P(VDF-TrFE) proves to be an unstable option for a device technology, yet the superb switching behavior observed herein opens the way for further exploration of nanomaterials for extremely low-voltage NC-FETs.

High performance p-type NiOx thin-film transistor by Sn doping

Major obstacles towards power efficient complementary electronics employing oxide thin-film transistors (TFTs) lie in the lack of equivalent well performing p-channel devices. Here, we report a significant performance enhancement of solution-processed p-type nickel oxide (NiOx) TFTs by introducing Sn dopant. The Sn-doped NiOx (Sn-NiOx) TFTs annealed at 280 °C demonstrate substantially improved electrical performances with the increase in the on/off current ratio (Ion/Ioff) by ∼100 times, field-effect mobility (μlin) by ∼3 times, and the decrease in subthreshold swing by half, comparing with those of pristine NiOx TFTs. X-ray photoelectron spectroscopy and X-ray diffraction results confirm that Sn atoms tend to substitute Ni sites and induce more amorphous phase. A decrease in density of states in the gap of NiOx by Sn doping and the shift of Fermi level (EF) into the midgap lead to the improvements of TFT performances. As a result, Sn-NiOx can be a promising material for the next-generation, oxide-based electronics.

Universal analytic model for tunnel FET circuit simulation

A simple analytic model based on the Kane–Sze formula is used to describe the current–voltage characteristics of tunnel field-effect transistors (TFETs). This model captures the unique features of the TFET including the decrease in subthreshold swing with drain current and the superlinear onset of the output characteristic. The model also captures the ambipolar current characteristic at negative gate–source bias and the negative differential resistance for negative drain–source biases. A simple empirical capacitance model is also included to enable circuit simulation. The model has fairly general validity and is not specific to a particular TFET geometry. Good agreement is shown with published atomistic simulations of an InAs double-gate TFET with gate perpendicular to the tunnel junction and with numerical simulations of a broken-gap AlGaSb/InAs TFET with gate in parallel with the tunnel junction.

Performance and physical mechanisms in SIMOX MOS transistors operated at very low temperature

The performance and the physical properties of SIMOX (separation by implantation of oxygen) MOS transistors are studied from room to liquid helium temperatures with particular emphasis on the behavior of carrier mobility, threshold voltage, subthreshold swing, leakage current, and kink effect. Various SIMOX substrates, such as partially depleted films annealed at low or high temperature and ultrathin films (100 nm), are analyzed and compared. Enhancement- and depletion-mode devices with different doping levels, channel lengths, and geometries are considered. The front and back channels are activated independently in order to assess the electrical quality of both interfaces. Comparison with bulk Si transistors reveals a number of interesting features of SIMOX devices, which are explained using comprehensive models. The advantages of low-temperature operation of SIMOX transistors are related to the decrease in subthreshold swing and leakage, increase in mobility, and reasonable shift of the threshold voltage. The performance of ultra-thin-film devices is excellent over the whole range or temperatures, whereas partially depleted transistors exhibit optimum performance at 77 K.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>