Decoupled Double Synchronous Reference Frame Phase-locked Loop Research Articles

An enhanced implementation of SRF and DDSRF-PLL for three-phase converters in weak grid

Abstract Renewable energy generation systems connected to utility grid require perfect synchronization to grid which is one of the most important issues that needs to be taken into consideration. This paper proposed a hardware-accelerated implementation for the decoupled double synchronous reference frame phase-locked loop (DDSFR-PLL) for grid synchronization in grid-connected converters in weak grid that suffers from phase voltage-unbalance, variable phase and frequency conditions. Since the transformations and filtering of this method is computationally intensive and needs to be executed as fast as possible by the microcontroller unit (MCU) and Due to the presence of other current and voltage regulation loops in the same interrupt service routine (ISR) with high frequency rate, a hardware-based acceleration using the STM32G4x4 MCU built-in filter, filter math accelerator (FMAC) and coordinate rotation digital computer (CORDIC) is used to speed the execution time. This study addresses the description, derivation and implementation of the both DQ-PLL and DDSRF-PLL algorithms. The performance of both pure-software and accelerated implementation is demonstrated, compared and run on a three-level active neutral point clamped (ANPC) converter board. In proposed method, CPU load dropped from 80.5% by using the conventional software implementation to 23.6% (70% load reduction).This reduction in CPU load enables the addition of more features and more advanced current and voltage control algorithms.

Three-phase phase-locked loop algorithm and application to a static synchronous compensator

This work presents a phase-locked loop (PLL) algorithm for the detection of positive-sequence and negative-sequence grid voltages in three-phase systems. Since it employs an adaptive filter (AF), it is possible to track the fundamental component of the grid voltages accurately even in the presence of harmonics, subharmonics, and interharmonics. This aspect is of major concern for practical applications, especially because some popular algorithms present limited performance in such scenarios, e.g., the decoupled double synchronous reference frame PLL (DDSRF-PLL) and double second-order generalized integrator frequency-locked loop (DSOGI-FLL). A thorough comparison among the proposed method and other similar structures is presented in terms of steady-state and dynamic behaviors to show that the introduced PLL presents high immunity to power quality disturbances. Unfortunately, a possible drawback lies in the slow dynamic response due to the AF. In order to verify the applicability of the proposed approach, it is also incorporated to the control structure of a grid-connected power converter operating as a static synchronous compensator (STATCOM). This converter aims at regulating the ac voltage at the point of common coupling (PCC) and power factor correction. A detailed mathematical analysis is presented and experimental results are also discussed to validate the theoretical assumptions.

An Improved Harmonic Suppression Control Strategy for the Hybrid Microgrid Bidirectional AC/DC Converter

The nonlinear load in AC/DC hybrid microgrid seriously affects the power transmission quality of bidirectional AC/DC interlinking converter (BIC). In this article, an improved Fryze-Buchholz-Depenbrock (FBD) harmonic current detection method combined with droop control is designed to suppress harmonic current control strategy. The decoupled double synchronous reference frame phase locked loop (DDSRF-PLL) with self decoupled network is used to eliminate the negative sequence fundamental frequency component, and the accurate phase detection can also be realized when affected by nonlinear load. The least mean square (LMS) algorithm adaptive filter can enhance the dynamic response ability when the load current suddenly changes. To solve the problem that the cut-off frequency of low pass filter (LPF) can not take into account the detection accuracy and response speed of FBD harmonic current detection method. Finally, Matlab/Simulink is used for simulation verification. The simulation results show that the improved control strategy not only realizes the bidirectional flow of power and maintains the DC bus voltage stability, but also reduces the total harmonic distortion (THD) at point of common coupling (PCC) by 0.45% compared with the traditional FBD control strategy. And the effectiveness and feasibility of the design method are proved.

An Implementation of Improved PLL for Control of Grid-Connected Converters Under Grid Perturbations

In this article, a new method is proposed for calculating electric angle using a phase-locked loop (PLL) to perform these calculations correctly under disturbance conditions of the grid voltage. This work is based on using the decoupled double synchronous reference frame PLL (DDSRF-PLL), and this kind of PLL has been expanded to solve its problems in the presence of harmonics and high disturbance in the input voltage. In the DDSRF-PLL, only components with a frequency of double the fundamental frequency will be deleted, but in the expanded PLL all the harmonics will be eliminated. The effect of this method was tested using both simulation and practical experimentation. The simulation of this method was performed in MATLAB software. It has been shown that this method is robust, precise and fast for calculating the electric angle under grid voltage perturbations. Subsequently, the developed PLL was implemented in a FPGA-based experimental setup and its function was studied.

역상분 전류 주입을 적용한 3상 인버터 기반 BESS의 단독 운전 검출 방법

This paper proposes an active islanding detection method for the BESS (Battery Energy Storage System) with 3-phase inverter which is connected to the AC grid. The proposed method adopts the DDSRF (Decoupled Double Synchronous Reference Frame) PLL (Phase Locked-Loop) so that the independent control of positive-sequence and negative-sequence current is successfully carried out using the detected phase angle information. The islanding state can be detected by sensing the variation of negative-sequence voltage at the PCC (Point of Common Connection) due to the injection of 2-3% negative-sequence current from the BESS. The proposed method provides a secure and rapid detection under the variation of negative-sequence voltage due to the sag and swell. The feasibility of proposed method was verified by computer simulations with PSCAD/EMTDC and experimental analyses with 5kW hardware prototype for the benchmark circuit of islanding detection suggested by IEEE 1547 and UL1741. The proposed method would be applicable for the secure detection of islanding state in the grid-tied Microgrid.

Impact of strength of fault current path on the operation of decoupled double synchronous reference frame – phase locked loop

This paper studies the performance of decoupled double synchronous reference frame - phase locked loop (DDSRF-PLL) synchronizing method during grid fault. The study is carried out using Matlab/Simulink. The contribution of the paper is to reveal that if the DDSRF-PLL proposed in many papers is used, the control system of network side converter (NSC) may become unstable during a symmetrical grid fault. The instability problem appears only when certain tuning parameters of DDSRF-PLL are used and the fault current path is weak. Thus, the problem may not be easily detected. This paper emphasizes that it is mandatory to use PI-controller with integrator anti- windup in the loop filter of DDSRF-PLL. In addition, the impact of angular frequency limitation range on the fault ride through performance is evaluated with comparative simulations.

Decoupled Double Synchronous Reference Frame PLL for Power Converters Control

This paper deals with a crucial aspect in the control of grid-connected power converters, i.e., the detection of the fundamental-frequency positive-sequence component of the utility voltage under unbalanced and distorted conditions. Specifically, it proposes a positive-sequence detector based on a new decoupled double synchronous reference frame phase-locked loop (DDSRF-PLL), which completely eliminates the detection errors of conventional synchronous reference frame PLL's (SRF-PLL). This is achieved by transforming both positive- and negative-sequence components of the utility voltage into the double SRF, from which a decoupling network is developed in order to cleanly extract and separate the positive- and negative-sequence components. The resultant DDSRF-PLL conducts then to a fast, precise, and robust positive-sequence voltage detection even under unbalanced and distorted grid conditions. The paper presents a detailed description and derivation of the proposed detection method, together with an extensive evaluation using simulation and experimental results from a digital signal processor-based laboratory prototype in order to verify and validate the excellent performance achieved by the DDSRF-PLL