Decompression Circuit Research Articles

A Hardware Implementation of Real Time Lossless Data Compression and Decompression Circuits

This paper presents a hardware implementation of real time data compression and decompression circuits based on the LZW algorithm. LZW is a dictionary based data compression, which has the advantage of fast speed, high compression, and small resource occupation. In compression circuit, the design creatively utilizes two dictionaries alternately to improve efficiency and compressing rate. In decompression circuit, an integrated State machine control module is adopted to save hardware resource. Through hardware description and language programming, the circuits finally reach function simulation and timing simulation. The width of data sample is 12bits, and the dictionary storage capacity is 1K. The simulation results show the compression and decompression circuits have complete function. Compared to software method, hardware implementation can save more storage and compressing time. It has a high practical value in the future.

ABSTRACT 439

Background and aims: to prove scientifically and introduce into clinical practice the method of exogenous surfactant replacement therapy at the time of “mobilization of alveoli” in neonates and infants with ALI / ARDS, operated on different CHD. Methods: Central hemodynamics, X-rays of the lungs, gas exchange, ventilator parameters and mechanical properties of the lungs have been analyzed in 6 hours since the syndrome manifestation and also after the recruitment maneuver and the administration of exogenous surfactant. We also analyzed the duration of mechanical ventilation and the ICU period in 25 children aged from 24 days to 16 months (5,7 ± 4,8 m.). Surfactant was administered after the procedure of lung recruitment without the decompression circuit. Results: There was an increase from 135 paO2/FiO2 ± 38,0 to 329,6 ± 33,2 (p <0.05) in patients after the recruitment maneuver and the subsequent introduction of exogenous surfactant at the peak of the disclosure of alveoli. This allowed to reduce the intensity of ventilation modes downward Pmean with 12,4 ± 1,65 to 10,77 ± 2,66 mbar and with FiO2 0,76 ± 0,2 to 0,45 ± 0,06. One (4.16%) of the 25 patients died from the critical respiratory failure. Conclusions: Securing of ALI /ARDS targeted delivery of exogenous surfactant to the damaged alveoli at the first 24 hours since the beginning of manifestation with the concept of “the open lung”, leads to significant improvement and stabilization of the mechanical properties of the lungs and gas exchange, which enables to reduce aggressive ventilator settings.

Minimizing the runtime partial reconfiguration overheads in reconfigurable systems

Configuration overhead is a major performance bottleneck of the partial reconfiguration process. In this paper, we propose a combination of two techniques to minimize the partial reconfiguration performance overhead. First, we design and implement fully streaming DMA engines to achieve a near perfect configuration throughput. Second, we exploit the configuration data redundancy through Run-Length Encoding to compress the configuration bitstreams, and we implement an intelligent ICAP (Internal Configuration Access Port) controller to perform decompression at runtime. The results show that our design achieve an effective configuration data transfer throughput that well surpasses the upper bound of data transfer throughput, 400 Mbytes/s. Specifically, our fully stream DMA engines reduce the configuration time from the range of seconds to the range of milliseconds, a more than 1000-fold improvement. In addition, our simple compression scheme achieves significant reduction of bitstream size and results in a decompression circuit with negligible hardware overhead.

A low-power-consumption architecture for embedded processors

This paper discusses a low-power-consumption architecture for the processor based on object code compression, especially the application of the idea to embedded processors. In the proposed method, duplicated instructions are unified to compress the program. An instruction decompression circuit is added, which reorganizes the object code from the pseudocode generated by the compression. The instruction decompression circuit and the processor are integrated into a single chip, which helps to reduce the bandwidth needed in the interface to the external memory. Then, the power consumption is reduced greatly. As a result of experiments, when the proposed method is applied to the ARM610 32-bit RISC processor, the code is compressed by 62.5%. The power consumption in the instruction memory is reduced by 42.3%. The area of the instruction decompression circuit that is additionally implemented is 0.983 mm2. © 1998 Scripta Technica, Electron Comm Jpn Pt 3, 81(10): 83–90, 1998

Design of built-in test generator circuits using width compression

We present a method for designing test generator circuits (TCCs) that incorporate a precomputed test set T/sub D/ in the patterns they produce. Our method uses width compression based on the property of d-compatibles as well as compatibles and inverse compatibles and does not require access to a gate-level model of the circuit under test. The TGC consists of a counter, which generates a set of encoded test patterns T/sub E/ and a decompression circuit, which consists of simple binary decoders that generate a final sequence containing T/sub D/. We show that partially specified test sets, i.e., those that contain a large number of don't-cares, lead to more efficient TGCs. These TGCs are applicable to embedded core circuits whose detailed designs are not available. We demonstrate the effectiveness of our approach by presenting experimental results on width compression for the ISCAS'85 benchmark circuits and the full-scan versions of the ISCAS'89 benchmark circuits.