Decision Feedback Equalizer Architecture Research Articles

A 2.5–32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE

This brief presents a 2.5 – 32 Gb/s Gen 5-PCIe receiver with a multi-rate clock and data recovery (CDR) engine and a hybrid decision feedback equalizer (DFE). The receiver for the PCIe requires wide-range operation and compensation for high insertion loss. The proposed multi-rate CDR engine enables the receiver to operate with multi-rate clocking schemes according to the data rates, which does not need any additional high-speed analog circuits normally used for wide-range operation. In addition, the hybrid DFE architecture not only meets the DFE feedback timing constraint and but also reduces the equalization power. By using clock gating, the receiver can save power when operating at lower generations such as Gen 1, 2, 3, and 4. The prototype chip is fabricated in a 40-nm CMOS technology and occupies an active area of 0.14 mm². The receiver achieves BER less than 10^−12 with various PCIe channels, satisfying PCIe jitter tolerance masks. It consumes 62.7 mW at 32 Gb/s, compensating for 27.5-dB inserting loss, and the figure of merit (energy efficiency per channel loss at Nyquist frequency) of 0.07 pJ/b/dB is achieved.

DFE Error Propagation and FEC Interleaving for 400GbE PAM4 Electrical Lane

This paper analyzes the effect of error propagation of decision feedback equalizer (DFE) for PAM4 based 400Gb/s Ethernet. First, an analytic model for the error propagation is proposed to estimate the probability of different burst error length due to error propagation for PAM4 link system with multi-tap TX FFE (Feed Forward Equalizer) + RX DFE architecture. After calculating the symbol error rate (SER) and bit error rate (BER) based on the probability model, the theoretical analysis about the impact of different equalizer configurations on BER is compared with the simulation results, and then BER performance with FEC (Forward Error Correction) is analyzed to evaluate the effect of DFE error propagation on PAM4 link. Finally, two FEC interleaving schemes, symbol and bit interleaving, are employed in order to reduce BER further and then the theoretical analysis and the simulation result of their performance improvement are also evaluated. Simulation results show that at most 0.52dB interleaving gain can be achieved compared with non-interleaving scheme just at a little cost in storing memory and latency. And between the two interleaving methods, symbol interleaving performs better compared with the other one from the view of tradeoff between the interleaving gain and the cost and can be applied for 400Gb/s Ethernet.

A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS

The emergence of four-level pulse amplitude modulation (PAM-4) standards to increase data rates motivates the use of receiver front ends that utilize high-speed analog-to-digital converters (ADCs) followed by digital signal processing (DSP) to provide robust digital equalization. This paper presents an ADC-based PAM-4 receiver employing a 32-way time-interleaved, 2-bit/stage, 6-bit successive approximation register (SAR) ADC with a single capacitive reference digital-to-analog converter (DAC) and a digital equalizer consisting of a 12-tap feed-forward equalizer (FFE) and a two-tap decision-feedback equalizer (DFE). A new digital DFE architecture that reduces the complexity of a PAM-4 DFE to that of a binary non-return-to-zero (NRZ) DFE, while simultaneously nearly doubling the maximum achievable data rate, is presented. Partial analog equalization is provided in the receiver front end in the form of a programmable two-stage continuous-time linear equalizer (CTLE) and a three-tap FFE that is embedded in the ADC using a non-binary FFE DAC to improve the FFE coefficient coverage space. This partial analog equalization allows placement of the digital baud-rate clock and data recovery (CDR) system's Mueller-Muller phase detector directly at the ADC output to avoid excessive loop delay. Fabricated in GP 65-nm CMOS, the receiver achieves 32-Gb/s operation at a bit error rate (BER) <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> with a 30-dB loss channel and 52-Gb/s operation at a BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> with a 31-dB loss channel without utilizing any transmit equalization. The complete ADC-based receiver achieves a 52-Gb/s power efficiency of 8.06 pJ/bit, including all the front end, ADC, and DSP power.

High speed and low area decision feed-back equalizer with novel memory less distributed arithmetic filter

In this paper an efficient implementation of decision feed back equalizer (DFE) is carried out using novel memory less distributed arithmetic (NMLDA) filter. In wireless transmission systems, DFEs are used to mitigate the inter-symbol interference (ISI). The ISI is occurred due to multi-path propagation of the transmitted signal. High data rate systems demand higher order filters in DFE architectures which increase complexity in hardware design. In our proposed NMLDA design, we have used multiplexers and enhanced compressor adders in place of memory unit and conventional adders. The proposed design occupies lower area and gives higher throughput, when compared to MAC based filter and all other memory based DA filter architectures. By using proposed NMLDA based DFE, the ISI errors in transmission signal, will be minimized and the performance of the transmission system will be enhanced. We have synthesized the NMLDA of 32-tap, 16-tap, 8-tap and 4-tap filters and implemented them on FPGA device. The proposed design has nearly 70% less number of logical elements than OBC DA and 50% less than MDA and offers better throughput than the existing designs when implemented on Altera Cyclone III EP3C55F484C6.

A 2.44-pJ/b 1.62–10-Gb/s Receiver for Next Generation Video Interface Equalizing 23-dB Loss With Adaptive 2-Tap Data DFE and 1-Tap Edge DFE

This brief presents a 1.62-to-10-Gb/s receiver for next generation video interconnected with an adaptive decision-feedback equalizer (DFE). The adaptive DFE facilitates the best bit error rate (BER) performance for various losses of video cables. A differential-pair stage is added to the DFE for extending an effective DFE range, presetting a minimum data level, and calibrating a mismatch offset. Circuit techniques are proposed to relax timing constraints for the direct-feedback DFE architecture. A referenceless frequency acquisition is performed during a dedicated clock recovery phase. The measured BER at 10 Gb/s is lower than 10−12 with a 23-dB loss cable. The RMS jitter and the peak-to-peak jitter of a recovered clock are measured as 2.38 ps and 17.5 ps, respectively. The prototype chip is implemented in 65-nm CMOS technology and occupies an active area of 0.254 mm2. This receiver consumes 24.4 mW at 10 Gb/s, corresponding to the energy efficiency of 2.44 pJ/b, which is the lowest compared to other recently published video interface receivers.

An Energy Efficient VLSI Architecture of Decision Feedback Equalizer for 5G Communication System

Decision feedback equalizer (DFE) is widely used to mitigate the inter-symbol interference. In gigabit applications, the complexity of time domain DFE grows exponentially with feedback filter (FBF) order. In this paper, we have derived low complexity, high throughput architectural designs for time domain DFEs, which meets the requirements of 5G communication systems. These designs are based on the concept of pre-speedup the conventional DFE architecture. The number of FBF coefficient combinations to be stored in the lookup table (LUT) and the hardware complexity of proposed designs are reduced by almost $(M/2)^{-1}$ with $M$ being the number of levels in quadrature-amplitude modulation (QAM). The proposed design achieves the throughput nearly 2.15 Gb/s for 16-QAM. A new strategy for updating the FBF coefficients is proposed to improve the convergence rate and steady state error performances without extra hardware overhead. This is based on storing the past decisions in separate LUT, whose contents are updated time to time using parallel error multiplexor. In addition, the bit-error-rate performance of proposed designs is evaluated for different speedup factors in AWGN and Rayleigh fading channels. From the implementation results, it is found that the area, power, and logic utilization of the proposed designs are significantly reduced. For example, an $8^{\mathrm{ th}}$ -order FBF of proposed adaptive DFE for 16-QAM occupies times 1.19 less area, 1.04 times less area-time product, with nearly consumes 2.48 times less power and; utilizes 1.93 times less slice LUTs and 2.04 times less flip-flops as compared with the best existing scheme.

An Efficient Distributed Arithmetic-Based Realization of the Decision Feedback Equalizer

A distributed arithmetic (DA)-based decision feedback equalizer architecture for IEEE 802.11b PHY scenarios is presented. As the transmission data rate increases, the hardware complexity of the decision feedback equalizer increases due to requirement for large number of taps in feed forward and feedback filters. DA, an efficient technique that uses memories for the computation of inner product of two vectors, has been used since DA-based realization of filters can lead to great computational savings. For higher-order filters, the memory-size requirement in DA would be high, and so ROM decomposition has been employed. The speed is further increased by employing digit-serial input operation. Two architectures have been presented, namely the direct-memory architecture and reduced-memory architecture where the later is derived using the former. A third architecture has also been presented where the offset-binary coding scheme is employed along with the ROM decomposition and digit-serial variants of DA. Synthesis results on Altera Cyclone III EP3C55F484C6 FPGA show that the proposed DA-based implementations are free of hardware multipliers and use less number of hardware resources compared to the multiply-and-accumulate-based implementation.

A 12.5 Gb/s 6.6 mW receiver with analog equalizer and 1-tap DFE

This paper presents a compact, low power 12.5Gb/s backplane receiver in a 90nm CMOS technology. The receiver incorporates an analog equalizer, which is designed using active inductor circuit, and a 1-tap speculative decision-feedback- equalizer (DFE). The proposed active inductor circuit provides wider tuning range and higher inductive impedance with respect to the previous reported topologies, using negative impedance implemented by a cross coupled transistor pair, at the output nodes of active inductor circuit. The DFE is designed in half rate architecture utilizing an improved front end sample and hold to speculate the first feedback tap while consuming low power and imposing small capacitive load on the analog equalizer block. The input capacitance of the DFE block is alleviated more by changing the place of multiplexer in the DFE architecture. Furthermore power consumption reduction in DFE architecture is achieved by using a novel high speed slicer with rail-to-rail swing in the output to avoid implementing latches and MUXs in the next stages in CML topology. The receiver consumes 6.6mW from a 1.2V supply while delivering 12.5Gb/s data over 5″ NELCO 4000-6 channel in the presence of two aggressor far-end-crosstalk (FEXT) signals.

Decision Feedback Equalizer Architectures With Multiple Continuous-Time Infinite Impulse Response Filters

Decision feedback equalizer (DFE) architectures with varying numbers of discrete-time taps and continuous-time infinite impulse response (IIR) filters are compared for use in typical wireline channels. In each case, the DFE coefficients are optimized to minimize a cost function that equally weights both jitter and vertical eye opening. Even when some reflections are present (e.g., backplane channels) continuous-time IIR taps can be effective if their filter coefficients are properly optimized. Using a DFE architecture with only two IIR filters provides adequate results for both a 26-dB loss coax cable and a 16 FR-4 backplane channel at 10 Gb/s while keeping the DFE complexity low. Furthermore, the implementation and experimental results of a DFE with multiple (three) IIR filters is reported. Fabricated in a 0.13 μm CMOS process, the DFE consumes 17.3 mW from a 1.2 V supply. A bit error rate (BER) of 10-12 was achieved at a data rate of 3.7 Gb/s.

High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems

This brief addresses the design of a decision feedback equalizer (DFE) for gigabit throughput rate. It is well known that the feedback loop in a DFE limits an upper bound of the achievable speed. For a L-tap feedbackward filter (FBF) and M-pulse amplitude modulation, Parhi (1991) and Kasturia and Winters (1991) reformulated the FBF as a (M)L-to-1 multiplexer. Due to the reformulation, the overhead of extra adders and extra multiplexers are as large as (M)L. The required hardware overhead should be more severe when the DFE is implemented in parallel. In this brief, we propose two new approaches to implement the DFE when gigabit throughput rate is desired. The first approach is partial pre-computation scheme, which can trade-off between hardware complexity and computational speed. The second approach is two-stage pre-computation scheme, which can be applied to higher speed applications. In the later case, we can reduce the hardware overhead to about 2(M)(-L/2) times of [1], [2], and the iteration bound is (log2W+2)/(L/2+1)+(log2M) multiplexer-delays, where W is the wordlength of weight coefficient of a FBF. We demonstrate the proposed architectures by apply it to the 10 Gbase-LX4 optical communication systems

Pipelined DFE architectures using delayed coefficient adaptation

In this paper the delayed least-mean-square (DLMS) algorithm is proposed for training a transversal filter-based decision feedback equalizer (DFE). Delays in the filter coefficient update process are used to pipeline the DFE, thereby increasing the throughput rate, for a given speed of hardware. The filter structures selected for the feedforward and feedback section of the DFE facilitate the use of a shared error signal, thereby reducing communication costs. The new resulting structure is highly modular and is very suitable for very large scale integration (VLSI) implementation. A pipelined form for the normalized least-mean-square algorithm (NMLS) is also obtained which removes the dependency of the convergence speed on the input signal power. The convergence and residual mean-square error characteristics of the different pipelined filters are compared.