Decimation In Time Fast Fourier Transform Research Articles

Comparison Study of DIT and DIF Radix-2 FFT Algorithm

The fast fourier transform (FFT) is an important technique for image compression, digital signal processing and communication especially for application in multiple input multiple output OFDM system. The fast fourier transform are good algorithm and computed discrete fourier transform (DFT). In this paper, the comparison study of various FFT algorithm and compare all them. FFT algorithm is divided into two part i.e. decimation in time (DIT) and decimation in frequency (DIF). In DIT algorithm firstly computed multiplier then adder but in DIF firstly computed adder then multiplier. In this paper we study of different types of multiplier i.e. array multiplier; sing multiplier (Baugh Wooley) and complex multiplier. In proposed complex multiplier is consuming three multipliers. In further work in my dissertation in design to 8point, 16-point, 32-point, 64-point and 128-point radix FFT algorithm in different multiplier.

A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO

Nowadays, many applications require simultaneous computation of multiple independent fast Fourier transform (FFT) operations with their outputs in natural order. Therefore, this brief presents a novel pipelined FFT processor for the FFT computation of two independent data streams. The proposed architecture is based on the multipath delay commutator FFT architecture. It has an $N/2$ -point decimation in time FFT and an $N/2$ -point decimation in frequency FFT to process the odd and even samples of two data streams separately. The main feature of the architecture is that the bit reversal operation is performed by the architecture itself, so the outputs are generated in normal order without any dedicated bit reversal circuit. The bit reversal operation is performed by the shift registers in the FFT architecture by interleaving the data. Therefore, the proposed architecture requires a lower number of registers and has high throughput.

Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data

The decimation-in-time (DIT) fast Fourier transform (FFT) very often has advantage over the decimation-in-frequency (DIF) FFT for most real-valued applications, like speech/image/video processing, biomedical signal processing, and time-series analysis, etc., since it does not require any output reordering. Besides, the DIT FFT butterfly involves less computation time than its DIF counterpart. In this paper, we present an efficient architecture for the radix-2 DIT real-valued FFT (RFFT). We present here the necessary mathematical formulation for removing the redundancies in the radix-2 DIT RFFT, and present a formulation to regularize its flow graph to facilitate folded computation with a simple control unit. We propose here a register-based storage design which involves significantly less area at the cost of a little higher latency compared with the conventional RAM-based storage. The address generation for folded in-place DIT RFFT computation with register-based storage is challenging since both read and write operations are performed in the same clock cycle at different locations. Therefore, we present here a simple formulation of address generation for the proposed radix-2 DIT RFFT structure. The proposed structure involves $\sim$ 61% less area and $\sim$ 40% less power consumption than those of , on average, for FFT sizes 16, 32, 64, and 128. It involves $\sim$ 70% less area-delay product and $\sim$ 57% less energy per sample than those of the other, on average, for the same FFT sizes.

Design of power efficient butterflies from Radix-2 DIT FFT using adder compressors with a new XOR gate topology

This paper addresses the design of power efficient dedicated structures of Radix-2 Decimation in Time (DIT) pipelined butterflies, aiming the implementation of low power Fast Fourier Transform (FFT), using adder compressors, with a new XOR gate topology. In the FFT computation, the butterflies play a central role, since they allow calculation of complex terms. In this calculation, involving multiplications of input data with appropriate coefficients, the optimization of the butterfly can contribute for the reduction of power consumption of FFT architectures. In this paper, different and dedicated structures for the 16 bit-width pipelined Radix-2 DIT butterfly, running at 100 MHz, are implemented, where the main goal is to minimize both the number of real multipliers and the critical path of the structures. This is done by changing the structure of the complex multipliers and applying them into the butterflies. For logic synthesis of the implemented butterflies it was used Cadence Encounter RTL Compiler tool with XFAB MOSLP 0.18 μm library. Area and power consumption results are presented for the synthesized butterflies. Regarding power consumption, switching activity analysis is performed using 10,000 inputs vectors at inputs of the butterflies. The main results show that when combining the use of pipeline approach and the use of efficient adder compressors, with a new XOR gate topology, the power consumption of the butterflies is significantly reduced.

On the Fixed-Point Accuracy Analysis of FFT Algorithms

In this paper, we investigate the effect of fixed-point arithmetics with limited precision for different fast Fourier transform (FFT) algorithms. A matrix representation of error propagation model is proposed to analyze the rounding effect. An analytic expression of overall quantization loss due to the arithmetic quantization errors is derived to compare the performance with decimation-in-time (DIT) and decimation-in-frequency (DIF) configurations. From the simulation results, the radix-2 DIT FFT algorithm has better accuracy in term of signal-to-quantization-noise ratio (SQNR). Based on the results, a simple criterion of wordlength optimization is proposed to yield comparable accuracy with fewer bit budget.

Pruning the decimation in-time FFT algorithm

Significant time-saving can be achieved by a simple modification to the radix-2 decimation in-time fast Fourier transform (FFT) algorithm when the data sequence to be transformed contains a large number of zero-valued samples. The time-saving is accomplished by replacing M - L stages of the FFT computation with a simple recopying procedure where 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sup> is the total number of points to be transformed of which only 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sup> are nonzero.