Debugging Of Parallel Programs Research Articles

Synchronous Deterministic Parallel Programming for Multi-Cores with ForeC

Embedded real-time systems are tightly integrated with their physical environment. Their correctness depends both on the outputs and timeliness of their computations. The increasing use of multi-core processors in such systems is pushing embedded programmers to be parallel programming experts. However, parallel programming is challenging because of the skills, experiences, and knowledge needed to avoid common parallel programming traps and pitfalls. This article proposes the ForeC synchronous multi-threaded programming language for the deterministic, parallel, and reactive programming of embedded multi-cores. The synchronous semantics of ForeC is designed to greatly simplify the understanding and debugging of parallel programs. ForeC ensures that ForeC programs can be compiled efficiently for parallel execution and be amenable to static timing analysis. ForeC’s main innovation is its shared variable semantics that provides thread isolation and deterministic thread communication. All ForeC programs are correct by construction and deadlock free because no non-deterministic constructs are needed. We have benchmarked our ForeC compiler with several medium-sized programs (e.g., a 2.274-line ForeC program with up to 26 threads and distributed on up to 10 cores, which was based on a 2.155-line non-multi-threaded C program). These benchmark programs show that ForeC can achieve better parallel performance than Esterel, a widely used imperative synchronous language for concurrent safety-critical systems, and is competitive in performance to OpenMP, a popular desktop solution for parallel programming (which implements classical multi-threading, hence is intrinsically non-deterministic). We also demonstrate that the worst-case execution time of ForeC programs can be estimated to a high degree of precision.

Решение прикладных задач с использованием DVM-системы

DVM-system was designed to create parallel programs of scientific-technical computations in C-DVMH and Fortran-DVMH languages. These languages use the same model of parallel programming (DVMH-model) and are the extensions of standard C and Fortran languages by parallelism specifications, implemented as compiler directives. DVMH-model allows creating efficient parallel programs for heterogeneous computational clusters, the nodes of which use as computing devices not only universal multi-core processors but also can use attached accelerators (GPUs or Intel Xeon Phi coprocessors). This article describes the experience of parallelizing various application programs using DVM-system. The method of incremental or partial parallelization, the system's capabilities for working with unstructured grids, new tools for mapping MPI-programs to multi-core processors and accelerators are considered. The efficiency of parallel DVMH-programs on heterogeneous computing clusters K-10, K-100, Lomonosov and MVS-10P is investigated. The main advantages of DVM-approach for the development of parallel programs are described. The main features of DVM-system tools for performance analysis and functional debugging of parallel programs are presented. The directions for further development of DVM-system are determined.

멀티 스레딩 기반 병렬 프로그램의 효과적인 디버깅을 위한 추상적 시각화

멀티 스레딩 기반 병렬 프로그램의 효과적인 디버깅을 위한 추상적 시각화

Средства программирования реконфигурируемых вычислительных систем на основе ПЛИС VIRTEX-7 с использованием софт-архитектур

The paper covers the existing design tools of digital devices in FPGAs, programming languages of reconfigurable computer systems and ability of their use for programming of multichip reconfigurable computer systems. Besides it deals with the high-level programming language COLAMO and the multichip solution development suite for reconfigurable computer systems that are developed in SRI MCS SFU. A particular attention is paid to a new programming approach, which consists in development and use of adjustable special-purpose soft-architectures which help to reduce the number of translations of FPGA bitstream files during debugging of parallel programs on reconfigurable computer systems. Owing to special-purpose soft-architectures it is possible to change communication links between devices and create required computing structures for user applications only by means of program adjustment and without re-loading FPGA bitstream files of the computational field. It considerably reduces the debugging time of parallel applications.

Interactive debugging of parallel programs: Distributed scheme of interacting components

A general scheme of the organization of a distributed debugger of parallel programs. The experience of using this scheme for developing a debugger of programs in NORMA and for developing a system for examining MPI programs is discussed.

HIGH-LEVEL PARALLEL SOFTWARE DEVELOPMENT WITH PYTHON AND BSP

One of the main obstacles to a more widespread use of parallel computing in computational science is the difficulty of implementing, testing, and maintaining parallel programs. The combination of a simple parallel computation model, BSP, and a high-level programming language, Python, simplifies these tasks significantly. It allows the rapid development facilities of Python to be applied to parallel programs, providing interactive development as well as interactive debugging of parallel programs.

AdEPar Integrated Simulation and Implementation Environment for DSP

The AdEPar (Advanced Educational Parallel) integrated simulation and implementation environment for Digital Signal Processing (DSP) has been designed and implemented to serve as a test-bed for various scheduling, simulation, and code generation problems as well as a real-time implementation tool for DSP algorithms that could be mapped onto the proposed parallel pipelined architecture. The integrated environment fully exploits all types of concurrency present in DSP algor ithms and addresses practical issues such as processor and memory constraints, architec tural features of DSP processors in the target architectures, debugging of parallel programs, and development of high-level programming environments. The AdEPar software DSP environment is based on object-oriented programming techniques. Because DSP computation objects and graphics objects of AdEPar are separated from each other carefully, the software system portability is guaranteed. This programming approach saves time and effort to develop an environ ment based on a graphical user interface.

Event-based debugging system for a parallel object-oriented language A-NETL

Debugging of parallel programs is generally very difficult to undertake since the execution of programs is nondeterministic and nonrepeatable. Considering a parallel object-oriented language, this paper proposes a method of preserving the repeatability of the order of execution in a replay by defining a logic time in terms of events in the message communication system and state transitions, and by representing the execution history of events. A debugger that mainly uses a two-dimensional (2-D) representation and replay debugging has been designed based on the proposed method. A high-performance system has been constructed based on the design. The debugger functions are distributed between a host workstation and multicomputer nodes, and between local OS on nodes and in firmware so that a high-performance system has been realized. The experiments show that the method is successful for practical applications; the time and space overhead of event recording is 0.04 ms (mean value) and 35 B per event, respectively; the display of 16 objects for one logical time is 0.94 s; and the overhead for a breakpoint is 3.1 ms per point. © 1998 Scripta Technica, Syst Comp Jpn, 28(11): 53–63, 1997

ON-LINE DEBUGGING OF PARALLEL PROGRAMS

Nondeterminacy is a main obstacle of parallel debugging. Current debugging strategies either detect non-dcterminacy separately, or control the execution in a two-phase manner. Here we present a strategy called “state freezing”. Based on the strategy, one-phase (we call one-line) debugging of parallel programs is available. Basic algorithms and an example are given in the paper.

A Process Specification Formalism1

Traditional methods for programming sequential machines are inadequate for specifying parallel systems. Because debugging of parallel programs is hard, due to e.g. non-deterministic execution, verification of program correctness becomes an even more important issue. The Algebra of Communicating Processes (ACP) is a formal theory which emphasizes verification and can be applied to a large domain of problems ranging from electronic circuits to CAM architectures. The manual verification of specifications of small size has already been achieved, but this cannot easily be extended to the verification of larger industrially relevant systems. To deal with this problem we need computer tools to help with the specification, simulation, verification and implementation. The first requirement for building such a set of tools is a specification language. In this paper we introduce PSFd (Process Specification Formalism – draft) which can be used to formally express processes in ACP. In order to meet the modern requirements of software engineering, like reusability of software, PSFd supports the modular construction of specifications and parameterization of modules. To be able to deal with the notion of data, ASF (Algebraic Specification Formalism) is embedded in our formalism. As semantics for PSFd a combination of initial algebra semantics and operational semantics for concurrent processes is used. A comparison with programming languages and other formal description techniques for the specification of concurrent systems is included.

A mechanism for efficient debugging of parallel programs

This paper addresses the design and implementation of an integrated debugging system for parallel programs running on shared memory multi-processors (SMMP). We describe the use of flowback analysis to provide information on causal relationships between events in a program's execution without re-executing the program for debugging. We introduce a mechanism called incremental tracing that, by using semantic analyses of the debugged program, makes the flowback analysis practical with only a small amount of trace generated during execution. We extend flowback analysis to apply to parallel programs and describe a method to detect race conditions in the interactions of the co-operating processes.

A mechanism for efficient debugging of parallel programs

This paper addresses the design and implementation of an integrated debugging system for parallel programs running on shared memory multi-processors (SMMP). We describe the use of flowback analysis to provide information on causal relationships between events in a program's execution without re-executing the program for debugging. We introduce a mechanism called incremental tracing that, by using semantic analyses of the debugged program, makes the flowback analysis practical with only a small amount of trace generated during execution. We extend flowback analysis to apply to parallel programs and describe a method to detect race conditions in the interactions of the co-operating processes.

The program summary graph and flow-sensitive interprocedual data flow analysis

This paper discusses a method for interprocedural data flow analysis which is powerful enough to express flowsensitive problems but fast enough to apply to very large programs. While such information could be applied toward standard program optimizations, the research described here is directed toward software tools for parallel programming, in which it is crucial. Many of the recent “supercomputers” can be roughly characterized as shared memory multi-processors. These include top-of-the-line systems from Cray Research and IBM, as well as multi-processor computers developed and successfully marketed by many younger companies. Development of efficient, correct programs on these machines presents new challenges to the designers of compilers, debuggers, and programming environments. Powerful analysis mechanisms have been developed for understanding the structure of programs. One such mechanism, data dependence analysis, has been evolving for many years. The product of data dependence analysis is a dota dependence gmph, a directed multi-graph that describes the interactions of program components through shared memory. Such a graph has been shown useful for a variety of applications from vectorization and parallelization to compiler management of locality. Another application of the data dependence graph is as an aid to static debugging of parallel programs. PTOOL [4] is a software system developed at Rice University to help programmers understand parallel programs. It is within this context that we at Rice have learned of the importance of interprocedural data flow analysis. I will briefly describe the PTOOL system and explain the kind of interprocedural information valuable in such an environment. PTOOL is designed to help locate interactions between