Debugging Facilities Research Articles

MemPol: polling-based microsecond-scale per-core memory bandwidth regulation

In today’s multiprocessor systems-on-a-chip, the shared memory subsystem is a known source of temporal interference. The problem causes logically independent cores to affect each other’s performance, leading to pessimistic worst-case execution time analysis. Memory regulation via throttling is one of the most practical techniques to mitigate interference. Traditional regulation schemes rely on a combination of timer and performance counter interrupts to be delivered and processed on the same cores running real-time workload. Unfortunately, to prevent excessive overhead, regulation can only be enforced at a millisecond-scale granularity. In this work, we present a novel regulation mechanism from outside the cores that monitors performance counters for the application core’s activity in main memory at a microsecond scale. The approach is fully transparent to the applications on the cores, and can be implemented using widely available on-chip debug facilities. The presented mechanism also allows more complex composition of metrics to enact load-aware regulation. For instance, it allows redistributing unused bandwidth between cores while keeping the overall memory bandwidth of all cores below a given threshold. We implement our approach on a host of embedded platforms and conduct an in-depth evaluation on the Xilinx Zynq UltraScale+ ZCU102, NXP i.MX8M and NXP S32G2 platforms using the San Diego Vision Benchmark Suite.

Debugger for Declarative DSL for Telecommunication

Development of telecommunication product lines is still a very labor-intensive task, involving a great amount of human resources and producing a large number of development artifacts — code, models, tests, etc. Declarative domain-specific languages (DSLs) may reasonably simplify this process by increasing the level of abstraction. We use the term “declarative” implying that such a DSL does not enable the development of a closed software application, but rather supports creation, generation and maintenance of various kind of software assets — product database, events and event handlers, target code data structures, etc. At the same time, such a DSL may have some executable semantic, but it could be very specific and have many environment-wise requirements. Thus, execution and debugging of such DSL specifications is a meaningful task, which has no common solution due to the unique executable semantic. Consequently, it is not possible to use debug facilities of known DSL environments, such as xtext, MPS, etc. for such a case. In the current paper, we present a debugger for DevM — a declarative DSL intended for support device management in software development in the context of a router product line by a large telecommunication company. We clarify executable semantic for DevM, making it possible to execute DevM specifications in an isolated environment, i.e. in simulation mode, without generation of target code. We use a graphic model-based notation to depict every step of execution. Finally, we implement and integrate the debugger in the DevM IDE, using Debug Adapter Protocol and language server architecture combined with the Eclipse xText/EMF tool chain.

Visual exploration of visual parser execution

In this paper, we present ParVis, an interactive visual system for the animated visualization of logged parser trace executions. The system allows a parser implementer to create a visualizer for generated parsers by simply defining a JavaScript module that maps each logged parser instruction into a set of events driving the visual system interface. The result is a set of interacting graphical/text windows that allows users to explore logged parser executions and helps them to have a complete understanding of how the parser behaves during its execution on a given input. We used our system to visualize the behavior of textual as well as visual parsers and describe here two of these uses. Moreover, in order to validate the efficacy of our system, we ran a user experiment where students analyzed a CUP-generated parser both with ParVis, instantiated to LALR parsers, and the standard CUP debug facilities. The results show that students can indeed analyze parser behavior and find mistakes in parser specifications more easily and quickly using ParVis. In particular, in some parser design tasks, using ParVis participants achieved a higher success rate of 50% in 42% less time with respect to the baseline system.

Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption

Scan attacks exploit facilities offered by scan chains to retrieve embedded secret data, in particular, secret keys used by the device for data encryption/decryption in mission mode. This paper presents a scan attack countermeasure based on the encryption of the data written to or read from the scan chains. The secret-key management system already embedded in the device is used to provide appropriate keys for encryption of data flowing on the scan chains. The goal of the proposed solution is to counteract the scan-related security threats while preserving test and diagnosis efficiency provided by conventional design-for-testability techniques, as well as to allow debugging capabilities in mission mode. The proposed solution can deal with both stuck-at and transition-faults test schemes as well as single and multiple scan chain configurations using test data compression schemes. We will show that the proposed scheme provides expected test/diagnostic and debug facilities as classical scan design with marginal impacts on area, test time and design flows, while successfully preventing control and observation of data flowing in the scan chains by unauthorized users.

Model-driven toolset for embedded reconfigurable cores: Flexible prototyping and software-like debugging

Improvements in system cost, size, performance, power dissipation, and design turnaround time are the key benefits offered by System-on-Chip designs. However they come at the cost of an increased complexity and long development cycles. Integrating reconfigurable cores offers a way to increase their flexibility and lifespan. However the integration of embedded reconfigurable units poses a number of unique challenges in terms of design-space exploration and system exploitation. Over the last few years, model-driven engineering has become one of the most promising methodologies for tackling such challenging software problems.This paper presents Biniou, a model-driven toolset for embedded reconfigurable core modeling. Biniou is a major step ahead of the Madeo framework that was one of the rare non-commercial environments targeting reconfigurable design automation. In Biniou, the design space is broadened with (re-)configuration modeling aspects, and the exploitation tools are enhanced through the use of multi-level simulation and high-level debugging.These advancements are illustrated through a case-study focused on the design-space exploration of a coarse-grained reconfigurable architecture and through an examination of the integration of the debug-specific features into the framework. The main benefits of the presented toolset are: efficient domain-space exploration (validation), software design-kit generation (usability), software-like debug facilities (verification).

The embedded black-box recorder [embedded system built-in trace and debug facility

High-integration processors are hiding a lot of vital information from real-time, embedded systems developers. What you need is a black-box recorder to give much better insight into what the system is doing. This article discusses the evolution of debug peripherals which allow designs to be put in a black box. With complete trace and modification functionality, it is possible to create a trace buffer that allows the state of a system to be observed at any point during execution. With a comprehensive view of the complete state of the system when it is halted, the trace can be used to reconstruct previous states accurately. That enables you to find your customers' intermittent bugs by simply connecting up to their trace storage tool.

Supporting JAsCo AOP By Means of Eclipse

In this tool demonstration paper, we present a plugin for the Eclipse tool platform which provides support for JAsCo. JAsCo is a dynamic AOP language focused at component-based software engineering. The JAsCo Eclipse plugin provides a visual integrated development environment for JAsCo that guides developers to program JAsCo artifacts using visual wizards. The plugin also supports running JAsCo enabled applications and offers an extensive range of debugging and introspection facilities.

Debug Facilities in the TriMedia CPU64 Architecture

This paper describes debug facilities in the Philips TriMedia CPU64, which is an embedded processor core for multimedia applications. Its architecture provides a VLIW pipeline, support for 64-bit v...

Automatic distribution of reactive systems for asynchronous networks of processors

The paper addresses the problem of automatically distributing reactive systems. We first show that the use of synchronous languages allows a natural parallel description of such systems, regardless of any distribution problems. Then, a desired distribution can be easily specified, and achieved with the algorithm presented here. This distribution technique provides distributed programs with the same safety, test, and debug facilities as ordinary sequential programs. Finally, the implementation of such distributed programs only requires a very simple communication protocol ("first in first out" queues), thereby reducing the need for large distributed real time executives.

Visualization of geometric algorithms

Investigates the visualization of geometric algorithms. We discuss how limiting the domain makes it possible to create a system that enables others to use it easily. Knowledge about the domain can be very helpful in building a system which automates large parts of the user's task. A system can be designed to isolate the user from any concern about how graphics is done. The application need only specify "what" happens and need not be concerned with "how" to make it happen on the screen. We develop a conceptual model and a framework for experimenting with it. We also present a system, GASP (Geometric Animation System, Princeton), which implements this model. GASP allows quick generation of 3D geometric algorithm visualizations, even for highly complex algorithms. It also provides a visual debugging facility for geometric computing. We show the utility of GASP by presenting a variety of examples.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

OPIUM

Opium is an extensible debugging environment for PROLOG providing high-level debugging facilities for programmers and debugging experts.

OPIUM: a debugging environment for Prolog development and debugging research

Opium is an extensible debugging environment for PROLOG providing high-level debugging facilities for programmers and debugging experts.

Discrete event simulation in C with DISC

The creation of complex simulation models requires the capabilities of a good analyst/programmer and the support of a truly versatile and powerful simulation language. The migration of computing from mainframes to microcomputers and the growth of the capacity and speed of microcomputing present convincing arguments for the development and use of a simulation “language” which is compatible with microcomputer implementation. DISC ( DIscrete event Simulation in C) is a software library of C functions with supports the development of discrete event simulation models with event routines coded in C in a manner analogous to the use of SLAM or SIMAN with FORTRAN. The primary advantages of using C and DISC are dynamic memory management, an interactive execution environment, an interactive trace and powerful debugging facility, flexible input-output features, small code sizes and faster execution.

High-level debugging in parasight

Debugging parallel programs with time critical dependencies is difficult due to subtle race conditions that may cause deadlock, starvation, and other errors. These errors can be detected by multiple instrumentation points triggered by logical assertions. Although some advanced debuggers provide a programmer with the ability to define complex logical assertions, they are inadequate for debugging parallel programs due to the high overhead of monitoring these assertions. This paper describes the facilities for high-level debugging in Parasight™ a parallel programming environment. In Parasight, high-level debugging facilities are implemented as separate programs that are linked dynamically to a target program. The target program is controlled by attaching these debugging programs to light-weight instrumentation points that are dynamically inserted and deleted. Different facilities of arbitrary complexity may be created to support high-level debugging. Parasight has been implemented on Multimax™ a shared-memory multiprocessor. It has been used for debugging and profiling “C” programs.

Hydra - an Implicit Partial Differential Equation Relaxation Stability Analysis Package

view Abstract Citations (5) References (14) Co-Reads Similar Papers Volume Content Graphics Metrics Export Citation NASA/ADS Hydra - an Implicit Partial Differential Equation Relaxation Stability Analysis Package Stellingwerf, R. F. Abstract A brief description is given of HYDRA, a numerical analysis code designed to provide a rather complete analysis of many difficult problems often encountered in astrophysical contexts. The primary use for this system is the solution of implicit partial differential equations. Given the difference equations and a trial solution, options include (1) forward time integration, (2) relaxation to steady state, (3) stability of steady state and time evolution, (4) numerical stability check, and (5) driven oscillations. Extensive input/output and debug facilities are provided, including dump/restart, variable plots, and initialization from a given state with an eigenvector perturbation. Generalization to solve global problems such as computations of periodic solutions and their stability is straightforward. Publication: The Astrophysical Journal Pub Date: August 1983 DOI: 10.1086/161253 Bibcode: 1983ApJ...271..876S full text sources ADS |

Emu: a multiprocessor software debugging tool

The paper describes a multiprocessor software debugging facility available on the UMIST multimicroprocessor research system. Design considerations and concepts not found in uniprocessor debugging systems are described

Emu: a multiprocessor software debugging tool

The paper describes a multiprocessor software debugging facility available on the UMIST multimicroprocessor research system. Design considerations and concepts not found in uniprocessor debugging systems are described

An implementation of microdiagnostics on the ECLIPSE® MV/8000

The effectiveness of using a microcoded Independent Diagnostic Instruction Set for the development, manufacturing and field support of the 32-bit ECLIPSE® MV/8000 data processing system is demonstrated. A separate Diagnostic Processor with a simple operating system and microcode debugging facility is used to aid in this task.

An interactive debugging facility for GPSS

This paper describes the interactive debugging feature of GPSS/H (1), a new implementation of GPSS for IBM 360/370 computers. In GPSS/H, interactive debugging of a simulation model is carried out by means of a simple, but powerful command language. Commands are provided to selectively display model data on a terminal, to set breakpoints at arbitrary points in a model, and to step through a model one or more blocks at a time. An overview of the command language and an illustrative example of its use are presented in this paper.

Portable Microcomputer Cross-Assembler in BASIC

With the tremendous number of microprocessors on the market today it is becoming increasingly hard to find cross assemblers that run on the particular in-house computer system or timesharing service available. Since most minicomputer systems and almost all timesharing systems have BASIC interpreters or compilers available, this seems to be the most reasonable language choice for writing cross assemblers. It also has a very good trace and debug facility, which is especially useful if you are writing medium-long programs, such as cross-assemblers.