Dead Blocks Research Articles

Proactively Invalidating Dead Blocks to Enable Fast Writes in STT-MRAM Caches

Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising emerging memory technology for on-chip caches. It has a low read access time and low leakage power. Unfortunately, however, STT-MRAM suffers from its long write latency and high write energy consumption. This paper proposes a cache management technique called Proactive Invalidation (PROI) that proactively invalidates dead blocks in advance to enable fast writes in the STT-MRAM caches. Experimental evaluation shows that the proposed technique improves performance by 14% on average compared to the baseline STT-MRAM cache. This paper also proposes two optimization techniques called Proactive Invalidation-aware Data Encoding (PIDE) and Narrowness-aware Partial Write (NPW) to minimize the energy overheads of Proactive Invalidation. Experimental results demonstrate that the total energy consumption of the STT-MRAM cache with PROI is only 1.8% higher than the baseline when PROI is applied with PIDE and NPW.

Study on aerated concrete using steam curing test method

The Accumulation of warm and moisture in building walls plays an vital role in its upkeep and power conservation. Aerated Concrete block, an environmental material gives an anticipated result to building construction. Aerated Concrete can build light weight, eco-friendly, non-structural wall, reduced dead weight concrete blocks. Aerated Concrete is developed introducing aluminium powder which reacts with the calcium hydroxide on hydration of cement. Several curing test methods are done to find out the optimum dosage of aluminium content. The Aerated concrete blocks are pre-casted by mixing Portland cement, fly ash, GGBS, quarry dust, lime stone powder, water and aluminium powder.

Line-Coalescing DRAM Cache

Die-stacked DRAM has emerged as an effective approach to address the memory bandwidth wall as it offers much higher bandwidth than off-chip DRAM. It is typically used along with much larger off-chip DRAM to form a hybrid memory system with sufficient capacity and abundant bandwidth. Lots of research activities have been drawn to exploit the potentials of such memory systems. One of the approaches is to use Die-stacked DRAM as a cache of off-chip DRAM. Judicious mechanisms have been proposed to manage these on-chip DRAM caches with tailored line sizes, fetch sizes, replacement policies, and allocation mechanisms. One such example is Footprint Cache[16] which uses 2KB lines but populates each line with only referenced 64B blocks to avoid transferring dead blocks. Doing so significantly reduces the traffic between on-chip DRAM and off-chip DRAM.In this paper, we propose to extend the idea of Decoupled Sector Cache [32] to the DRAM Cache by allowing multiple sparsely populated lines to be coalesced and stored in one DRAM Cache line (we call it Line-Coalescing DRAM Cache (LCDC)). Our experimental results show that LCDC can effectively increase the utilization of on-chip DRAM and provide 16.7% performance boost over prior designs. In addition, it is orthogonal with many existing DRAM Cache techniques and can work with them to increase the performance improvement to 27.5% and achieve 89.1% of the performance of an ideal DRAM Cache design.

Addressing variability in reuse prediction for last-level caches

Last-Level Cache (LLC) represents the bulk of a modern CPU processor's transistor budget and is essential for application performance as LLC enables fast access to data in contrast to much slower main memory. However, applications with large working set size often exhibit streaming and/or thrashing access patterns at LLC. As a result, a large fraction of the LLC capacity is occupied by dead blocks that will not be referenced again, leading to inefficient utilization of the LLC capacity. To improve cache efficiency, the state-of-the-art cache management techniques employ prediction mechanisms that learn from the past access patterns with an aim to accurately identify as many dead blocks as possible. Once identified, dead blocks are evicted from LLC to make space for potentially high reuse cache blocks. In this thesis, we identify variability in the reuse behavior of cache blocks as the key limiting factor in maximizing cache efficiency for state-of-the-art predictive techniques. Variability in reuse prediction is inevitable due to numerous factors that are outside the control of LLC. The sources of variability include control-flow variation, speculative execution and contention from cores sharing the cache, among others. Variability in reuse prediction challenges existing techniques in reliably identifying the end of a block's useful lifetime, thus causing lower prediction accuracy, coverage, or both. To address this challenge, this thesis aims to design robust cache management mechanisms and policies for LLC in the face of variability in reuse prediction to minimize cache misses, while keeping the cost and complexity of the hardware implementation low. To that end, we propose two cache management techniques, one domain-agnostic and one domain-specialized, to improve cache efficiency by addressing variability in reuse prediction.

Small-LRU: A Hardware Efficient Hybrid Replacement Policy

Replacement policy plays a major role in improving the performance of the modern highly associative cache memo-ries. As the demand of data intensive application is increasing it is highly required that the size of the Last Level Cache (LLC) must be increased. Increasing the size of the LLC also increases the associativity of the cache. Modern LLCs are divided into multiple banks where each bank is a set-associative cache. The replacement policy implemented on such highly associative banks consume significant hardware (storage and area) overhead. Also the Least Recently Used (LRU) based replacement policy has an issue of dead blocks. A block in the cache is called dead, if the block is not used in the future before its eviction from the cache. In LRU policy, a dead block can not be remove early until it become LRU-block. So, we have proposed a replacement technique which is capable of removing dead block early with reduced hardware cost between 77% to 91% in comparison to baseline techniques. In this policy random replacement is used for 70% ways and LRU is applied for rest of the ways. The early eviction of dead blocks also improves the performance of the system by 5%.

Infection-Based Dead Page Prediction in Hybrid Memory Architecture

With the widespread use of cloud computing and the Internet, applications that require a large memory footprint, such as in-memory databases, have gained in popularity. These applications depend on a high capacity, reliable memory architecture. To achieve these two goals, hybrid memory that uses both DRAM and nonvolatile memory (NVM) provides benefits that include large capacity and nonvolatility. However, NVM is usually accompanied by high write latency and endurance problems. It is important to reduce NVM writes and improve the latency and lifetime of hybrid memory. One way to reduce NVM writes is to reduce dead pages that occupy DRAM and have not been accessed for a long time. When dead pages are removed from the memory, more space can be reserved for frequently accessed data, reducing DRAM misses and NVM writes. Currently, there are several dead block prediction techniques that can identify dead blocks and reduce miss rates at the cache level. However, they are not effective at the memory level because CPU memory accesses exhibit less locality when accesses are filtered by caches. To propose an application that is suitable at the memory level and to achieve a reduction in NVM writes, this paper proposes a simple but effective dead page predictor, called the infection-based dead page predictor (IDP), for the memory level. IDP uses the access counts of evicted pages to determine if nearby pages are also dead pages (i.e., other pages are infected by evicted pages). The simulation results show that compared to related work, the proposed predictor significantly reduces DRAM misses and enhances lifetime.

Global Dead-Block Management for Task-Parallel Programs

Task-parallel programs inefficiently utilize the cache hierarchy due to the presence of dead blocks in caches. Dead blocks may occupy cache space in multiple cache levels for a long time without providing any utility until they are finally evicted. Existing dead-block prediction schemes take decisions locally for each cache level and do not efficiently manage the entire cache hierarchy. This article introduces runtime-orchestrated global dead-block management , in which static and dynamic information about tasks available to the runtime system is used to effectively detect and manage dead blocks across the cache hierarchy. In the proposed global management schemes, static information (e.g., when tasks start/finish, and what data regions tasks produce/consume) is combined with dynamic information to detect when/where blocks become dead. When memory regions are deemed dead at some cache level(s), all the associated cache blocks are evicted from the corresponding level(s). We extend the cache controllers at both private and shared cache levels to use the aforementioned information to evict dead blocks. The article does an extensive evaluation of both inclusive and non-inclusive cache hierarchies and shows that the proposed global schemes outperform existing local dead-block management schemes.

A Dead Block Approach to Minimize Erase Operation in NAND Flash Memory

NAND flash memory is widely adopted in the various consumer electronic devices as storage media because of its characteristics like shock resistance, low cost, and energy efficiency. The main concern with the flash memory is its erase-than-write and read-write-asymmetric-speed constrain. In order to improve the performance of NAND flash memory, various techniques for management of write buffer cache (WBC) have been proposed. In this paper, we have proposed a WBC management technique which efficiently selects coldest and largest block as a victim and declares it as a dead block. Different from the existing approaches we have proposed eviction technique of selected victim block (dead block). Our proposed approach selects and evicts the dead block in such a manner that it minimizes erase operation, write operation, and increases hit ratio in WBC. The experimental results show that the dead block approach outperforms other approaches, i.e., BPLRU, cold and largest cluster policy, and Extended Unified ExLRU.

Data Backup Optimization for Nonvolatile SRAM in Energy Harvesting Sensor Nodes

Nonvolatile static random access memory (nvSRAM) has been widely investigated as a promising on-chip memory architecture in energy harvesting sensor nodes, due to zero standby power, resilience to power failures, and fast read/write operations. However, conventional approaches back up all data from static random access memory into nonvolatile memory when power failures happen. It leads to significant energy overhead and peak inrush current, which has a negative impact on the system performance and circuit reliability. This paper proposes a holistic data backup optimization to mitigate these problems in nvSRAM, consisting of a partial backup algorithm and a run-time adaptive write policy. A statistic dead-block predictor is employed to achieve dead block identification with trivial hardware overhead. An adaptive policy is used to switch between write-back and write-through strategy to reduce the rollback induced by backup failures. Experimental results show that the proposed scheme improves the performance by 4.6% on average while the backup power consumption and the inrush current are reduced by 38.1% and 54% on average compared to the full backup scheme. What is more, the backup capacitor size for energy buffer can be reduced by 40% on average under the same performance constraint.

Runtime-Assisted Global Cache Management for Task-Based Parallel Programs

Dead blocks are handled inefficiently in multi-level cache hierarchies because the decision as to whether a block is dead has to be taken locally at each cache level. This paper introduces runtime-assisted global cache management to quickly deem blocks dead across cache levels in the context of task-based parallel programs. The scheme is based on a cooperative hardware/software approach that leverages static and dynamic information about future data region reuse(s) available to runtime systems for task-based parallel programming models. We show that our proposed runtime-assisted global cache management approach outperforms previously proposed local dead-block management schemes for task-based parallel programs.

First description of a Lophelia pertusa reef complex in Atlantic Canada

For the first time, we describe a cold-water coral reef complex in Atlantic Canada, discovered at the shelf break, in the mouth of the Laurentian Channel. The study is based on underwater video and sidescan sonar. The reef complex covered an area of approximately 490×1300m, at 280–400m depth. It consisted of several small mounds (< 3m high) where the scleractinian Lophelia pertusa occurred as live colonies, dead blocks and skeletal rubble. On the mounds, a total of 67 live colonies occurred within 14 patches at 300–320m depth. Most of these (67%) were small (< 20cm high). Dead coral (rubble and blocks), dominated (88% of all coral observations). Extensive signs of damage by bottom-fishing gear were observed: broken and tilted coral colonies, over-turned boulders and lost fishing gear. Fisheries observer data indicated that the reef complex was subjected to heavy otter trawling annually between 1980 and 2000. In June 2004, a 15km2 conservation area excluding all bottom-fishing was established. Current bottom fisheries outside the closure include otter trawling for redfish and anchored longlines for halibut. Vessel monitoring system data indicate that the closure is generally respected by the fishing industry.

Feedback Learning Based Dead Write Termination for Energy Efficient STT‐RAM Caches

Spin-torque transfer RAM (STT-RAM) is a promising candidate to replace SRAM for larger Last level cache (LLC). However, it has long write latency and high write energy which diminish the benefit of adopting STT-RAM caches. A common observation for LLC is that a large number of cache blocks have never been referenced again before they are evicted. The write operations for these blocks, which we call dead writes, can be eliminated without incurring subsequent cache misses. To address this issue, a quantitative scheme called Feedback learning based dead write termination (FLDWT) is proposed to improve energy efficiency and performance of STT-RAM based LLC. FLDWT dynamically learns the block access behavior by using data reuse distance and data access frequency, and then classifies the blocks into dead blocks and live blocks. FLDWT terminates dead write block requests and improves the estimation accuracy via feedback information. Compared with STT-RAM baseline in the lastlevel caches, experimental results show that our scheme achieves energy reduction by 44.6% and performance improvement by 12% on average with negligible overhead.

Enhanced Approach for Cache Behaviour and Performance Evaluation

In previous research on cache replacement policies, have seen that a block usually becomes dead after some uses. By classifying the dead block and discarding them early, there are various policies have been used but still there are number of problems such as cache pollution, high cache miss rate and cache overhead existed which degrades the system performance. In this paper, a new approach for cache replacement policy has introduced which reduces the cache miss rate and cache overhead by using shared L2 level cache. In terms of less miss rate and good hit rate there is need to deploy effective replacement policies. Cache replacement techniques is one of the crucial design parameter that affects the overall processor performance and also become more important with current growing technological moves in the direction of high associative cache . Keywords: Cache pollution; Cache overhead; Cache miss rate; Cache replacement policy (LRU and LFU); Memory overhead;

Novel Block Matching Reduced Complexity Motion Estimation and Compensation Algorithm for Mobile Domain: DBTSSDS

Communication between ends have dramatically increased by the expansion in wired (Hard) and wireless networks (soft wire). The user end machines have constrained capability. The availability of power/computation capability/storage and processing buffer/registers along with display. This necessitate the processing or preprocessing of information before transmitting in processed, compressed form. The bottleneck is to transmit the data through the channel with constrained capacity, in error free and acceptable quality. The data is enormously increases with HD content further necessitate effective and vigorous video processing procedures to permit error free real-time encoding and decoding. The real-time conferencing and events generates large sets of data which demands maximum level of compression and very high quality of reception. Even though latest standards like 3G /4G/5G along with efficient coding techniques the available channel has significantly increased but still processing is needed to adjust and accommodate more information in terms of numbers and quality. Numerous methodology had been proposed for compressing the Video but Block Matching methodology(BM) remains the most acceptable. BM is also commonly known as Motion Estimation and compensation(ME) techniques had been utilized for reducing the computational complication of the coding process. BM algorithms is important for accomplishing the effectual and reasonable compression. The block matching algorithm dictates the total computation cost and actual bit budget. Lately various fast search algorithms for video coding have also been proposed. This paper presents a method built on the extension and adjustment of research work MTSSDS block matching algorithm. The proposed algorithm utilizes the concept of logical dead blocks. The projected algorithm is labeled as DBTSSDS which expands to include and manipulate Dead Block on Modified Three steps and Diamond Search (DS) Block Matching Algorithm for the active block based motion estimation for mobile domain. It has been found that from the original (3SS/TSS) and DS, the PSNR value (thus quality) has increased slightly and the significant lowering of computations and thus computation time (faster) has been reduced significantly. The investigational fallouts utilizing various video sequences with different environment are utilized for validating and equate the benefits of projected motion estimation technique.

LvtPPP: Live-Time Protected Pseudopartitioning of Multicore Shared Caches

Partition enforcement policy is essential in the cache partition, and its main function is to protect the lines and retain the cache quota of each core. This paper focuses online protection based on its generation time rather than the CPU core ID that it belongs to or the position of the replacement stack, where it is located. The basic idea is that when a line is live, it must be protected and retained in the cache; when the line is “dead,” it needs to be evicted as early as possible. Therefore, the live-time protected counter (LvtP, four bits) is augmented to trace the lines' live time. Moreover, dead blocks are predicted according to the access event sequence. This paper presents a pseudopartition approach-LvtPPP and proposes a two-cascade victim selection mechanism to alleviate dead blocks based on the LRU replacement policy and the LvtP counter. LvtPPP also supports flexible handling of allocation deviation by introducing a parameter λ to adjust the generation time of the line. There is significant improvement of the performance and fairness in LvtPPP over PIPP and UCP according to the evaluation results based on Simics.

Zombie memory: Extending memory lifetime by reviving dead blocks

Zombie is an endurance management framework that enables a variety of error correction mechanisms to extend the lifetimes of memories that suffer from bit failures caused by wearout, such as phase-change memory (PCM). Zombie supports both single-level cell (SLC) and multi-level cell (MLC) variants. It extends the lifetime of blocks in working memory pages (primary blocks) by pairing them with spare blocks, i.e., working blocks in pages that have been disabled due to exhaustion of a single block's error correction resources, which would be 'dead' otherwise. Spare blocks adaptively provide error correction resources to primary blocks as failures accumulate over time. This reduces the waste caused by early block failures, making working blocks in discarded pages a useful resource. Even though we use PCM as the target technology, Zombie applies to any memory technology that suffers stuck-at cell failures. This paper describes the Zombie framework, a combination of two new error correction mechanisms (ZombieXOR for SLC and ZombieMLC for MLC) and the extension of two previously proposed SLC mechanisms (ZombieECP and ZombieERC). The result is a 58% to 92% improvement in endurance for Zombie SLC memory and an even more impressive 11x to 17x improvement for ZombieMLC, both with performance overheads of only 0.1% when memories using prior error correction mechanisms reach end of life.

ELF: Shared Cache Management through Eliminating Dead Blocks and Filtering Less Reused Lines

Modern CMP processors usually employ shared last-level cache(LLC) based on LRU replacement policy and its approximations.However,as the LLC grows in capacity and associativity,the performance gap between the LRU and the theoretical optimal replacement algorithms has widened.Various alternative cache management technologies have been proposed to resolve this problem,but they only cover a single type of memory access behavior,and exploit little frequency information of cache accesses,thus have limited performance benefits.In this paper,we propose a unified cache management policy ELF which can cover a variety of memory behaviors and exploit both recency and frequency information of a program simultaneously.Motivatedbythe observation that cache blocks often exhibit a small number of uses during their life time in the LLC,ELF is designed to(1) predict dead lines through a counter-based mechanism and evict them early,(2) filter less reused blocks through dynamic insertion and promotion policies.Thereby,the potentially live blocks are retained and most of the working set keeps undisturbed in the ELF managed L2 cache.Our evaluation on 4-way CMPs shows that ELF improves the overall performance by 14.5% on average over the LRU policy,and the performance benefit of ELF is 1.06x compared to PIPP and 1.09x compared to TADIP.

Efficient extraction and analysis of preprocessor-based variability

The C Preprocessor (CPP) is the tool of choice for the implementation of variability in many large-scale configurable software projects. Linux, probably the most-configurable piece of software ever, employs more than 10,000 preprocessor variables for this purpose. However, this de-facto variability tends to be "hidden in the code"; which on the long term leads to variability defects, such as dead code or inconsistencies with respect to the intended (modeled) variability of the software. This calls for tool support for the efficient extraction of (and reasoning over) CPP-based variability. We suggest a novel approach to extract CPP-based variability. Our tool transforms CPP-based variability in O(n) complexity into a propositional formula that "mimics" all valid effects of conditional compilation and can be analyzed with standard SAT or BDD packages. Our evaluation results demonstrate the scalability and practicability of the approach. A dead-block-analysis on the complete Linux source tree takes less than 30 minutes; we thereby have revealed 60 dead blocks, 2 of which meanwhile have been confirmed as new (and long-lasting) bugs; the rest is still under investigation.

Attraction of pinewood nematode, Bursaphelenchus xylophilus, to the endoparasitic fungus Esteya vermicola

The investigations on attraction of nematodes to nematophagous fungi have mostly dealt with the nematode-trapping species and just were limited to the assays on plate. In present study, attraction of pinewood nematodes to the living mycelia ofendoparasitic fungus, Esteya vermicola, was investigated. It was confirmed that the living mycelia of E. vermicola were attractive not only to pinewood nematodes on plate, but also to that in the discs of infected pine seedling, dead blocks of infected pine tree, 15 and 30 days infected pine seedlings. Moreover, the volatiles released byE. vermicola also were attractive to pinewood nematodes in 15 and 30 days infected pine seedlings. This study may provide information for the application of E. vermicolaas biological control agent of pinewood nematode. Key words: Esteya vermicola, pinewood nematode, Bursaphelenchus xylophilus,Pinus densiflora, living mycelia, attraction, volatiles.

Evolution of texture and strain states in AA 3004 sheet during rolling with a dead block

Aluminum alloy AA 3004 strips were deformed by rolling together with a hard non-deforming steel slab to investigate the evolution of strain states and, in particular, shear strains during rolling with a dead block. The strain states at various through-thickness layers were analyzed by measurements of crystallographic texture and microhardness as well as by simulations with the finite element method (FEM). After rolling with the dead block the aluminum strip revealed pronounced through-thickness texture gradients. These texture gradients were modeled with the strain history extracted from the FEM data. At variance to the strain states prevailing in other techniques involving large shears, which give rise to quite uniform strain states comprised of unidirectional shear, the strain state obtained in a sheet rolled together with a dead block is akin to that observed in ordinarily rolled strip under high friction conditions.