DC Voltage Utilization Ratio Research Articles

RC-qTPWM method with high DC voltage utilization ratio and power balance for three-phase CHB inverters

RC-qTPWM method with high DC voltage utilization ratio and power balance for three-phase CHB inverters

A hybrid high‐efficiency nine‐level inverter with high DC voltage utilization ratio

AbstractThis paper proposes a new hybrid nine‐level inverter topology with high efficiency and high dc voltage utilization ratio, which provides a potential for renewable energy power conversion. The proposed inverter can synthesize up to nine voltage levels with only ten switching devices and a flying capacitor (FC). To improve the operation efficiency, a hybrid‐device topology based on Si and SiC is proposed. The total device cost of this inverter is much lower than the all‐SiC‐based inverter. Compared with other advanced multilevel inverters, a notable feature is the more comprehensive performance of the proposed inverter. In addition to having fewer components and higher efficiency, the dc voltage utilization ratio of the inverter is 2.5 times that of the traditional inverter such as Neutral Point Clamped (NPC), FC, and Active NPC (ANPC). A hybrid FC voltage balancing strategy based on redundancy switching states and three voltage levels step switching method is implemented to reduce FC voltage ripple. Besides, a cooperative voltage control strategy between the dc‐link capacitors and FC ensures the neutral‐point voltage balancing. The voltage stresses analysis and the design guidelines of components are discussed in detail. A comparison with some existing topologies has also been made to highlight its performance. Experimental results verify the validity of the proposed inverter topology and the control schemes.

Analysis and Arm Voltage Control of Isolated Modular Multilevel DC–DC Converter with Asymmetric Branch Impedance

Isolated modular multilevel dc–dc converter (IMMDCC), which consists of two modular multilevel converters and a medium-frequency transformer, is attractive for medium-voltage applications because of the following features: the modular structure can handle higher voltage, and synthesizing square-wave voltages toward the alternating current (ac) link increases the dc voltage utilization ratio and achieves the zero-voltage switching operation. However, the asymmetry of arm impedance in practice inevitably leads to power imbalance and divergence of total capacitor voltages in the upper and lower arms of IMMDCC, thereby inducing large ripples in the common-mode arm current and adding a dc bias to the synthesized ac voltage. To compensate for the power imbalance and maintain the stable operation, the interarm phase-shift modulation (IAPSM) scheme and arm voltage-balancing control strategy based on this scheme are presented in this paper. Combining the IAPSM scheme with the intersubmodule phase-shift modulation scheme, deep rising and falling edges of the synthesized square-wave voltage in each phase leg are modified into staircase waveforms with 2 N + 1 steps, dv/dt in the ac-link is thus significantly reduced. Simulation and experimental results validate the theoretical analysis and control strategy.

Novel Carrier-Based PWM Strategy of a Three-Level NPC Voltage Source Converter without Low-Frequency Voltage Oscillation in the Neutral Point

A novel carrier-based PWM (CBPWM) strategy of a three-level NPC converter is proposed in this paper. The novel strategy can eliminate the low-frequency neutral point (NP) voltage oscillation under the entire modulation index and full power factor. The basic principle of the novel strategy is introduced. The internal modulation wave relationship between the novel CBPWM strategy and traditional SPWM strategy is also studied. All 64 modulation wave solutions of the CBPWM strategy are derived. Furthermore, the proposed CBPWM strategy is compared with traditional SPWM strategy regarding the output phase voltage THD characteristics, DC voltage utilization ratio, and device switching losses. Comparison results show that the proposed strategy does not cause NP voltage oscillation. As a result, no low-frequency harmonics occur on output line-to-line voltage and phase current. The novel strategy also has higher DC voltage utilization ratio (15.47% higher than that of SPWM strategy), whereas it causes larger device switching losses (4/3 times of SPWM strategy). The effectiveness of the proposed modulation strategy is verified by simulation and experiment results.

HARDWARE-RESOURCE SAVING FOR REALIZATION OF SPACE VECTOR PWM BASED ON FPGA USING BUS-CLAMPING TECHNIQUE

The space vector pulse width modulation (SV-PWM) is more suitable and can increase the obtainable DC voltage utilization ratio very much compared to others PWM. Moreover, the modulation can obtain a better voltage total harmonic distortion (THD) factor. But until now, no studies that concern at hardware resources saving to realize SV-PWM based on FPGA. This paper proposes a new technique to realize SV-PWM based on FPGA. In order to get hardware resource saving, a simple technique to judge sectors, to calculate the firing pulses and to generate SV-PWM waveform without calculation of trigonometric function using bus-clamping technique is proposed. The technique has been implemented successfully based on APEX20KE FPGA to drive three phase induction machine 1.5 kW with low ripples in current and voltage, and has been shown that the proposed SVM method required the most minimum hardware resources compared to others research.