DC-link Voltage Imbalance Research Articles

Differential-Mode Filters With Common-Mode Neutral-Point-Balancing Accelerators for Single-Phase Symmetrical Five-Level Converters

Single-phase symmetrical five-level converter offers a low-harmonic power interface, whose attractiveness is nevertheless affected by dc-link voltage imbalance. Fast rebalancing methods have therefore been proposed, if the natural balancing speed of the converter is intolerable. One possible method is to add a separate parallel RLC branch between the converter and its filter. Being parallel, the branch does not change spectral properties of the converter and filtering properties of the filter, in addition to its robust sensor-less requirement. However, being separated, it does not properly integrate with the filter to explore dual usabilities of the components. This article therefore proposes a few differential-mode (DM) filters with each having a common-mode (CM) capacitor as the balancing accelerator. The accelerator does not conduct and hence consume no power during the normal balanced condition. It conducts only when an imbalance occurs and directs only those harmonics with fast balancing ability to the dc link. Its design is simple and can conveniently be performed with an appropriate CM harmonic model. Its performance has ultimately been verified by simulation and experimental results obtained with two different modulation schemes.

A Simplified Deadbeat Based Predictive Torque Control for Three-Level Simplified Neutral Point Clamped Inverter Fed IPMSM Drives Using SVM

This paper proposes a simplified deadbeat based predictive torque control (DB-PTC) for interior permanent magnet synchronous machine (IPMSM) drives using space vector modulation (SVM). The proposed DB-PTC is implemented in stationary reference frame, which simplifies the design. It contributes to greatly diminish the torque and flux ripples by using SVM and predictions. Low computational complexity is achieved since iterative optimization is not needed in the proposed method. Moreover, one cycle delay is compensated through predictions. In addition, to further reduce the torque and flux ripples, three-level simplified neutral point clamped inverter (3L-SNPCI) is employed. It features fewer switching devices and less DC-link capacitor voltage imbalance problem compared to the other types of three-level inverters. A novel SVM scheme is proposed to fully exploit the advantages of this inverter while ensuring smooth voltage vector transition. Experimental results are provided to verify the validity of the proposed method.

Reinforced Droop for Active Current Sharing in Parallel NPC Inverter for Islanded AC Microgrid Application

The paper investigates the current sharing in parallel 3-level Neutral point clamped inverter for islanded AC microgrid application. In Distributed generation, parallel power electronic interface based microgrid suffers from power quality issues due to inaccurate output current sharing. To address the current sharing problem, the paper proposes an improved droop technique that reinforces the droop loop by infusing the incurred voltage drop accountable for inaccurate current sharing at the inverter output. The control based on droop reference is bounded with regard to output current since the output impedance influences the output current of the inverter largely. Besides that, the parallel NPC inverter also suffers from dc link voltage imbalance due to neutral currents. To address these issues a control strategy is proposed in the research work in which the processed DC offset is incorporated into the reinforced droop loop and the generated reference is utilized with feedback control to accurately share the currents under linear and nonlinear load conditions. The effectiveness of devised reinforced droop strategy is realized in MATLAB/Simulink environment and experimental validation is carried out with the field-programmable gate array as hardware interface to the hardware laboratory prototype of parallel NPC inverter.

SVM Direct Torque and Flux Control of Three-Level Simplified Neutral Point Clamped Inverter Fed Interior PM Synchronous Motor Drives

The direct torque and flux control abandons the current control approach but instead regulates the stator flux and torque directly and independently. Consequently, excellent dynamic performance can be expected from the motor drive, making it attractive for low and medium voltage applications. This paper presents a direct torque and flux controlled interior permanent magnet synchronous motor driven from a three level simplified neutral point clamped inverter. This inverter features fewer switching devices and less dc-link capacitor voltage imbalance problems due to the absence of the medium voltage vectors. A novel space vector modulation algorithm is proposed to generate the reference voltage vector for control purposes while balancing the neutral point voltage. The experimental results included verify the effectiveness of the proposed approach.

Structure and the space vector modulation for a medium‐voltage power‐electronic‐transformer based on two seven‐level cascade H‐bridge inverters

This study presents the structure and the space vector pulse-width modulation (SVPWM) for power electronic transformer (PET) based on two seven-level cascade H-bridge (CHB) inverters. The DC links of CHB inverters are coupled with nine dual-active bridge (DAB) converters with medium-frequency transformers. The DC-link voltages are equalised with two methods - through the control of DAB voltages and through the modulation strategy applied to both CHB inverters. In the proposed SVPWM, the influence of vector sequences on predicted DC-link voltages is analysed, and the optimum vector sequence is selected to equalise them. Regardless of this, the proposed SVPWM strategy enables the proper generation of output voltage vector also in the case of DC-link voltage imbalance - the calculation of the space-vector area takes into consideration the inequality of the DC-link voltages and its influence on the lengths and positions of active vectors. To simplify the modulation algorithm, the multilevel CHB inverter is considered as a set of three-level inverters connected in series. Each of them is controlled using the same SVPWM algorithm. The proposed modulation method reuses the H-bridges with zero duty cycles determined in the initial stages of the output voltage generation process. This enables the optimal management of the DC-link voltage distribution. The experimental research was carried out on a 600 kW/3.3 kV PET. The results are presented in this study.

Model Predictive Control Methods for Three-Level Sparse Neutral Point Clamped Inverter

Three-level sparse neutral point clamped inverter is employed in this paper due to low harmonic, fewer switching devices, and less dc-link capacitor voltage imbalance problems. Model predictive control (MPC) methods are proposed to fully exploit the advantages of this inverter while ensuring neutral point voltage balance and maintaining low computational complexity. First, the desired voltage vector reference is constructed to realize reference current tracking based on the model of three-level sparse neutral point clamped inverter. Second, the n-type or the p-type small voltage vectors are carefully tuned to minimize the neutral-point (NP) voltage unbalance. Last, the voltage vectors that are far from the desired voltage vector reference are excluded in the cost function so as to reduce the computational burden. Therefore, only 5 effective voltage vectors instead of totally 13 voltage vectors are required in the implementation of the proposed fast MPC algorithm, which saves computational time up to 61.5%. Moreover, it compensates the one cycle digital delay through predictions. The performance of the proposed method has been validated by the simulation and experimental results.

Simultaneous Common-Mode Voltage Reduction and Neutral-Point Voltage Balance Scheme for the Quasi-Z-Source Three-Level T-Type Inverter

The conventional three-level inverter only has voltage buck capability. The quasi-Z-source three-level T-type inverter (QZS 3LT $^2$ I) has been proposed to realize voltage buck–boost operation. In this paper, we further propose a novel modulation scheme for the QZS 3LT $^2$ I to realize voltage boosting, reduce the common-mode voltage (CMV), and control the neutral-point voltage balance simultaneously. The proposed scheme adopts a large vector, a medium vector, a small vector with low CMV magnitude, a zero vector, and a shoot-through vector to generate the output voltage. According to sector number and neutral-point voltage difference, a p-type or n-type small vector with low CMV magnitude is properly selected to balance the neutral-point voltage. Shoot-through states are inserted within zero vector to boost the dc input voltage without affecting the ac output voltage. Dwell times of basic vectors are calculated through the revised volt–second balance equation. Furthermore, a coordinate control strategy between neutral-point voltage balance and voltage boosting is proposed. Doing so, the CMV magnitude can be restricted within one-sixth of dc-link voltage and neutral-point voltage imbalance can be effectively mitigated. The effectiveness of the proposed scheme is verified by simulations and experiments.

Application of Barycentric Coordinates in Space Vector PWM Computations

This paper proposes the use of barycentric coordinates in the development and implementation of space-vector pulse-width modulation (SVPWM) methods, especially for inverters with deformed space-vector diagrams. The proposed approach is capable of explicit calculation of vector duty cycles, independent of whether they assume ideal positions or are displaced due to the DC-link voltage imbalance. The use of barycentric coordinates also permits a well-defined and universal approach to the problem of identifying the region in which the reference vector is located. It completely avoids the use of angles, trigonometric functions, and inverse trigonometric functions and is chiefly based on matrix operations which are well suited for digital signal processor implementation. The proposed approach is exposed and validated for the special case of three-level neutral-point clamped (NPC) inverter controlled by a discontinuous space-vector PWM.

Voltage and Power Balance Strategy without Communication for a Modular Solid State Transformer Based on Adaptive Droop Control

Solid State Transformers (SST) are attracting considerable attention due to their great application potential in future smart grids. It is an essential technology capable of promoting the modernization of the electric power distribution system and it is considered a key element for interfacing future microgrid systems to medium voltage utility grids, allowing plug-and-play integration with multiple renewable energy sources, storage devices and DC power systems. Its main advantages in relation to conventional transformers are substantial reduction of volume and weight, fault isolation capability, voltage regulation, harmonic filtering, reactive power compensation and power factor correction. A three-stage modular cascaded topology has been considered as an adequate candidate for the SST implementation, consisting of multiple power modules with input series and output parallel connection. The modular structure presents many advantages, e.g., redundancy, flexibility, lower current harmonic content and voltage stress on the power switches, however component tolerances and mismatches between modules can lead to DC link voltage imbalance and unequal power sharing that can damage the solid state transformer. This paper proposes a decentralized strategy based on adaptive droop control capable of promoting voltage and power balance among modules of a modular cascaded SST, without relying on a communication network. The behavior of the proposed strategy is assessed through a MATLAB/Simulink simulation model of an 100 kVA SST and shows that power and voltage balance are attained through inner power distribution of the SST modules, being transparent to elements connected to the transformer input and output ports. Besides that, real-time simulation results are presented to validate the proposed control strategies. The performance of embedded algorithms is evaluated by the implementation of the SST in a real-time simulation hardware, using a Digital Signal Processor (DSP) and high level programming.

Design and Control of a 13.2 kV/10 kVA Single-Phase Solid-State-Transformer with 1.7 kV SiC Devices

This paper describes the power stage design, control, and performance evaluation of a 13.2 kV/10 kVA solid-state-transformer (SST) for a power distribution system. The proposed SST consists of 10 modules where each individual module contains a unidirectional three-level power factor correction (PFC) converter for the active-front-end (AFE) stage and an LLC resonant converter for the isolated DC-DC stage. The operating principles of the converters are analyzed and the modulation and the control schemes for the entire module are described in detail. The DC-link voltage imbalance is also less than other SST topologies due to the low number of uncontrollable switching states. In order to simplify the control of the power stage, a modulation strategy for the AFE stage is proposed, and the modulation frequency of the LLC converter is also fixed. In addition, a compensation algorithm is suggested to eliminate the current measurement offset in the AFE stage. The proposed SST achieves the unity power factor at the input AC current regardless of the reactive or nonlinear load and a low voltage regulation at the AC output. In order to verify the effectiveness of the SST, the 13.2 kV/10 kV SST prototype is built and tested. Both the simulation and the experimental results under actual 13.2 kV line show the excellent performance of the proposed SST scheme.

A Review of Multilevel Inverter Topology and Control Techniques

This paper focused on reviewing the main types of topologies and control strategies employed for the operation of multilevel inverter. Advantages and disadvantages of the topologies and the control techniques in relation to one another are equally reviewed. Recent proposed methods employed to improve the harmonic performance, reduce electromagnetic interference (EMI), lower stress on the power switches, eliminate DC link voltage imbalance and simplify the pulse width modulation control algorithms are fully reviewed. Selective harmonic elimination modulation technique is used in generating the 11-level of output voltage. It is aimed at reducing the total harmonic distortion as low as possible.

Failure-Mode Analysis and Protection of Three-Level Neutral-Point-Clamped PWM Voltage Source Converters

This paper presents the detection and protection methods uniquely associated with three-level neutral-point-clamped voltage source converters. The line-to-ground fault can cause significant dc-link neutral voltage and can therefore be effectively detected and located through monitoring the dc-link midpoint voltage without extra hardware. The inner device short in the three-level phase leg can lead to dc-link voltage imbalance and doubling the stress on capacitors and devices, which must be suppressed for the safe operation of the converter. Two overvoltage-limiting methods are proposed to limit the overvoltage. The design of both ground fault detection and overvoltage limiting has been covered in the paper. The schemes are verified through simulation and experiments.