Dc-link Capacitor Voltage Balance Research Articles

A Switched-Capacitor Multilevel Inverter With Modified Pulsewidth Modulation and Active DC-Link Capacitor Voltage Balancing

Although switched-capacitor (SC) multilevel inverters (MLIs) offer self-voltage balancing of flying capacitors and voltage gain higher than unity, the advantages come at the cost of high current stress and power loss in the SC circuit and DC source. Moreover, the voltage balancing is often restricted to a limited range of modulation index. Another problem of MLIs with neutral-point clamped (NPC) front end is with DC-link capacitor voltage balancing under unbalanced load conditions, imploring sensor-based closed-loop control. This paper proposes a unity gain five-level active-NPC SC-MLI with inrush charging current attenuation and actively balanced DC-link capacitor voltages under all load conditions and over the entire range of modulation index and power factor. The modified pulse-width modulation results in most switches operating at a low switching frequency, minimizing switching losses in the SC circuit. The proposed MLI attains a maximum efficiency of 98.04% at an output power of 510 W. Experiments on a 2 kVA laboratory prototype validate the theoretical analysis. Results from transformerless grid-connected solar PV system show that the proposed MLI can inject power into the grid with a unity power factor under conditions of varying irradiance and provide the grid with reactive power as well.

Topology and Hybrid Modulation of Six-Level Switched-Capacitor HC Converter With Improved DC-Link Capacitor Voltage Balancing

Topology and Hybrid Modulation of Six-Level Switched-Capacitor HC Converter With Improved DC-Link Capacitor Voltage Balancing

Zero-sequence controller requirements and comparison for a delta-CHB STATCOM under unbalanced operation

Delta-configured Cascaded H-Bridge (DCHB) topology is a suitable alternative for Static Synchronous Compensator (STATCOM) applications. However, under unbalanced voltage and/or current conditions, zero-sequence current needs to be injected to guarantee dc-link capacitor voltage balancing. The control loop of this zero-sequence current is analyzed in this paper, in order to determine the requirements that the implemented controller must fulfill. Considering these requirements, appropriate transient response and stability margin indicators are defined to quantify and evaluate the performance of different controllers that could be employed —Proportional-Resonant controller (PR), PR controller with delay compensation (PRd), and Vector Proportional-Integral controller (VPI) are proposed and analyzed for this application in this paper. Based on the defined indicators, the VPI is the most appropriate among the studied control techniques. Experimental results validate the analytical model of the controllers and their performance.

A Novel DC-Link Capacitor Voltage Balance Control Based on Coordination of Rectifier–Inverter Stage in a Modified Unidirectional Five-Level Converter for AC Motor Drives

A Novel DC-Link Capacitor Voltage Balance Control Based on Coordination of Rectifier–Inverter Stage in a Modified Unidirectional Five-Level Converter for AC Motor Drives

A Three-Phase Dual-Output T-Type Three-Level Converter

A novel three-phase dual-output T-type three-level converter (DO-T-TLC) topology is proposed in this article. The proposed topology has the dc-link and two sets of three-phase ac voltage output terminals. The topology of DO-T-TLC is introduced. Then, the operating principle of multiplexing switches and the available switching states of converter are analyzed, including current path, output phase voltage level, and blocking voltage of different switching states. The phase disposition pulsewidth modulation scheme with dc offsets is discussed in detail, and the key problems of the modulation scheme under both the common frequency and different frequency operation modes, such as voltage level selection, displacement angle constraint, and modulation index range, are studied. For the imbalance of two series capacitors in the dc-link, the mechanism is first revealed, and then a dc-link capacitor voltage balance method to control the average neutral point current is proposed. When DO-T-TLC is used in different operation modes, the ability and effect of this method to balance capacitor voltages are summarized. A low-power three-phase prototype is built, and the experimental results are given to verify the feasibility of the proposed topology and the effectiveness of the modulation scheme to control the voltage balance.

A Flexible Reactive Power Injection Method for DC-Link Capacitors Voltage Balancing in Back-to-Back Multilevel Converters

The dc-link capacitor voltage drift is the key technical problem of the converters with multi-intermediate nodes. The back-to-back (BTB) configuration with voltage balancing control can achieve a certain operation range. Nevertheless, the challenge of voltage drift still remains, especially when both sides operate at high but different modulation indexes and high power factors. This article focuses on a BTB seven-level V-clamp multilevel converter (VMC). The balanced operation limits are presented, and the effect of the power factor on balancing capability is analyzed. To maintain the voltage balancing of the dc-link capacitor under different operation conditions of the load (inverter side), a reactive power injection control is proposed in this article. Suitable reactive power is injected into the rectifier according to the balancing situation. The proposed control method can actively adjust the power factor of the rectifier to provide the required balancing capability. In this way, the dc-link capacitor voltage balancing is maintained within a larger operation range. In this article, a 10-kVA laboratory prototype of BTB seven-level VMC is set up to verify the effectiveness of the proposed control.

DC-Link Neutral Point Control for 3L-NPC Converters Utilizing Selective Harmonic Elimination–PWM

Selective harmonic elimination–pulsewidth modulation (SHE–PWM) is a modulation technique widely used to improve the efficiency and harmonic content in medium-voltage high-power converters. Among these converters, the three-level neutral-point-clamped (3L-NPC) converter is one of the most utilized topologies. However, the 3L-NPC converter requires a proper balancing of dc-link capacitor voltages. This article presents a control technique, based on pulse shifting method, to regulate the neutral point voltage when SHE-PWM is utilized. The proposed technique performs well with any power factor and it can also be directly applied to T-type converters and easily extrapolated to other multilevel topologies. The proposed method is experimentally validated in a scaled-down power converter and a full-scale medium-voltage 3L-NPC converter.

A Multilevel Inverter for Instantaneous Voltage Balancing of Single Sourced Stacked DC-Link Capacitors for an Induction Motor Load

This article proposes a novel nine-level multilevel inverter topology with an instantaneous voltage balancing scheme of stacked dc-link capacitors for an induction motor (IM) drive application. Three neutral points (NPs, terminal joints of four series-connected capacitors) across a single dc-link are balanced instantaneously (within a sampling interval) by ensuring zero current at the NPs. The proper selection of pole voltage from the redundancies provides zero current at any NP during the pulsewidth modulation operation under a steady-state and transient operation. A five-level stacked inverter and three cascaded hybrid-bridge (CHB) inverter cells are used in each phase. Along with the balancing of dc-link capacitors, CHB capacitors’ voltage balancing is also achieved using the pole voltage redundancies at all modulation indexes for all power factor and load. It is also possible to increase more number of levels using more low-voltage switches, and a generalized form of the topology is presented. The concept is validated using a laboratory-developed nine-level inverter with a three-phase IM load, operated under “V/ <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> ” control. The detailed experimental results for the steady and transient condition, simulation studies for switching loss, and harmonic content in the phase voltage are also presented.

A Simple Virtual-Vector-Based PWM Formulation for Multilevel Three-Phase Neutral-Point-Clamped DC–AC Converters including the Overmodulation Region

Neutral-point-clamped (NPC) power conversion topologies are among the most popular multilevel topologies in current industrial products and in industrial and academic research. The proper operation of multilevel three-phase NPC DC–AC converters requires the use of specific pulse-width modulation (PWM) strategies that maintain the DC-link capacitor voltage balance and concurrently optimize various performance factors such as efficiency and harmonic distortion. Although several such PWM strategies have been proposed in the literature, their formulation is often complex and/or covers only particular cases and operating conditions. This manuscript presents a simple formulation of the original virtual-vector-based PWM, which enables capacitor voltage balance in every switching cycle. The formulation is presented, for the general case, in terms of basic phase voltage modulating signals, with no reference to space vectors, involving any number of levels and for any operating conditions, including the overmodulation region. The equivalence of the presented formulation to the original PWM strategy is demonstrated through simulation under different scenarios and operating conditions. Thus, this manuscript offers in a one-stop source a simple, effective, and comprehensive PWM formulation to operate multilevel three-phase NPC DC–AC converters with any number of levels in any operating condition.

Model Predictive Control Scheme of a Four-Level Quasi-Nested Converter Fed AC-Drive, with dc-Link Voltage-Drift Compensation

In this paper, a Model Predictive Control (MPC) strategy is introduced for its application in a four-level quasi-nested topology, feeding an Interior Permanent Magnet Synchronous Machine (IPMSM) AC-drive. The proposed control strategy is capable to synthesize the required output space vectors to ensure perfect tracking of the AC-drive speed reference under different loading conditions, while also ensuring voltage balance between the dc-link capacitors. The proposed converter topology is based on a reduced number of components compared to other mature converter topologies, such as the neutral-point clamped converter (NPC) or the active neutral-point clamped converter (ANPC) topologies, when compared in terms of the number of output voltage levels, since this quasi-nested topology does not require passive clamping devices such as diodes or active switches. Moreover, no floating dc-link capacitors with asymmetrical voltage levels are employed, thus simplifying the dc-link capacitor voltage balance mechanism. This work presents the switching operation principles and MPC control law when supplying an IPMSM AC-drive load are addressed in detail. Simulation and validation results using a Hardware in the Loop (HIL) prototype under different operation conditions are presented in order to validate the proposed converter topology and control strategy.

A Dual Modulation Waveform PWM Combined With Phase-Shifted Carriers in Stacked Multicell Converter

This article proposes a hybrid dual modulation waveform pulsewidth modulation (DMW-PWM) strategy for 5L-SMC. The driver signals of each cell are generated by comparing dual modulating waves and two phase-shifted carriers, respectively. The voltage natural-balancing characteristic of both the floating capacitors and dc-link capacitors with the proposed DMW-PWM is derived. The proper active voltage balance control strategy is also presented to regulate the voltages of neutral point and floating capacitors. With this strategy, the voltage balancing of dc-link capacitors and floating capacitors is achieved simultaneously with the complete elimination of low-frequency ripples in neutral point. Compared with the conventional DMW-PWM method (also called the fast processing modulation method), the proposed method has a smaller voltage fluctuation in floating capacitors, better dynamic performance, lower switching frequency, and simply digital implementation. The superiority of the proposed method is verified by experimental results.

DC-Link Capacitor Voltage Balancing Control of a Five-Level Regenerative AC Electronic Load Using One-Cycle Control

High voltage electric power equipment requires rigorous regulation testing to specific standards which ensure proper and safe operation in the grid. Manufacturers conduct these tests in order to prove standard compliance and product liability. Variable linear or nonlinear loads are necessary for testing medium voltage (MV) high power AC power converters. Generally, those AC power converters or power supplies require performance validation, burn-in and/or lifetime testing under different load conditions, defined by the end-user or standards for the given applications. For flexible and efficient MV verification testing, this paper presents a five-level multilevel converter-based MV regenerative AC electronic load with one-cycle control (OCC), which is based on five-level diode-clamped multilevel converters with back-to-back structure and can emulate any impedance load. In this paper, especially the dc-link capacitor voltage balance of the proposed multilevel MV regenerative AC load is deeply analyzed. Simulation and experimental results are presented to verify the dc-link voltage balance performance of the proposed multilevel MV regenerative AC electronic load.

Enhanced Direct Torque Control for a Three-Level T-Type Inverter

Direct torque control (DTC) is a widely used approach for motor drives due to its distinctive advantages, e.g., fast dynamic response and highly robust against motor parameters uncertainties and external disturbances. To achieve a lower torque ripple, a higher switching frequency is usually required, which, however, can reduce the drive efficiency. Using the emerging silicon carbide (SiC) devices, which can operate efficiently at a much higher switching frequency than their silicon counterparts, thus, it could be feasible to achieve high efficiency and low torque ripple simultaneously. In this work, a novel multilevel DTC for a SiC T-type inverter is proposed to significantly reduce the torque and flux ripples while retaining the fast-dynamic response. The unbalanced dc-link is a common issue of the T-type inverter, which may also lead to a higher torque ripple. To address this issue, the proposed DTC algorithm only uses the real voltage space vectors and virtual space vectors (VSVs) that do not contribute to the neutral point current such that an inherent dc-link capacitor voltage balancing can be achieved without using any active dc-link voltage controls or additional dc-link voltage and/or current sensors. The feasibility and effectiveness of proposed methods are verified by using both simulation and experimental studies.

Study of Toroidal Core Multilimb Transformer (TCMLT) for High-Power DC Application

Multimodule isolated converters incorporating excellent features of galvanic isolation, bidirectional power flow, and simple control are widely adopted in medium-voltage (MV) high-power dc-dc applications. However, the converter size and dc-link capacitor voltage balancing are significant concerns in galvanically isolated cascaded dc-dc converters. This article proposes a new design of an integrated transformer implementing toroidal cores named toroidal core multilimb transformer (TCMLT), employed in a dc-dc modular isolated bidirectional dual-active-bridge (IB-DAB) resonant converter topology. The modular design structure of the proposed transformer can be conveniently constructed and implemented for more number of participating modules conforming the compactness constraint. Moreover, an external coupling winding is implemented in the TCMLT structure to resolve the dc-link voltage balancing issue. This coupling winding method substitutes the expensive complex control circuits, which consequently results in cost reduction and reliability enhancement. Besides, the reluctance model of the proposed structure is analyzed. Based on the reluctance model, a common mode-difference mode (CM-DM) electrical circuit is realized for the proposed scheme. Furthermore, unlike the conventional approach of implementing U, UI, and EI cores for multilimb transformer (MLT) structure with separate limbs, a synthesis method of TCMLT in toroidal form is proposed. The comparative study of the proposed design with the conventional U-core MLT confirms that the proposed TCMLT offers less leakage inductance with significant size reduction. Finally, to validate the efficacy of TCMLT, a three-limb laboratory-scale prototype is employed in a 6-kW cascaded IB-DAB resonant converter topology.

Improved DTC Technique for THL-NPC VSI fed Five Phase Induction Motor Drive Based on VVs Assessment Over a Wide Speed Range.

A three-level neutral point clamped voltage source inverter fed five-phase induction motor (FPIM) drive is assessed by analyzing common-mode voltage (CMV). The presence of CMV leads to motor bearing fault and phase winding insulation failure due to additional voltage stress. To nullify the effect of CMV, this article proposes a modified direct torque control (DTC) based on the virtual vector (VV) concept. The proposed DTC utilizes the appropriate nonvertex voltage vectors to form VVs that neutralize the average volt-second in the $xy$ plane, maintain dc-link capacitor voltage balancing, and limits the switching voltage stress. The theoretical analysis is carried out to investigate the VVs effect on change in flux and torque response. Based on this assessment, a modified lookup table is designed for a wide range of speed operations. For the low-speed operation, i.e., below 25% of rated speed, the small VVs provide better drive performance instead of zero VV. The proposed DTC method is verified at steady-state and dynamic conditions through experimental investigations. Comparative results are provided for the assessment of the proposed DTC method in comparison to existed methods. It is concluded from the findings that the proposed DTC method is a promising approach to improving FPIM performance at high- and low-speed operations with zero CMV output.

Carrier-based Closed-loop DC-link Voltage Balancing Algorithm for Four Level NPC Converters Based on Redundant Level Modulation

Four-level neutral-point-clamped (NPC) multilevel converter topologies have been proposed and actively studied for low/medium voltage applications. As an inherent issue with these topologies, the voltage balancing of dc-link capacitors is challenging, especially when it operates as a single-end inverter/rectifier with high power factors and high modulation indexes. This article proposes a closed-loop voltage balancing algorithm that is effective and simple to implement with regular level-shifted carriers for a four-level NPC converter, e.g., a π-type converter. This approach is based on the redundant level modulation (RLM), which utilizes one additional voltage level in one switching cycle to gain extra controllability of the capacitor voltages without distorting/undermining the fundamental-frequency output voltage. An algorithm based on analytical expressions and logical operations is developed to achieve a dynamic closed-loop voltage balancing with RLM. The proposed method is effective over the full span of linear modulation indexes (M = 0 ~ 1.15) and power factors. The proposed algorithm is validated and evaluated in both simulations and experiments.

Novel multi‐level inverters with flyback high frequency link

A novel topological family of multi-level inverters with flyback high frequency link is proposed in this study. The inverters can transfer high DC voltage into regulated sinusoidal voltage with low total harmonic distortion (THD). The circuit configuration consists of high DC input voltage, DC-link capacitors, novel multi-level conversion unit, high frequency flyback transformer, cyclo-converter, output filter capacitor and AC load. This topological family includes diode-clamp type full-wave mode, hybrid-clamp half-bridge mode, multi-end mode and improved multi-end mode. To achieve reliable multi-level inversion and overcome DC-link capacitor voltages unbalance, multi-carrier modulation and DC-link capacitor voltage balancing strategy are presented. In addition, steady principle and AC small-signal model are analysed. Simulation and experimental results are given to prove that the novel flyback high frequency isolated multi-level inverters have the following advantages such as the high frequency electrical isolation, the bi-directional power flow, the two-stage power conversion (DC-high frequency AC (HFAC) - low frequency AC (LFAC)), the lower voltage stress of power switches and the low THD of output voltage.

Two-Stage Optimization-Based Model Predictive Control of 5L-ANPC Converter-Fed PMSM Drives

Balancing the dc-link voltage and three flying-capacitor (FC) voltages while maintaining very fast control of the motor is always a challenging task in five-level active neutral-point-clamped (5L-ANPC) converter-fed permanent-magnet synchronous motor drives, especially when the FC is small. Besides, the fundamental-frequency operation of the low-frequency cell (LFC) is also required to reduce the losses of the converter. This article proposed a two-stage optimization-based model predictive control (MPC) scheme to achieve these goals. In the first stage, the switching states of the LFC are selected based on the sign of the desired output voltage through a deadbeat approach for its fundamental-frequency operation; in the second stage, the optimal duty cycles for the high-frequency cell are calculated by the multiple-vector MPC and generated by phase-shifted pulsewidth modulation for its fixed-switching frequency operation. The FC and dc-link capacitor voltage balance can be managed by the flexibility of the inherent redundancy in the 5L-ANPC converter. Instead of 512, only six switching vectors must be considered, which significantly simplifies the computational burden of MPC. A thorough experimental evaluation has been conducted to validate the effectiveness of the proposed MPC method.

Dc‐link capacitor voltage control for the NPC three‐level inverter with a newly MPC‐based virtual vector modulation

Dc-link capacitor voltage unbalance would affect the performance of the neutral-point clamped (NPC) three-level inverter. With the traditional virtual space vector modulation (VSVPWM) method, the dc-link capacitor voltage could be kept balance under the different modulation indexes or power factors. With the virtual medium vector being set as an adjustable one, the voltage balance could be better guaranteed no matter there might have some non-linear factors However, whether the traditional or improved VSVPWM method has a complicated trigonometric calculation, thus, a newly MPC-based virtual vector modulation has been proposed in this paper. With the 19 virtual space vectors being in roll optimisation, a nice current trajectory, dc-link capacitor voltage balance, even a relative low switch losses have been implemented. Considering that the optimised virtual space vector could not be taken as a direct output, the distribution of the basic vectors has been generated to make it being favourable for modulation. The effectiveness of this MPC-based virtual vector modulation is verified in comparisons with other methods, which can save over 67.3% execution time of the traditional SVPWM method, and over 46.6% of the improved VSVPWM way while provide a better dc-link capacitor voltage balance and output current quality.

MPC Algorithm With Reduced Computational Burden and Fixed Switching Spectrum for a Multilevel Inverter in a Photovoltaic System

Renewable energy has gained significant attention of researchers in the last years, mainly due to the importance of using unlimited energy sources to supply homes, industries, cities and countries. In this context, this document focuses on the solar injection by employing a neutral point clamped (NPC) topology together with utilization of a maximum power point tracking (MPPT) and space vector modulation (SVM) techniques. Model predictive control (MPC) is employed to manage the currents and track their references. The proposed algorithms do not employ a cost function to decide which voltage to apply resulting in a spread frequency spectrum, and instead, a concentrated SVM spectrum is imposed. Notwithstanding, the DC link capacitors voltage balance is ensured and the computational burden is notably reduced as compared to traditional Finite Set Model Predictive Control (FS-MPC). Nevertheless, the consistent results are a consequence of the critical analysis that shows the feasibility of the proposal and guarantees the good performance of the entire system in simulated and experimental platforms.